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dev: seperate legacy io offsets from PCI offset

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The PC platform has a single IO range that is used both legacy IO and PCI IO
while other platforms may use seperate regions. Provide another mechanism to
configure the legacy IO base address range and set it to the PCI IO address
range for x86.
This commit is contained in:
Ali Saidi 2014-09-03 07:43:06 -04:00
parent 1c0ae90027
commit 346fe73370
3 changed files with 3 additions and 1 deletions
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1
src/dev/Pci.py
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@ -98,6 +98,7 @@ class PciDevice(DmaDevice):
BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO")
CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
SubsystemID = Param.UInt16(0x00, "Subsystem ID")

2
src/dev/pcidev.cc
View file

@ -213,7 +213,7 @@ PciDevice::PciDevice(const Params *p)
for (int i = 0; i < 6; ++i) {
if (legacyIO[i]) {
BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i]));
BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]);
config.baseAddr[i] = 0;
} else {
BARAddrs[i] = 0;

1
src/dev/x86/SouthBridge.py
View file

@ -84,6 +84,7 @@ class SouthBridge(SimObject):
ide.ProgIF = 0x80
ide.InterruptLine = 14
ide.InterruptPin = 1
ide.LegacyIOBase = x86IOAddress(0)
def attachIO(self, bus, dma_ports):
# Route interupt signals