.. |
bios
|
style: fix missing spaces in control statements
|
2016-02-06 17:21:19 -08:00 |
insts
|
x86: revamp cmpxchg8b/cmpxchg16b implementation
|
2016-02-06 17:21:20 -08:00 |
isa
|
x86: revamp cmpxchg8b/cmpxchg16b implementation
|
2016-02-06 17:21:20 -08:00 |
linux
|
syscall_emul: fix bugs for mmap2 system call and x86-32 syscalls
|
2016-03-17 10:25:53 -07:00 |
regs
|
x86: create function to check miscreg validity
|
2016-02-06 17:21:20 -08:00 |
cpuid.cc
|
style: fix missing spaces in control statements
|
2016-02-06 17:21:19 -08:00 |
cpuid.hh
|
scons: Add warning for missing declarations
|
2013-02-19 05:56:07 -05:00 |
decoder.cc
|
style: fix missing spaces in control statements
|
2016-02-06 17:21:19 -08:00 |
decoder.hh
|
misc: Remove redundant compiler-specific defines
|
2015-10-12 04:07:59 -04:00 |
decoder_tables.cc
|
x86: decode instructions with vex prefix
|
2015-07-17 11:31:22 -05:00 |
emulenv.cc
|
CPU: Merge the predecoder and decoder.
|
2012-05-26 13:44:46 -07:00 |
emulenv.hh
|
gcc: Clean-up of non-C++0x compliant code, first steps
|
2012-03-19 06:36:09 -04:00 |
faults.cc
|
style: remove trailing whitespace
|
2016-02-06 17:21:18 -08:00 |
faults.hh
|
x86: Invalidating TLB entry on page fault
|
2015-11-16 05:08:54 -06:00 |
interrupts.cc
|
cpu,isa,mem: Add per-thread wakeup logic
|
2015-09-30 11:14:19 -05:00 |
interrupts.hh
|
x86: Add missing explicit overrides for X86 devices
|
2015-10-23 09:51:12 -04:00 |
intmessage.hh
|
MEM: Remove the Broadcast destination from the packet
|
2012-04-14 05:45:55 -04:00 |
isa.cc
|
x86: create function to check miscreg validity
|
2016-02-06 17:21:20 -08:00 |
isa.hh
|
misc: Remove redundant compiler-specific defines
|
2015-10-12 04:07:59 -04:00 |
isa_traits.hh
|
x86: decode instructions with vex prefix
|
2015-07-17 11:31:22 -05:00 |
kernel_stats.hh
|
copyright: Change HP copyright on x86 code to be more friendly
|
2010-05-23 22:44:15 -07:00 |
ldstflags.hh
|
arch,x86,mem: Dynamically determine the ISA for Ruby store check
|
2014-10-16 05:49:44 -04:00 |
locked_mem.hh
|
cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
|
2014-01-24 15:29:30 -06:00 |
memhelpers.hh
|
arch, x86: add support for arrays as memory operands
|
2016-02-06 17:21:20 -08:00 |
microcode_rom.hh
|
includes: sort all includes
|
2011-04-15 10:44:06 -07:00 |
mmapped_ipr.hh
|
arch: Add support for m5ops using mmapped IPRs
|
2013-09-30 12:20:43 +02:00 |
nativetrace.cc
|
style: fix missing spaces in control statements
|
2016-02-06 17:21:19 -08:00 |
nativetrace.hh
|
Make commenting on close namespace brackets consistent.
|
2011-01-03 14:35:43 -08:00 |
pagetable.cc
|
sim: Refactor the serialization base class
|
2015-07-07 09:51:03 +01:00 |
pagetable.hh
|
misc: Remove redundant compiler-specific defines
|
2015-10-12 04:07:59 -04:00 |
pagetable_walker.cc
|
style: fix missing spaces in control statements
|
2016-02-06 17:21:19 -08:00 |
pagetable_walker.hh
|
arch, cpu: Do not forward snoops to table walker
|
2015-05-05 03:22:27 -04:00 |
process.cc
|
syscall_emul: fix bugs for mmap2 system call and x86-32 syscalls
|
2016-03-17 10:25:53 -07:00 |
process.hh
|
style: remove trailing whitespace
|
2016-02-06 17:21:18 -08:00 |
pseudo_inst.cc
|
kvm, x86: Adding support for SE mode execution
|
2014-11-23 18:01:08 -08:00 |
pseudo_inst.hh
|
kvm, x86: Adding support for SE mode execution
|
2014-11-23 18:01:08 -08:00 |
registers.hh
|
arch: get rid of unused LargestRead typedef
|
2016-01-17 18:27:46 -08:00 |
remote_gdb.cc
|
arm: remote GDB: rationalize structure of register offsets
|
2015-12-18 15:12:07 -06:00 |
remote_gdb.hh
|
arm: remote GDB: rationalize structure of register offsets
|
2015-12-18 15:12:07 -06:00 |
SConscript
|
kvm, x86: Adding support for SE mode execution
|
2014-11-23 18:01:08 -08:00 |
SConsopts
|
copyright: This file need not have had the more restrictive copyright.
|
2009-02-09 20:10:15 -08:00 |
stacktrace.cc
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
stacktrace.hh
|
arch: Use const StaticInstPtr references where possible
|
2014-09-27 09:08:36 -04:00 |
system.cc
|
x86: Segment initialization to support KvmCPU in SE
|
2014-11-23 18:01:08 -08:00 |
system.hh
|
x86: Segment initialization to support KvmCPU in SE
|
2014-11-23 18:01:08 -08:00 |
tlb.cc
|
sim: Refactor the serialization base class
|
2015-07-07 09:51:03 +01:00 |
tlb.hh
|
x86: Add missing explicit overrides for X86 devices
|
2015-10-23 09:51:12 -04:00 |
types.cc
|
x86: decode instructions with vex prefix
|
2015-07-17 11:31:22 -05:00 |
types.hh
|
style: fix missing spaces in control statements
|
2016-02-06 17:21:19 -08:00 |
utility.cc
|
x86: create function to check miscreg validity
|
2016-02-06 17:21:20 -08:00 |
utility.hh
|
misc: Remove redundant compiler-specific defines
|
2015-10-12 04:07:59 -04:00 |
vtophys.cc
|
arch: Use shared_ptr for all Faults
|
2014-10-16 05:49:51 -04:00 |
vtophys.hh
|
gcc: Clean-up of non-C++0x compliant code, first steps
|
2012-03-19 06:36:09 -04:00 |
x86_traits.hh
|
arch/x86: add support for explicit CC register file
|
2013-10-15 14:22:44 -04:00 |
X86ISA.py
|
arch: Make the ISA class inherit from SimObject
|
2013-01-07 13:05:35 -05:00 |
X86LocalApic.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
X86NativeTrace.py
|
cpu: Put all CPU instruction tracers in a single file
|
2015-01-25 07:22:17 -05:00 |
X86System.py
|
sim: Include object header files in SWIG interfaces
|
2012-11-02 11:32:01 -05:00 |
X86TLB.py
|
x86: add tlb checkpointing
|
2013-08-07 14:51:17 -05:00 |