x86: Segment initialization to support KvmCPU in SE
This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts.
This commit is contained in:
Alexandru Dutu
parent
adbaa4dfde
commit
f743bdcb69
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@ -1,4 +1,5 @@
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/*
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* Copyright (c) 2014 Advanced Micro Devices, Inc.
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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@ -45,6 +46,7 @@
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#include "arch/x86/regs/segment.hh"
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#include "arch/x86/isa_traits.hh"
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#include "arch/x86/process.hh"
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#include "arch/x86/system.hh"
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#include "arch/x86/types.hh"
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#include "base/loader/elf_object.hh"
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#include "base/loader/object_file.hh"
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@ -52,6 +54,7 @@
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Stack.hh"
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#include "mem/multi_level_page_table.hh"
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#include "mem/page_table.hh"
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#include "sim/process_impl.hh"
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#include "sim/syscall_emul.hh"
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@ -183,73 +186,418 @@ X86_64LiveProcess::initState()
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initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
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vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
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for (int i = 0; i < contextIds.size(); i++) {
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ThreadContext * tc = system->getThreadContext(contextIds[i]);
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if (kvmInSE) {
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PortProxy physProxy = system->physProxy;
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SegAttr dataAttr = 0;
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dataAttr.dpl = 3;
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dataAttr.unusable = 0;
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dataAttr.defaultSize = 1;
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dataAttr.longMode = 1;
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dataAttr.avl = 0;
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dataAttr.granularity = 1;
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dataAttr.present = 1;
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dataAttr.type = 3;
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dataAttr.writable = 1;
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dataAttr.readable = 1;
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dataAttr.expandDown = 0;
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dataAttr.system = 1;
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/*
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* Set up the gdt.
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*/
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uint8_t numGDTEntries = 0;
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uint64_t nullDescriptor = 0;
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physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
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(uint8_t *)(&nullDescriptor), 8);
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numGDTEntries++;
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//Initialize the segment registers.
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for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
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tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
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tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
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tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
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SegDescriptor initDesc = 0;
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initDesc.type.codeOrData = 0; // code or data type
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initDesc.type.c = 0; // conforming
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initDesc.type.r = 1; // readable
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initDesc.dpl = 0; // privilege
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initDesc.p = 1; // present
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initDesc.l = 1; // longmode - 64 bit
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initDesc.d = 0; // operand size
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initDesc.g = 1; // granularity
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initDesc.s = 1; // system segment
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initDesc.limitHigh = 0xFFFF;
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initDesc.limitLow = 0xF;
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initDesc.baseHigh = 0x0;
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initDesc.baseLow = 0x0;
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//64 bit code segment
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SegDescriptor csLowPLDesc = initDesc;
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csLowPLDesc.type.codeOrData = 1;
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csLowPLDesc.dpl = 0;
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uint64_t csLowPLDescVal = csLowPLDesc;
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physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
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(uint8_t *)(&csLowPLDescVal), 8);
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numGDTEntries++;
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SegSelector csLowPL = 0;
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csLowPL.si = numGDTEntries - 1;
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csLowPL.rpl = 0;
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//64 bit data segment
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SegDescriptor dsLowPLDesc = initDesc;
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dsLowPLDesc.type.codeOrData = 0;
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dsLowPLDesc.dpl = 0;
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uint64_t dsLowPLDescVal = dsLowPLDesc;
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physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
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(uint8_t *)(&dsLowPLDescVal), 8);
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numGDTEntries++;
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SegSelector dsLowPL = 0;
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dsLowPL.si = numGDTEntries - 1;
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dsLowPL.rpl = 0;
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//64 bit data segment
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SegDescriptor dsDesc = initDesc;
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dsDesc.type.codeOrData = 0;
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dsDesc.dpl = 3;
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uint64_t dsDescVal = dsDesc;
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physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
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(uint8_t *)(&dsDescVal), 8);
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numGDTEntries++;
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SegSelector ds = 0;
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ds.si = numGDTEntries - 1;
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ds.rpl = 3;
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//64 bit code segment
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SegDescriptor csDesc = initDesc;
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csDesc.type.codeOrData = 1;
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csDesc.dpl = 3;
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uint64_t csDescVal = csDesc;
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physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
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(uint8_t *)(&csDescVal), 8);
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numGDTEntries++;
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SegSelector cs = 0;
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cs.si = numGDTEntries - 1;
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cs.rpl = 3;
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SegSelector scall = 0;
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scall.si = csLowPL.si;
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scall.rpl = 0;
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SegSelector sret = 0;
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sret.si = dsLowPL.si;
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sret.rpl = 3;
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/* In long mode the TSS has been extended to 16 Bytes */
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TSSlow TSSDescLow = 0;
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TSSDescLow.type = 0xB;
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TSSDescLow.dpl = 0; // Privelege level 0
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TSSDescLow.p = 1; // Present
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TSSDescLow.g = 1; // Page granularity
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TSSDescLow.limitHigh = 0xF;
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TSSDescLow.limitLow = 0xFFFF;
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TSSDescLow.baseLow = (((uint32_t)TSSVirtAddr) << 8) >> 8;
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TSSDescLow.baseHigh = (uint8_t)(((uint32_t)TSSVirtAddr) >> 24);
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TSShigh TSSDescHigh = 0;
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TSSDescHigh.base = (uint32_t)(TSSVirtAddr >> 32);
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struct TSSDesc {
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uint64_t low;
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uint64_t high;
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} tssDescVal = {TSSDescLow, TSSDescHigh};
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physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8,
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(uint8_t *)(&tssDescVal), sizeof(tssDescVal));
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numGDTEntries++;
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SegSelector tssSel = 0;
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tssSel.si = numGDTEntries - 1;
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uint64_t tss_base_addr = (TSSDescHigh.base << 32) | ((TSSDescLow.baseHigh << 24) | TSSDescLow.baseLow);
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uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16);
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SegAttr tss_attr = 0;
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tss_attr.type = TSSDescLow.type;
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tss_attr.dpl = TSSDescLow.dpl;
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tss_attr.present = TSSDescLow.p;
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tss_attr.granularity = TSSDescLow.g;
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tss_attr.unusable = 0;
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for (int i = 0; i < contextIds.size(); i++) {
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ThreadContext * tc = system->getThreadContext(contextIds[i]);
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tc->setMiscReg(MISCREG_CS, (MiscReg)cs);
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tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
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tc->setMiscReg(MISCREG_ES, (MiscReg)ds);
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tc->setMiscReg(MISCREG_FS, (MiscReg)ds);
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tc->setMiscReg(MISCREG_GS, (MiscReg)ds);
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tc->setMiscReg(MISCREG_SS, (MiscReg)ds);
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// LDT
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tc->setMiscReg(MISCREG_TSL, 0);
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SegAttr tslAttr = 0;
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tslAttr.present = 1;
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tslAttr.type = 2;
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tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
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tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
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tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
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tc->setMiscReg(MISCREG_TR, (MiscReg)tssSel);
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tc->setMiscReg(MISCREG_SEG_BASE(SYS_SEGMENT_REG_TR), tss_base_addr);
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tc->setMiscReg(MISCREG_SEG_EFF_BASE(SYS_SEGMENT_REG_TR), 0);
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tc->setMiscReg(MISCREG_SEG_LIMIT(SYS_SEGMENT_REG_TR), tss_limit);
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tc->setMiscReg(MISCREG_SEG_ATTR(SYS_SEGMENT_REG_TR), (MiscReg)tss_attr);
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//Start using longmode segments.
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installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
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installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
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installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
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installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
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installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
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installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
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Efer efer = 0;
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efer.sce = 1; // Enable system call extensions.
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efer.lme = 1; // Enable long mode.
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efer.lma = 1; // Activate long mode.
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efer.nxe = 0; // Enable nx support.
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efer.svme = 1; // Enable svm support for now.
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efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
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tc->setMiscReg(MISCREG_EFER, efer);
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//Set up the registers that describe the operating mode.
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CR0 cr0 = 0;
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cr0.pg = 1; // Turn on paging.
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cr0.cd = 0; // Don't disable caching.
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cr0.nw = 0; // This is bit is defined to be ignored.
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cr0.am = 1; // No alignment checking
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cr0.wp = 1; // Supervisor mode can write read only pages
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cr0.ne = 1;
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cr0.et = 1; // This should always be 1
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cr0.ts = 0; // We don't do task switching, so causing fp exceptions
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// would be pointless.
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cr0.em = 0; // Allow x87 instructions to execute natively.
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cr0.mp = 1; // This doesn't really matter, but the manual suggests
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// setting it to one.
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cr0.pe = 1; // We're definitely in protected mode.
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tc->setMiscReg(MISCREG_CR0, cr0);
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CR0 cr2 = 0;
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tc->setMiscReg(MISCREG_CR2, cr2);
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CR3 cr3 = pageTablePhysAddr;
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tc->setMiscReg(MISCREG_CR3, cr3);
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CR4 cr4 = 0;
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//Turn on pae.
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cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
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cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
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cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
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cr4.pce = 0; // Performance-Monitoring Counter Enable
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cr4.pge = 0; // Page-Global Enable
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cr4.mce = 0; // Machine Check Enable
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cr4.pae = 1; // Physical-Address Extension
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cr4.pse = 0; // Page Size Extensions
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cr4.de = 0; // Debugging Extensions
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cr4.tsd = 0; // Time Stamp Disable
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cr4.pvi = 0; // Protected-Mode Virtual Interrupts
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cr4.vme = 0; // Virtual-8086 Mode Extensions
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tc->setMiscReg(MISCREG_CR4, cr4);
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CR4 cr8 = 0;
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tc->setMiscReg(MISCREG_CR8, cr8);
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const Addr PageMapLevel4 = pageTablePhysAddr;
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//Point to the page tables.
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tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
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tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
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tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
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tc->setMiscReg(MISCREG_SEG_BASE(MISCREG_TSG - MISCREG_SEG_SEL_BASE), GDTVirtAddr);
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tc->setMiscReg(MISCREG_SEG_LIMIT(MISCREG_TSG - MISCREG_SEG_SEL_BASE), 0xffff);
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tc->setMiscReg(MISCREG_SEG_BASE(MISCREG_IDTR - MISCREG_SEG_SEL_BASE), IDTVirtAddr);
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tc->setMiscReg(MISCREG_SEG_LIMIT(MISCREG_IDTR - MISCREG_SEG_SEL_BASE), 0xffff);
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/* enabling syscall and sysret */
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MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32);
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tc->setMiscReg(MISCREG_STAR, star);
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MiscReg lstar = (MiscReg) syscallCodeVirtAddr;
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tc->setMiscReg(MISCREG_LSTAR, lstar);
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MiscReg sfmask = (1<<8) | (1<<10); // TF | DF
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tc->setMiscReg(MISCREG_SF_MASK, sfmask);
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}
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SegAttr csAttr = 0;
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csAttr.dpl = 3;
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csAttr.unusable = 0;
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csAttr.defaultSize = 0;
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csAttr.longMode = 1;
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csAttr.avl = 0;
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csAttr.granularity = 1;
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csAttr.present = 1;
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csAttr.type = 10;
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csAttr.writable = 0;
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csAttr.readable = 1;
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csAttr.expandDown = 0;
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csAttr.system = 1;
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/*
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* Setting up the content of the TSS
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* and writting it to physical memory
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*/
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tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
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struct {
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uint32_t reserved0; // +00h
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uint32_t RSP0_low; // +04h
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uint32_t RSP0_high; // +08h
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uint32_t RSP1_low; // +0Ch
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uint32_t RSP1_high; // +10h
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uint32_t RSP2_low; // +14h
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uint32_t RSP2_high; // +18h
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uint32_t reserved1; // +1Ch
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uint32_t reserved2; // +20h
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uint32_t IST1_low; // +24h
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uint32_t IST1_high; // +28h
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uint32_t IST2_low; // +2Ch
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uint32_t IST2_high; // +30h
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uint32_t IST3_low; // +34h
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uint32_t IST3_high; // +38h
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uint32_t IST4_low; // +3Ch
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uint32_t IST4_high; // +40h
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uint32_t IST5_low; // +44h
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uint32_t IST5_high; // +48h
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uint32_t IST6_low; // +4Ch
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uint32_t IST6_high; // +50h
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uint32_t IST7_low; // +54h
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uint32_t IST7_high; // +58h
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uint32_t reserved3; // +5Ch
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uint32_t reserved4; // +60h
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uint16_t reserved5; // +64h
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uint16_t IO_MapBase; // +66h
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} tss;
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Efer efer = 0;
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efer.sce = 1; // Enable system call extensions.
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efer.lme = 1; // Enable long mode.
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efer.lma = 1; // Activate long mode.
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efer.nxe = 1; // Enable nx support.
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efer.svme = 0; // Disable svm support for now. It isn't implemented.
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efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
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tc->setMiscReg(MISCREG_EFER, efer);
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/** setting Interrupt Stack Table */
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uint64_t IST_start = ISTVirtAddr + PageBytes;
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tss.IST1_low = (uint32_t)IST_start;
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tss.IST1_high = (uint32_t)(IST_start >> 32);
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tss.RSP0_low = tss.IST1_low;
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tss.RSP0_high = tss.IST1_high;
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tss.RSP1_low = tss.IST1_low;
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tss.RSP1_high = tss.IST1_high;
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tss.RSP2_low = tss.IST1_low;
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tss.RSP2_high = tss.IST1_high;
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physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss));
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//Set up the registers that describe the operating mode.
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CR0 cr0 = 0;
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cr0.pg = 1; // Turn on paging.
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cr0.cd = 0; // Don't disable caching.
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cr0.nw = 0; // This is bit is defined to be ignored.
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cr0.am = 0; // No alignment checking
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cr0.wp = 0; // Supervisor mode can write read only pages
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cr0.ne = 1;
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cr0.et = 1; // This should always be 1
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cr0.ts = 0; // We don't do task switching, so causing fp exceptions
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// would be pointless.
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cr0.em = 0; // Allow x87 instructions to execute natively.
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cr0.mp = 1; // This doesn't really matter, but the manual suggests
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// setting it to one.
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cr0.pe = 1; // We're definitely in protected mode.
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tc->setMiscReg(MISCREG_CR0, cr0);
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/* Setting IDT gates */
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GateDescriptorLow PFGateLow = 0;
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PFGateLow.offsetHigh = (uint16_t)((uint32_t)PFHandlerVirtAddr >> 16);
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PFGateLow.offsetLow = (uint16_t)PFHandlerVirtAddr;
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PFGateLow.selector = (MiscReg)csLowPL;
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PFGateLow.p = 1;
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PFGateLow.dpl = 0;
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PFGateLow.type = 0xe; // gate interrupt type
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PFGateLow.IST = 0; // setting IST to 0 and using RSP0
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tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
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GateDescriptorHigh PFGateHigh = 0;
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PFGateHigh.offset = (uint32_t)(PFHandlerVirtAddr >> 32);
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struct {
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uint64_t low;
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uint64_t high;
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} PFGate = {PFGateLow, PFGateHigh};
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physProxy.writeBlob(IDTPhysAddr + 0xE0,
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(uint8_t *)(&PFGate), sizeof(PFGate));
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/** System call handler */
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uint8_t syscallBlob[] = {
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0x48,0xa3,0x00,0x60,0x00,
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0x00,0x00,0xc9,0xff,0xff, // mov %rax, (0xffffc90000005600)
|
||||
0x48,0x0f,0x07, // sysret
|
||||
};
|
||||
|
||||
physProxy.writeBlob(syscallCodePhysAddr,
|
||||
syscallBlob, sizeof(syscallBlob));
|
||||
|
||||
/** Page fault handler */
|
||||
uint8_t faultBlob[] = {
|
||||
0x48,0xa3,0x00,0x61,0x00,
|
||||
0x00,0x00,0xc9,0xff,0xff, // mov %rax, (0xffffc90000005700)
|
||||
0x48,0x83,0xc4,0x08, // add $0x8,%rsp # skip error
|
||||
0x48,0xcf, // iretq
|
||||
};
|
||||
|
||||
physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob));
|
||||
|
||||
MultiLevelPageTable<PageTableOps> *pt =
|
||||
dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable);
|
||||
|
||||
/* Syscall handler */
|
||||
pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false);
|
||||
/* GDT */
|
||||
pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false);
|
||||
/* IDT */
|
||||
pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false);
|
||||
/* TSS */
|
||||
pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false);
|
||||
/* IST */
|
||||
pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false);
|
||||
/* PF handler */
|
||||
pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false);
|
||||
/* MMIO region for m5ops */
|
||||
pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false);
|
||||
} else {
|
||||
for (int i = 0; i < contextIds.size(); i++) {
|
||||
ThreadContext * tc = system->getThreadContext(contextIds[i]);
|
||||
|
||||
SegAttr dataAttr = 0;
|
||||
dataAttr.dpl = 3;
|
||||
dataAttr.unusable = 0;
|
||||
dataAttr.defaultSize = 1;
|
||||
dataAttr.longMode = 1;
|
||||
dataAttr.avl = 0;
|
||||
dataAttr.granularity = 1;
|
||||
dataAttr.present = 1;
|
||||
dataAttr.type = 3;
|
||||
dataAttr.writable = 1;
|
||||
dataAttr.readable = 1;
|
||||
dataAttr.expandDown = 0;
|
||||
dataAttr.system = 1;
|
||||
|
||||
//Initialize the segment registers.
|
||||
for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
|
||||
tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
|
||||
tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
|
||||
tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
|
||||
}
|
||||
|
||||
SegAttr csAttr = 0;
|
||||
csAttr.dpl = 3;
|
||||
csAttr.unusable = 0;
|
||||
csAttr.defaultSize = 0;
|
||||
csAttr.longMode = 1;
|
||||
csAttr.avl = 0;
|
||||
csAttr.granularity = 1;
|
||||
csAttr.present = 1;
|
||||
csAttr.type = 10;
|
||||
csAttr.writable = 0;
|
||||
csAttr.readable = 1;
|
||||
csAttr.expandDown = 0;
|
||||
csAttr.system = 1;
|
||||
|
||||
tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
|
||||
|
||||
Efer efer = 0;
|
||||
efer.sce = 1; // Enable system call extensions.
|
||||
efer.lme = 1; // Enable long mode.
|
||||
efer.lma = 1; // Activate long mode.
|
||||
efer.nxe = 1; // Enable nx support.
|
||||
efer.svme = 0; // Disable svm support for now. It isn't implemented.
|
||||
efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
|
||||
tc->setMiscReg(MISCREG_EFER, efer);
|
||||
|
||||
//Set up the registers that describe the operating mode.
|
||||
CR0 cr0 = 0;
|
||||
cr0.pg = 1; // Turn on paging.
|
||||
cr0.cd = 0; // Don't disable caching.
|
||||
cr0.nw = 0; // This is bit is defined to be ignored.
|
||||
cr0.am = 0; // No alignment checking
|
||||
cr0.wp = 0; // Supervisor mode can write read only pages
|
||||
cr0.ne = 1;
|
||||
cr0.et = 1; // This should always be 1
|
||||
cr0.ts = 0; // We don't do task switching, so causing fp exceptions
|
||||
// would be pointless.
|
||||
cr0.em = 0; // Allow x87 instructions to execute natively.
|
||||
cr0.mp = 1; // This doesn't really matter, but the manual suggests
|
||||
// setting it to one.
|
||||
cr0.pe = 1; // We're definitely in protected mode.
|
||||
tc->setMiscReg(MISCREG_CR0, cr0);
|
||||
|
||||
tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -573,10 +921,13 @@ X86LiveProcess::argsInit(int pageSize,
|
|||
|
||||
stack_min = stack_base - space_needed;
|
||||
stack_min = roundDown(stack_min, align);
|
||||
stack_size = stack_base - stack_min;
|
||||
stack_size = roundUp(stack_base - stack_min, pageSize);
|
||||
|
||||
// map memory
|
||||
allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize));
|
||||
Addr stack_end = roundDown(stack_base - stack_size, pageSize);
|
||||
|
||||
DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
|
||||
allocateMem(stack_end, stack_size);
|
||||
|
||||
// map out initial stack contents
|
||||
IntType sentry_base = stack_base - sentry_size;
|
||||
|
|
|
|||
|
|
@ -613,6 +613,9 @@ namespace X86ISA
|
|||
EndBitUnion(CR3)
|
||||
|
||||
BitUnion64(CR4)
|
||||
Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
|
||||
Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
|
||||
// WRGSBASE instructions
|
||||
Bitfield<10> osxmmexcpt; // Operating System Unmasked
|
||||
// Exception Support
|
||||
Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
|
||||
|
|
@ -885,6 +888,44 @@ namespace X86ISA
|
|||
EndSubBitUnion(type)
|
||||
EndBitUnion(SegDescriptor)
|
||||
|
||||
/**
|
||||
* TSS Descriptor (long mode - 128 bits)
|
||||
* the lower 64 bits
|
||||
*/
|
||||
BitUnion64(TSSlow)
|
||||
Bitfield<63, 56> baseHigh;
|
||||
Bitfield<39, 16> baseLow;
|
||||
Bitfield<55> g; // Granularity
|
||||
Bitfield<52> avl; // Available To Software
|
||||
Bitfield<51, 48> limitHigh;
|
||||
Bitfield<15, 0> limitLow;
|
||||
Bitfield<47> p; // Present
|
||||
Bitfield<46, 45> dpl; // Descriptor Privilege-Level
|
||||
SubBitUnion(type, 43, 40)
|
||||
// Specifies whether this descriptor is for code or data.
|
||||
Bitfield<43> codeOrData;
|
||||
|
||||
// These bit fields are for code segments
|
||||
Bitfield<42> c; // Conforming
|
||||
Bitfield<41> r; // Readable
|
||||
|
||||
// These bit fields are for data segments
|
||||
Bitfield<42> e; // Expand-Down
|
||||
Bitfield<41> w; // Writable
|
||||
|
||||
// This is used for both code and data segments.
|
||||
Bitfield<40> a; // Accessed
|
||||
EndSubBitUnion(type)
|
||||
EndBitUnion(TSSlow)
|
||||
|
||||
/**
|
||||
* TSS Descriptor (long mode - 128 bits)
|
||||
* the upper 64 bits
|
||||
*/
|
||||
BitUnion64(TSShigh)
|
||||
Bitfield<31, 0> base;
|
||||
EndBitUnion(TSShigh)
|
||||
|
||||
BitUnion64(SegAttr)
|
||||
Bitfield<1, 0> dpl;
|
||||
Bitfield<2> unusable;
|
||||
|
|
@ -910,6 +951,23 @@ namespace X86ISA
|
|||
Bitfield<36, 32> count; // Parameter Count
|
||||
EndBitUnion(GateDescriptor)
|
||||
|
||||
/**
|
||||
* Long Mode Gate Descriptor
|
||||
*/
|
||||
BitUnion64(GateDescriptorLow)
|
||||
Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
|
||||
Bitfield<47> p; // Present
|
||||
Bitfield<46, 45> dpl; // Descriptor Privilege-Level
|
||||
Bitfield<43, 40> type;
|
||||
Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling
|
||||
Bitfield<31, 16> selector; // Target Code-Segment Selector
|
||||
Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
|
||||
EndBitUnion(GateDescriptorLow)
|
||||
|
||||
BitUnion64(GateDescriptorHigh)
|
||||
Bitfield<31, 0> offset; // Target Code-Segment Offset
|
||||
EndBitUnion(GateDescriptorHigh)
|
||||
|
||||
/**
|
||||
* Descriptor-Table Registers
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -63,8 +63,8 @@ X86System::X86System(Params *p) :
|
|||
{
|
||||
}
|
||||
|
||||
static void
|
||||
installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
|
||||
void
|
||||
X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
|
||||
SegDescriptor desc, bool longmode)
|
||||
{
|
||||
uint64_t base = desc.baseLow + (desc.baseHigh << 24);
|
||||
|
|
@ -151,19 +151,25 @@ X86System::initState()
|
|||
(uint8_t *)(&nullDescriptor), 8);
|
||||
numGDTEntries++;
|
||||
|
||||
SegDescriptor initDesc = 0;
|
||||
initDesc.type.codeOrData = 0; // code or data type
|
||||
initDesc.type.c = 0; // conforming
|
||||
initDesc.type.r = 1; // readable
|
||||
initDesc.dpl = 0; // privilege
|
||||
initDesc.p = 1; // present
|
||||
initDesc.l = 1; // longmode - 64 bit
|
||||
initDesc.d = 0; // operand size
|
||||
initDesc.g = 1; // granularity
|
||||
initDesc.s = 1; // system segment
|
||||
initDesc.limitHigh = 0xFFFF;
|
||||
initDesc.limitLow = 0xF;
|
||||
initDesc.baseHigh = 0x0;
|
||||
initDesc.baseLow = 0x0;
|
||||
|
||||
//64 bit code segment
|
||||
SegDescriptor csDesc = 0;
|
||||
SegDescriptor csDesc = initDesc;
|
||||
csDesc.type.codeOrData = 1;
|
||||
csDesc.type.c = 0; // Not conforming
|
||||
csDesc.type.r = 1; // Readable
|
||||
csDesc.dpl = 0; // Privelege level 0
|
||||
csDesc.p = 1; // Present
|
||||
csDesc.l = 1; // 64 bit
|
||||
csDesc.d = 0; // default operand size
|
||||
csDesc.g = 1; // Page granularity
|
||||
csDesc.s = 1; // Not a system segment
|
||||
csDesc.limitHigh = 0xF;
|
||||
csDesc.limitLow = 0xFFFF;
|
||||
csDesc.dpl = 0;
|
||||
//Because we're dealing with a pointer and I don't think it's
|
||||
//guaranteed that there isn't anything in a nonvirtual class between
|
||||
//it's beginning in memory and it's actual data, we'll use an
|
||||
|
|
@ -180,17 +186,7 @@ X86System::initState()
|
|||
tc->setMiscReg(MISCREG_CS, (MiscReg)cs);
|
||||
|
||||
//32 bit data segment
|
||||
SegDescriptor dsDesc = 0;
|
||||
dsDesc.type.codeOrData = 0;
|
||||
dsDesc.type.e = 0; // Not expand down
|
||||
dsDesc.type.w = 1; // Writable
|
||||
dsDesc.dpl = 0; // Privelege level 0
|
||||
dsDesc.p = 1; // Present
|
||||
dsDesc.d = 1; // default operand size
|
||||
dsDesc.g = 1; // Page granularity
|
||||
dsDesc.s = 1; // Not a system segment
|
||||
dsDesc.limitHigh = 0xF;
|
||||
dsDesc.limitLow = 0xFFFF;
|
||||
SegDescriptor dsDesc = initDesc;
|
||||
uint64_t dsDescVal = dsDesc;
|
||||
physProxy.writeBlob(GDTBase + numGDTEntries * 8,
|
||||
(uint8_t *)(&dsDescVal), 8);
|
||||
|
|
@ -210,15 +206,7 @@ X86System::initState()
|
|||
tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
|
||||
tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
|
||||
|
||||
SegDescriptor tssDesc = 0;
|
||||
tssDesc.type = 0xB;
|
||||
tssDesc.dpl = 0; // Privelege level 0
|
||||
tssDesc.p = 1; // Present
|
||||
tssDesc.d = 1; // default operand size
|
||||
tssDesc.g = 1; // Page granularity
|
||||
tssDesc.s = 0;
|
||||
tssDesc.limitHigh = 0xF;
|
||||
tssDesc.limitLow = 0xFFFF;
|
||||
SegDescriptor tssDesc = initDesc;
|
||||
uint64_t tssDescVal = tssDesc;
|
||||
physProxy.writeBlob(GDTBase + numGDTEntries * 8,
|
||||
(uint8_t *)(&tssDescVal), 8);
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "arch/x86/regs/misc.hh"
|
||||
#include "base/loader/symtab.hh"
|
||||
#include "cpu/pc_event.hh"
|
||||
#include "kern/system_events.hh"
|
||||
|
|
@ -62,6 +63,9 @@ namespace X86ISA
|
|||
class ConfigTable;
|
||||
}
|
||||
|
||||
void installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
|
||||
SegDescriptor desc, bool longmode);
|
||||
|
||||
/* memory mappings for KVMCpu in SE mode */
|
||||
const uint64_t syscallCodeVirtAddr = 0xffff800000000000;
|
||||
const uint64_t syscallCodePhysAddr = 0x60000;
|
||||
|
|
@ -73,6 +77,10 @@ namespace X86ISA
|
|||
const uint64_t TSSPhysAddr = 0x63000;
|
||||
const uint64_t ISTVirtAddr = 0xffff800000004000;
|
||||
const uint64_t ISTPhysAddr = 0x64000;
|
||||
const uint64_t PFHandlerVirtAddr = 0xffff800000005000;
|
||||
const uint64_t PFHandlerPhysAddr = 0x65000;
|
||||
const uint64_t MMIORegionVirtAddr = 0xffffc90000000000;
|
||||
const uint64_t MMIORegionPhysAddr = 0xffff0000;
|
||||
|
||||
const uint64_t pageTablePhysAddr = 0x70000;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ class Process(SimObject):
|
|||
system = Param.System(Parent.any, "system process will run on")
|
||||
useArchPT = Param.Bool('false', 'maintain an in-memory version of the page\
|
||||
table in an architecture-specific format')
|
||||
kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in SE')
|
||||
max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack')
|
||||
|
||||
@classmethod
|
||||
|
|
|
|||
|
|
@ -107,6 +107,7 @@ Process::Process(ProcessParams * params)
|
|||
max_stack_size(params->max_stack_size),
|
||||
M5_pid(system->allocatePID()),
|
||||
useArchPT(params->useArchPT),
|
||||
kvmInSE(params->kvmInSE),
|
||||
pTable(useArchPT ?
|
||||
static_cast<PageTableBase *>(new ArchPageTable(name(), M5_pid, system)) :
|
||||
static_cast<PageTableBase *>(new FuncPageTable(name(), M5_pid)) ),
|
||||
|
|
|
|||
|
|
@ -128,6 +128,9 @@ class Process : public SimObject
|
|||
|
||||
// flag for using architecture specific page table
|
||||
bool useArchPT;
|
||||
// running KvmCPU in SE mode requires special initialization
|
||||
bool kvmInSE;
|
||||
|
||||
PageTableBase* pTable;
|
||||
|
||||
class FdMap
|
||||
|
|
|
|||
Loading…
Reference in a new issue