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gem5/src/arch/x86
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Steve Reinhardt 6677b9122a mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW 
Makes x86-style locked operations even more distinct from
LLSC operations.  Using "locked" by itself should be
obviously ambiguous now.
2015-03-23 16:14:20 -07:00
..
bios base: Replace the internal varargs stuff with C++11 constructs 2014-08-26 10:13:45 -04:00
insts arch,x86,mem: Dynamically determine the ISA for Ruby store check 2014-10-16 05:49:44 -04:00
isa mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW 2015-03-23 16:14:20 -07:00
linux sim: revert 6709bbcf564d 2014-10-22 15:59:57 -05:00
regs x86: Segment initialization to support KvmCPU in SE 2014-11-23 18:01:08 -08:00
cpuid.cc x86: Enable three bits in the FamilyModelStepping ECX CPUID bitfield. 2015-01-06 22:15:00 -08:00
cpuid.hh scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
decoder.cc x86: Rework opcode parsing to support 3 byte opcodes properly. 2014-12-04 15:53:54 -08:00
decoder.hh x86: Rework opcode parsing to support 3 byte opcodes properly. 2014-12-04 15:53:54 -08:00
decoder_tables.cc x86: Rework opcode parsing to support 3 byte opcodes properly. 2014-12-04 15:53:54 -08:00
emulenv.cc CPU: Merge the predecoder and decoder. 2012-05-26 13:44:46 -07:00
emulenv.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
faults.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
faults.hh sim: Move the BaseTLB to src/arch/generic/ 2015-02-11 10:23:27 -05:00
interrupts.cc x86: APIC: Only set deliveryStatus if our IPI is going somewhere. 2014-11-17 00:19:07 -08:00
interrupts.hh x86: APIC: Fix the getRegArrayBit function. 2014-11-17 00:17:06 -08:00
intmessage.hh MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
isa.cc arch: Make readMiscRegNoEffect const throughout 2015-02-16 03:33:28 -05:00
isa.hh arch: Make readMiscRegNoEffect const throughout 2015-02-16 03:33:28 -05:00
isa_traits.hh x86: Rework opcode parsing to support 3 byte opcodes properly. 2014-12-04 15:53:54 -08:00
kernel_stats.hh copyright: Change HP copyright on x86 code to be more friendly 2010-05-23 22:44:15 -07:00
ldstflags.hh arch,x86,mem: Dynamically determine the ISA for Ruby store check 2014-10-16 05:49:44 -04:00
locked_mem.hh cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped. 2014-01-24 15:29:30 -06:00
memhelpers.hh arch: Use shared_ptr for all Faults 2014-10-16 05:49:51 -04:00
microcode_rom.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
mmapped_ipr.hh arch: Add support for m5ops using mmapped IPRs 2013-09-30 12:20:43 +02:00
nativetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
nativetrace.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
pagetable.cc mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
pagetable.hh mem: Page Table map api modification 2014-11-23 18:01:09 -08:00
pagetable_walker.cc mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
pagetable_walker.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
process.cc x86: Clean up style in process.cc. 2014-12-02 22:01:51 -08:00
process.hh mem: adding architectural page table support for SE mode 2014-08-28 10:11:44 -05:00
pseudo_inst.cc kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
pseudo_inst.hh kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
registers.hh arch/x86: add support for explicit CC register file 2013-10-15 14:22:44 -04:00
remote_gdb.cc misc: Generalize GDB single stepping. 2014-12-05 22:37:03 -08:00
remote_gdb.hh misc: Generalize GDB single stepping. 2014-12-05 22:37:03 -08:00
SConscript kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
SConsopts copyright: This file need not have had the more restrictive copyright. 2009-02-09 20:10:15 -08:00
stacktrace.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
stacktrace.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
system.cc x86: Segment initialization to support KvmCPU in SE 2014-11-23 18:01:08 -08:00
system.hh x86: Segment initialization to support KvmCPU in SE 2014-11-23 18:01:08 -08:00
tlb.cc kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
tlb.hh sim: Move the BaseTLB to src/arch/generic/ 2015-02-11 10:23:27 -05:00
types.cc x86: Rework opcode parsing to support 3 byte opcodes properly. 2014-12-04 15:53:54 -08:00
types.hh x86: Rework opcode parsing to support 3 byte opcodes properly. 2014-12-04 15:53:54 -08:00
utility.cc kvm, x86: Adding support for SE mode execution 2014-11-23 18:01:08 -08:00
utility.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
vtophys.cc arch: Use shared_ptr for all Faults 2014-10-16 05:49:51 -04:00
vtophys.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
x86_traits.hh arch/x86: add support for explicit CC register file 2013-10-15 14:22:44 -04:00
X86ISA.py arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
X86LocalApic.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
X86NativeTrace.py cpu: Put all CPU instruction tracers in a single file 2015-01-25 07:22:17 -05:00
X86System.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
X86TLB.py x86: add tlb checkpointing 2013-08-07 14:51:17 -05:00