sim: Move the BaseTLB to src/arch/generic/

The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.

--HG--
rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py
rename : src/sim/tlb.cc => src/arch/generic/tlb.cc
rename : src/sim/tlb.hh => src/arch/generic/tlb.hh

src/arch/alpha/tlb.hh

@@ -39,10 +39,10 @@
 #include "arch/alpha/pagetable.hh"
 #include "arch/alpha/utility.hh"
 #include "arch/alpha/vtophys.hh"
+#include "arch/generic/tlb.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/AlphaTLB.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 

src/arch/arm/stage2_lookup.hh

@@ -47,7 +47,6 @@
 #include "arch/arm/table_walker.hh"
 #include "arch/arm/tlb.hh"
 #include "mem/request.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 

src/arch/arm/tlb.hh

@@ -48,12 +48,12 @@
 #include "arch/arm/pagetable.hh"
 #include "arch/arm/utility.hh"
 #include "arch/arm/vtophys.hh"
+#include "arch/generic/tlb.hh"
 #include "base/statistics.hh"
 #include "dev/dma_device.hh"
 #include "mem/request.hh"
 #include "params/ArmTLB.hh"
 #include "sim/probe/pmu.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 

src/arch/generic/BaseTLB.py

@@ -31,4 +31,4 @@ from m5.SimObject import SimObject
 class BaseTLB(SimObject):
     type = 'BaseTLB'
     abstract = True
-    cxx_header = "sim/tlb.hh"
+    cxx_header = "arch/generic/tlb.hh"

src/arch/generic/SConscript

@@ -33,4 +33,9 @@ if env['TARGET_ISA'] == 'null':
 
 Source('decode_cache.cc')
 Source('mmapped_ipr.cc')
+Source('tlb.cc')
+
+SimObject('BaseTLB.py')
+
+DebugFlag('TLB')
 Source('pseudo_inst.cc')

src/arch/generic/tlb.cc

@@ -28,12 +28,13 @@
  * Authors: Gabe Black
  */
 
+#include "arch/generic/tlb.hh"
+
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "sim/faults.hh"
 #include "sim/full_system.hh"
 #include "sim/process.hh"
-#include "sim/tlb.hh"
 
 Fault
 GenericTLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode)

src/arch/generic/tlb.hh

@@ -40,8 +40,8 @@
  * Authors: Gabe Black
  */
 
-#ifndef __SIM_TLB_HH__
-#define __SIM_TLB_HH__
+#ifndef __ARCH_GENERIC_TLB_HH__
+#define __ARCH_GENERIC_TLB_HH__
 
 #include "base/misc.hh"
 #include "mem/request.hh"
@@ -147,4 +147,4 @@ class GenericTLB : public BaseTLB
     Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
 };
 
-#endif // __ARCH_SPARC_TLB_HH__
+#endif // __ARCH_GENERIC_TLB_HH__

src/arch/mips/tlb.hh

@@ -37,6 +37,7 @@
 
 #include <map>
 
+#include "arch/generic/tlb.hh"
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/pagetable.hh"
 #include "arch/mips/utility.hh"
@@ -45,7 +46,6 @@
 #include "mem/request.hh"
 #include "params/MipsTLB.hh"
 #include "sim/sim_object.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 

src/arch/power/tlb.hh

@@ -39,6 +39,7 @@
 
 #include <map>
 
+#include "arch/generic/tlb.hh"
 #include "arch/power/isa_traits.hh"
 #include "arch/power/pagetable.hh"
 #include "arch/power/utility.hh"
@@ -46,7 +47,6 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/PowerTLB.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 

src/arch/sparc/tlb.hh

@@ -31,12 +31,12 @@
 #ifndef __ARCH_SPARC_TLB_HH__
 #define __ARCH_SPARC_TLB_HH__
 
+#include "arch/generic/tlb.hh"
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
 #include "base/misc.hh"
 #include "mem/request.hh"
 #include "params/SparcTLB.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 class Packet;

src/arch/x86/faults.hh

@@ -42,10 +42,10 @@
 
 #include <string>
 
+#include "arch/generic/tlb.hh"
 #include "base/bitunion.hh"
 #include "base/misc.hh"
 #include "sim/faults.hh"
-#include "sim/tlb.hh"
 
 namespace X86ISA
 {

src/arch/x86/tlb.hh

@@ -44,6 +44,7 @@
 #include <string>
 #include <vector>
 
+#include "arch/generic/tlb.hh"
 #include "arch/x86/regs/segment.hh"
 #include "arch/x86/pagetable.hh"
 #include "base/trie.hh"
@@ -51,7 +52,6 @@
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
 #include "sim/sim_object.hh"
-#include "sim/tlb.hh"
 
 class ThreadContext;
 class Packet;

src/cpu/base_dyn_inst.hh

@@ -51,6 +51,7 @@
 #include <string>
 #include <queue>
 
+#include "arch/generic/tlb.hh"
 #include "arch/utility.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
@@ -65,7 +66,6 @@
 #include "mem/packet.hh"
 #include "sim/byteswap.hh"
 #include "sim/system.hh"
-#include "sim/tlb.hh"
 
 /**
  * @file

src/cpu/checker/cpu.cc

@@ -44,6 +44,7 @@
 #include <list>
 #include <string>
 
+#include "arch/generic/tlb.hh"
 #include "arch/kernel_stats.hh"
 #include "arch/vtophys.hh"
 #include "cpu/checker/cpu.hh"
@@ -53,7 +54,6 @@
 #include "cpu/thread_context.hh"
 #include "params/CheckerCPU.hh"
 #include "sim/full_system.hh"
-#include "sim/tlb.hh"
 
 using namespace std;
 using namespace TheISA;

src/cpu/translation.hh

@@ -45,8 +45,8 @@
 #ifndef __CPU_TRANSLATION_HH__
 #define __CPU_TRANSLATION_HH__
 
+#include "arch/generic/tlb.hh"
 #include "sim/faults.hh"
-#include "sim/tlb.hh"
 
 /**
  * This class captures the state of an address translation.  A translation

src/sim/SConscript

@@ -30,7 +30,6 @@
 
 Import('*')
 
-SimObject('BaseTLB.py')
 SimObject('ClockedObject.py')
 SimObject('TickedObject.py')
 SimObject('Root.py')
@@ -75,7 +74,6 @@ if env['TARGET_ISA'] != 'null':
     Source('process.cc')
     Source('pseudo_inst.cc')
     Source('syscall_emul.cc')
-    Source('tlb.cc')
 
 DebugFlag('Checkpoint')
 DebugFlag('Config')
@@ -92,7 +90,6 @@ DebugFlag('PseudoInst')
 DebugFlag('Stack')
 DebugFlag('SyscallVerbose')
 DebugFlag('TimeSync')
-DebugFlag('TLB')
 DebugFlag('Thread')
 DebugFlag('Timer')
 DebugFlag('VtoPhys')