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arch: Make readMiscRegNoEffect const throughout

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Finally took the plunge and made this apply to all ISAs, not just ARM.
This commit is contained in:
Andreas Hansson 2015-02-16 03:33:28 -05:00
parent 07ce60bdfa
commit d0e1b8a19c
18 changed files with 21 additions and 21 deletions
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2
src/arch/alpha/isa.cc
View file

@ -74,7 +74,7 @@ ISA::unserialize(Checkpoint *cp, const std::string &section)
MiscReg
ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
switch (misc_reg) {
case MISCREG_FPCR:

2
src/arch/alpha/isa.hh
View file

@ -73,7 +73,7 @@ namespace AlphaISA
public:
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val,

4
src/arch/mips/isa.cc
View file

@ -410,14 +410,14 @@ ISA::configCP()
}
inline unsigned
ISA::getVPENum(ThreadID tid)
ISA::getVPENum(ThreadID tid) const
{
TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
return tcBind.curVPE;
}
MiscReg
ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);

4
src/arch/mips/isa.hh
View file

@ -76,7 +76,7 @@ namespace MipsISA
void configCP();
unsigned getVPENum(ThreadID tid);
unsigned getVPENum(ThreadID tid) const;
//////////////////////////////////////////////////////////
//
@ -87,7 +87,7 @@ namespace MipsISA
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
void updateCP0ReadView(int misc_reg, ThreadID tid) { }
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
//template <class TC>
MiscReg readMiscReg(int misc_reg,

2
src/arch/power/isa.hh
View file

@ -61,7 +61,7 @@ class ISA : public SimObject
}
MiscReg
readMiscRegNoEffect(int misc_reg)
readMiscRegNoEffect(int misc_reg) const
{
fatal("Power does not currently have any misc regs defined\n");
return dummy;

2
src/arch/sparc/isa.cc
View file

@ -173,7 +173,7 @@ ISA::clear()
}
MiscReg
ISA::readMiscRegNoEffect(int miscReg)
ISA::readMiscRegNoEffect(int miscReg) const
{
// The three miscRegs are moved up from the switch statement

2
src/arch/sparc/isa.hh
View file

@ -183,7 +183,7 @@ class ISA : public SimObject
public:
MiscReg readMiscRegNoEffect(int miscReg);
MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, const MiscReg val);

2
src/arch/x86/isa.cc
View file

@ -124,7 +124,7 @@ ISA::params() const
}
MiscReg
ISA::readMiscRegNoEffect(int miscReg)
ISA::readMiscRegNoEffect(int miscReg) const
{
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should

2
src/arch/x86/isa.hh
View file

@ -63,7 +63,7 @@ namespace X86ISA
ISA(Params *p);
const Params *params() const;
MiscReg readMiscRegNoEffect(int miscReg);
MiscReg readMiscRegNoEffect(int miscReg) const;
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
void setMiscRegNoEffect(int miscReg, MiscReg val);

2
src/cpu/checker/cpu.hh
View file

@ -285,7 +285,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
MicroPC microPC() { return thread->microPC(); }
//////////////////////////////////////////
MiscReg readMiscRegNoEffect(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg) const
{
return thread->readMiscRegNoEffect(misc_reg);
}

2
src/cpu/checker/thread_context.hh
View file

@ -275,7 +275,7 @@ class CheckerThreadContext : public ThreadContext
MicroPC microPC()
{ return actualTC->microPC(); }
MiscReg readMiscRegNoEffect(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }
MiscReg readMiscReg(int misc_reg)

2
src/cpu/minor/exec_context.hh
View file

@ -187,7 +187,7 @@ class ExecContext : public ::ExecContext
}
TheISA::MiscReg
readMiscRegNoEffect(int misc_reg)
readMiscRegNoEffect(int misc_reg) const
{
return thread.readMiscRegNoEffect(misc_reg);
}

2
src/cpu/o3/cpu.cc
View file

@ -1205,7 +1205,7 @@ FullO3CPU<Impl>::verifyMemoryMode() const
template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
return this->isa[tid]->readMiscRegNoEffect(misc_reg);
}

2
src/cpu/o3/cpu.hh
View file

@ -403,7 +403,7 @@ class FullO3CPU : public BaseO3CPU
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.

2
src/cpu/o3/thread_context.hh
View file

@ -228,7 +228,7 @@ class O3ThreadContext : public ThreadContext
{ return cpu->microPC(thread->threadId()); }
/** Reads a miscellaneous register. */
virtual MiscReg readMiscRegNoEffect(int misc_reg)
virtual MiscReg readMiscRegNoEffect(int misc_reg) const
{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
/** Reads a misc. register, including any side-effects the

2
src/cpu/simple/base.hh
View file

@ -367,7 +367,7 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
Addr nextInstAddr() { return thread->nextInstAddr(); }
MicroPC microPC() { return thread->microPC(); }
MiscReg readMiscRegNoEffect(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg) const
{
return thread->readMiscRegNoEffect(misc_reg);
}

2
src/cpu/simple_thread.hh
View file

@ -372,7 +372,7 @@ class SimpleThread : public ThreadState
}
MiscReg
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
{
return isa->readMiscRegNoEffect(misc_reg);
}

4
src/cpu/thread_context.hh
View file

@ -225,7 +225,7 @@ class ThreadContext
virtual MicroPC microPC() = 0;
virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
virtual MiscReg readMiscReg(int misc_reg) = 0;
@ -429,7 +429,7 @@ class ProxyThreadContext : public ThreadContext
void setPredicate(bool val)
{ actualTC->setPredicate(val); }
MiscReg readMiscRegNoEffect(int misc_reg)
MiscReg readMiscRegNoEffect(int misc_reg) const
{ return actualTC->readMiscRegNoEffect(misc_reg); }
MiscReg readMiscReg(int misc_reg)