22aaa5867f
Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. --HG-- rename : src/arch/x86/isa/decoder/three_byte_opcodes.isa => src/arch/x86/isa/decoder/three_byte_0f38_opcodes.isa rename : src/arch/x86/isa/decoder/three_byte_opcodes.isa => src/arch/x86/isa/decoder/three_byte_0f3a_opcodes.isa
105 lines
3.8 KiB
C++
105 lines
3.8 KiB
C++
/*
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* Copyright (c) 2010 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/x86/types.hh"
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#include "sim/serialize.hh"
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using namespace X86ISA;
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using namespace std;
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template <>
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void
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paramOut(ostream &os, const string &name, ExtMachInst const &machInst)
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{
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// Prefixes
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paramOut(os, name + ".legacy", (uint8_t)machInst.legacy);
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paramOut(os, name + ".rex", (uint8_t)machInst.rex);
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// Opcode
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paramOut(os, name + ".opcode.type", (uint8_t)machInst.opcode.type);
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paramOut(os, name + ".opcode.op", (uint8_t)machInst.opcode.op);
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// Modifier bytes
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paramOut(os, name + ".modRM", (uint8_t)machInst.modRM);
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paramOut(os, name + ".sib", (uint8_t)machInst.sib);
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// Immediate fields
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paramOut(os, name + ".immediate", machInst.immediate);
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paramOut(os, name + ".displacement", machInst.displacement);
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// Sizes
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paramOut(os, name + ".opSize", machInst.opSize);
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paramOut(os, name + ".addrSize", machInst.addrSize);
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paramOut(os, name + ".stackSize", machInst.stackSize);
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paramOut(os, name + ".dispSize", machInst.dispSize);
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// Mode
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paramOut(os, name + ".mode", (uint8_t)machInst.mode);
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}
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template <>
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void
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paramIn(Checkpoint *cp, const string §ion,
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const string &name, ExtMachInst &machInst)
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{
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uint8_t temp8;
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// Prefixes
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paramIn(cp, section, name + ".legacy", temp8);
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machInst.legacy = temp8;
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paramIn(cp, section, name + ".rex", temp8);
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machInst.rex = temp8;
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// Opcode
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paramIn(cp, section, name + ".opcode.type", temp8);
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machInst.opcode.type = (OpcodeType)temp8;
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paramIn(cp, section, name + ".opcode.op", temp8);
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machInst.opcode.op = temp8;
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// Modifier bytes
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paramIn(cp, section, name + ".modRM", temp8);
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machInst.modRM = temp8;
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paramIn(cp, section, name + ".sib", temp8);
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machInst.sib = temp8;;
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// Immediate fields
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paramIn(cp, section, name + ".immediate", machInst.immediate);
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paramIn(cp, section, name + ".displacement", machInst.displacement);
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// Sizes
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paramIn(cp, section, name + ".opSize", machInst.opSize);
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paramIn(cp, section, name + ".addrSize", machInst.addrSize);
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paramIn(cp, section, name + ".stackSize", machInst.stackSize);
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paramIn(cp, section, name + ".dispSize", machInst.dispSize);
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// Mode
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paramIn(cp, section, name + ".mode", temp8);
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machInst.mode = temp8;
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}
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