Korey Sewell f51656498e Merge zizzer:/bk/newmem ... into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips arch/mips/isa/formats/mem.isa: Filled in Split-Memory Access Code arch/mips/isa_traits.hh: Leave IntRegFile as an array instead of class with member functions mem/page_table.cc: take out NO ALIGN FAULT page table access code for now... No need to messs up what works --HG-- extra : convert_revision : cbf1cce9145daf9ee9ceabc9080271ddb0561489		2006-04-10 12:37:15 -04:00
..
memtest	Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.	2006-03-04 15:18:40 -05:00
o3	Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.	2006-03-14 15:55:00 -05:00
ozone	Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.	2006-03-14 15:55:00 -05:00
simple	Move to a model with a unified request object.	2006-04-07 15:54:48 -04:00
trace	Made Addr a global type	2006-02-21 03:38:21 -05:00
base.cc	Hand merge. Stuff probably doesn't compile.	2006-03-09 18:35:28 -05:00
base.hh	Replace Memory with MemObject; no need for two different levels of hierarchy there.	2006-03-12 17:21:59 -05:00
base_dyn_inst.cc	Merge ktlim@zizzer:/bk/m5	2006-03-05 00:34:54 -05:00
base_dyn_inst.hh	Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.	2006-03-04 15:18:40 -05:00
cpu_exec_context.cc	Merge m5.eecs.umich.edu:/bk/newmem	2006-04-06 15:00:11 -04:00
cpu_exec_context.hh	Move to a model with a unified request object.	2006-04-07 15:54:48 -04:00
cpu_models.py	Enable building only selected CPU models via new scons	2006-02-23 17:00:29 -05:00
exec_context.hh	Move to a model with a unified request object.	2006-04-07 15:54:48 -04:00
exetrace.cc	Enable register windows.	2006-04-06 14:47:03 -04:00
exetrace.hh	Enable register windows.	2006-04-06 14:47:03 -04:00
inst_seq.hh	fix problems on darwin/*BSD for syscall emulation mode	2006-02-10 14:21:32 -05:00
intr_control.cc	Updates for the quiesceEvent that was added to the XC.	2006-03-07 19:59:12 -05:00
intr_control.hh	Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.	2006-03-04 15:18:40 -05:00
op_class.cc	Move op_class.hh out of encumbered/cpu/full and into cpu.	2006-02-21 22:12:27 -05:00
op_class.hh	Move op_class.hh out of encumbered/cpu/full and into cpu.	2006-02-21 22:12:27 -05:00
pc_event.cc	Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.	2006-03-04 15:18:40 -05:00
pc_event.hh	Work towards factoring isa_traits.hh into smaller, more specialized files.	2006-03-10 19:11:27 -05:00
profile.cc	Updates for the quiesceEvent that was added to the XC.	2006-03-07 19:59:12 -05:00
profile.hh	Updates for the quiesceEvent that was added to the XC.	2006-03-07 19:59:12 -05:00
SConscript	Make sure cpu/static_inst_exec_sigs.hh get rebuilt when	2006-02-25 22:57:46 -05:00
smt.hh	Many files:	2005-06-05 05:16:00 -04:00
static_inst.cc	Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.	2006-02-19 02:34:37 -05:00
static_inst.hh	Finally MIPS does hello world!	2006-04-10 12:23:17 -04:00