Finally MIPS does hello world!
arch/mips/isa/bitfields.isa:
add RS_SRL bitfield ...these must be set to 0 for a SRL instruction
arch/mips/isa/decoder.isa:
Make unimplemented instructions Fail instead of just Warn
Edits to SRA & SRAV instructions
Implement CFC1 instructions
Unaligned Memory Access Support (Maybe Not fully functional yet)
Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions)
arch/mips/isa/formats/branch.isa:
Fix disassembly
arch/mips/isa/formats/int.isa:
Add sign extend Immediate and zero extend Immediate to Int class.
Probably a bit unnecessary in the long run since these manipulations could
be done in the actually instruction instead of keep a int value
arch/mips/isa/formats/mem.isa:
Comment/Remove out split-memory access code... revisit this after SimpleCPU works
arch/mips/isa/formats/unimp.isa:
Add inst2string function to Unimplemented panic. PRints out the instruction
binary to help in debuggin
arch/mips/isa/formats/unknown.isa:
define inst2string function , use in unknown disassembly and panic function
arch/mips/isa/operands.isa:
Make "Mem" default to a unsigned word since this is MIPS32
arch/mips/isa_traits.hh:
change return values to 32 instead of 64
arch/mips/linux_process.cc:
assign some syscalls to the right functions
cpu/static_inst.hh:
more debug functions for MIPS (these will be move to the mips directory soon)
mem/page_table.cc:
mem/page_table.hh:
toward a better implementation for unaligned memory access
mem/request.hh:
NO ALIGN FAULT flag added to support unaligned memory access
sim/syscall_emul.cc:
additional SyscallVerbose comments
--HG--
extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c
This commit is contained in:
Korey Sewell
parent
b855ea6968
commit
4f430e9ab5
15 changed files with 425 additions and 204 deletions
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@ -26,6 +26,7 @@ def bitfield RS <25:21>;
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def bitfield RS_MSB <25:25>;
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def bitfield RS_HI <25:24>;
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def bitfield RS_LO <23:21>;
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def bitfield RS_SRL <25:22>;
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def bitfield RD <15:11>;
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@ -43,14 +43,30 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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0x2: decode SRL {
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0: srl({{ Rd = Rt.uw >> SA; }});
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0x2: decode RS_SRL {
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0x0:decode SRL {
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0: srl({{ Rd = Rt.uw >> SA; }});
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//Hardcoded assuming 32-bit ISA, probably need parameter here
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1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
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//Hardcoded assuming 32-bit ISA, probably need parameter here
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1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
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}
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}
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0x3: sra({{ Rd = Rt.sw >> SA; }});
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0x3: decode RS {
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0x0: sra({{
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uint32_t temp = Rt >> SA;
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if ( (Rt & 0x80000000) > 0 ) {
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uint32_t mask = 0x80000000;
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for(int i=0; i < SA; i++) {
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temp |= mask;
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mask = mask >> 1;
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}
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}
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Rd = temp;
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}});
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}
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0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
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@ -61,7 +77,21 @@ decode OPCODE_HI default Unknown::unknown() {
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1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
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}
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0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }});
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0x7: srav({{
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int shift_amt = Rs<4:0>;
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uint32_t temp = Rt >> shift_amt;
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if ( (Rt & 0x80000000) > 0 ) {
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uint32_t mask = 0x80000000;
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for(int i=0; i < shift_amt; i++) {
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temp |= mask;
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mask = mask >> 1;
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}
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}
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Rd = temp;
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}});
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}
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}
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@ -130,23 +160,27 @@ decode OPCODE_HI default Unknown::unknown() {
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}
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}
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0x4: decode FUNCTION_LO {
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format IntOp {
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0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
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0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
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0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
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0x3: subu({{ Rd.sw = Rs.sw - Rt.uw;}});
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0x4: and({{ Rd = Rs & Rt;}});
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0x5: or({{ Rd = Rs | Rt;}});
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0x6: xor({{ Rd = Rs ^ Rt;}});
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0x7: nor({{ Rd = ~(Rs | Rt);}});
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0x4: decode HINT {
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0x0: decode FUNCTION_LO {
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format IntOp {
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0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}});
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0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
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0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}});
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0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
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0x4: and({{ Rd = Rs & Rt;}});
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0x5: or({{ Rd = Rs | Rt;}});
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0x6: xor({{ Rd = Rs ^ Rt;}});
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0x7: nor({{ Rd = ~(Rs | Rt);}});
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}
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}
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}
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0x5: decode FUNCTION_LO {
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format IntOp{
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0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
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0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
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0x5: decode HINT {
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0x0: decode FUNCTION_LO {
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format IntOp{
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0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
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0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
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}
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}
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}
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@ -216,8 +250,13 @@ decode OPCODE_HI default Unknown::unknown() {
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format Branch {
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0x4: beq({{ cond = (Rs.sw == Rt.sw); }});
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0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
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0x6: blez({{ cond = (Rs.sw <= 0); }});
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0x7: bgtz({{ cond = (Rs.sw > 0); }});
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0x6: decode RT {
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0x0: blez({{ cond = (Rs.sw <= 0); }});
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}
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0x7: decode RT {
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0x0: bgtz({{ cond = (Rs.sw > 0); }});
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}
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}
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}
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@ -226,11 +265,14 @@ decode OPCODE_HI default Unknown::unknown() {
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0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
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0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
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0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
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0x3: sltiu({{ Rt.sw = ( Rs.sw < imm ) ? 1 : 0 }});
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0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}});
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0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}});
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0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}});
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0x7: lui({{ Rt = INTIMM << 16}});
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0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
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0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
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0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
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0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
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0x7: decode RS {
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0x0: lui({{ Rt = imm << 16}});
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}
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}
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}
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@ -352,13 +394,37 @@ decode OPCODE_HI default Unknown::unknown() {
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0x0: decode RS_HI {
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0x0: decode RS_LO {
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format FloatOp {
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0x0: mfc1({{ /*Rt.uw = Fs.ud<31:0>;*/ }});
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0x2: cfc1({{ /*Rt.uw = xc->readMiscReg(FPCR[Fs]);*/}});
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0x3: mfhc1({{ /*Rt.uw = Fs.ud<63:32>*/;}});
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0x4: mtc1({{ /*Fs = Rt.uw*/}});
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0x6: ctc1({{ /*xc->setMiscReg(FPCR[Fs],Rt);*/}});
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0x7: mthc1({{ /*Fs<63:32> = Rt.uw*/}});
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format WarnUnimpl {
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0x0: mfc1();//{{ /*Rt.uw = Fs.ud<31:0>;*/ }}
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0x3: mfhc1();// /*Rt.uw = Fs.ud<63:32>*/;
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0x4: mtc1();// /*Fs = Rt.uw*/
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0x7: mthc1();//{{/*Fs<63:32> = Rt.uw*/}}
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}
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format System {
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0x2: cfc1({{
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uint32_t fcsr_reg = xc->readMiscReg(FCSR);
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if (Fs == 0){
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Rt = xc->readMiscReg(FIR);
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} else if (Fs == 25) {
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Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23;
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} else if (Fs == 26) {
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Rt = 0 | (fcsr_reg & 0x0003F07C);
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} else if (Fs == 28) {
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Rt = 0 | (fcsr_reg);
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} else if (Fs == 31) {
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Rt = fcsr_reg;
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} else {
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panic("FP Control Value (%d) Not Available. Ignoring Access to"
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"Floating Control Status Register",fcsr_reg);
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}
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}});
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0x6: ctc1({{
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/*xc->setMiscReg(FPCR[Fs],Rt);*/
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}});
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}
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}
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@ -830,14 +896,14 @@ decode OPCODE_HI default Unknown::unknown() {
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0x7: decode FUNCTION_HI {
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0x0: decode FUNCTION_LO {
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format WarnUnimpl {
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format FailUnimpl {
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0x1: ext();
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0x4: ins();
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}
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}
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0x1: decode FUNCTION_LO {
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format WarnUnimpl {
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format FailUnimpl {
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0x0: fork();
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0x1: yield();
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}
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@ -847,16 +913,16 @@ decode OPCODE_HI default Unknown::unknown() {
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//Table A-10 MIPS32 BSHFL Encoding of sa Field
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0x4: decode SA {
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0x02: WarnUnimpl::wsbh();
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0x02: FailUnimpl::wsbh();
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format BasicOp {
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0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}});
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0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}});
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0x10: seb({{ Rd.sw = Rt<7:0>}});
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0x18: seh({{ Rd.sw = Rt<15:0>}});
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}
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}
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0x6: decode FUNCTION_LO {
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0x7: BasicOp::rdhwr({{ /*Rt = xc->hwRegs[RD];*/ }});
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0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }}
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}
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}
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}
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@ -865,11 +931,97 @@ decode OPCODE_HI default Unknown::unknown() {
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format LoadMemory {
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0x0: lb({{ Rt.sw = Mem.sb; }});
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0x1: lh({{ Rt.sw = Mem.sh; }});
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0x2: lwl({{ uint32_t temp = Mem.uw<31:16> << 16; Rt.uw &= 0x00FF; Rt.uw |= temp;}}, {{ EA = (Rs + disp) & ~3; }});
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0x2: lwl({{
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uint32_t mem_word = Mem.uw;
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uint32_t unalign_addr = Rs + disp;
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uint32_t offset = unalign_addr & 0x00000003;
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#if BYTE_ORDER == BIG_ENDIAN
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std::cout << "Big Endian Byte Order\n";
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switch(offset)
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{
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case 0:
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Rt = mem_word;
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break;
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case 1:
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Rt &= 0x000F;
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Rt |= (mem_word << 4);
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break;
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case 2:
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Rt &= 0x00FF;
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Rt |= (mem_word << 8);
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break;
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case 3:
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Rt &= 0x0FFF;
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Rt |= (mem_word << 12);
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break;
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default:
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panic("lwl: bad offset");
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}
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#elif BYTE_ORDER == LITTLE_ENDIAN
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std::cout << "Little Endian Byte Order\n";
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switch(offset)
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{
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case 0:
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Rt &= 0x0FFF;
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Rt |= (mem_word << 12);
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break;
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case 1:
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Rt &= 0x00FF;
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Rt |= (mem_word << 8);
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break;
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case 2:
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Rt &= 0x000F;
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Rt |= (mem_word << 4);
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break;
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case 3:
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Rt = mem_word;
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break;
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default:
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panic("lwl: bad offset");
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}
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#endif
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}}, {{ EA = (Rs + disp) & ~3; }});
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0x3: lw({{ Rt.sw = Mem.sw; }});
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0x4: lbu({{ Rt.uw = Mem.ub; }});
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0x5: lhu({{ Rt.uw = Mem.uh; }});
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0x6: lwr({{ uint32_t temp = 0x00FF & Mem.uw<15:0>; Rt.uw &= 0xFF00; Rt.uw |= temp; }}, {{ EA = (Rs + disp) & ~3; }});
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0x6: lwr({{
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uint32_t mem_word = Mem.uw;
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uint32_t unalign_addr = Rs + disp;
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uint32_t offset = unalign_addr & 0x00000003;
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#if BYTE_ORDER == BIG_ENDIAN
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switch(offset)
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{
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case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break;
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case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break;
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case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break;
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case 3: Rt = mem_word; break;
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default: panic("lwr: bad offset");
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}
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#elif BYTE_ORDER == LITTLE_ENDIAN
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switch(offset)
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{
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case 0: Rt = mem_word; break;
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case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break;
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case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break;
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case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break;
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default: panic("lwr: bad offset");
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}
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#endif
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}},
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{{ EA = (Rs + disp) & ~3; }});
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}
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0x7: FailUnimpl::reserved();
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@ -879,9 +1031,144 @@ decode OPCODE_HI default Unknown::unknown() {
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format StoreMemory {
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0x0: sb({{ Mem.ub = Rt<7:0>; }});
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0x1: sh({{ Mem.uh = Rt<15:0>; }});
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0x2: swl({{ Mem.uh = Rt<31:16>; }}, {{ EA = (Rs + disp) & ~3; }});
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0x2: swl({{
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uint32_t mem_word = 0;
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uint32_t aligned_addr = (Rs + disp) & ~3;
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uint32_t unalign_addr = Rs + disp;
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uint32_t offset = unalign_addr & 0x00000003;
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DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x",
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aligned_addr,unalign_addr,offset);
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fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
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#if BYTE_ORDER == BIG_ENDIAN
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switch(offset)
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{
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case 0:
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Mem = Rt;
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break;
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case 1:
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mem_word &= 0xF000;
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mem_word |= (Rt >> 4);
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Mem = mem_word;
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break;
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case 2:
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mem_word &= 0xFF00;
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mem_word |= (Rt >> 8);
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Mem = mem_word;
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break;
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case 3:
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mem_word &= 0xFFF0;
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mem_word |= (Rt >> 12);
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Mem = mem_word;
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break;
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default:
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panic("swl: bad offset");
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}
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#elif BYTE_ORDER == LITTLE_ENDIAN
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switch(offset)
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{
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case 0:
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mem_word &= 0xFFF0;
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mem_word |= (Rt >> 12);
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Mem = mem_word;
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break;
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case 1:
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mem_word &= 0xFF00;
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mem_word |= (Rt >> 8);
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Mem = mem_word;
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break;
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case 2:
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mem_word &= 0xF000;
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mem_word |= (Rt >> 4);
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Mem = mem_word;
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break;
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case 3:
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Mem = Rt;
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break;
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default:
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panic("swl: bad offset");
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}
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#endif
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}},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT);
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0x3: sw({{ Mem.uw = Rt<31:0>; }});
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0x6: swr({{ Mem.uh = Rt<15:0>; }},{{ EA = ((Rs + disp) & ~3) + 4;}});
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0x6: swr({{
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uint32_t mem_word = 0;
|
||||
uint32_t aligned_addr = (Rs + disp) & ~3;
|
||||
uint32_t unalign_addr = Rs + disp;
|
||||
uint32_t offset = unalign_addr & 0x00000003;
|
||||
|
||||
fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags);
|
||||
|
||||
#if BYTE_ORDER == BIG_ENDIAN
|
||||
switch(offset)
|
||||
{
|
||||
case 0:
|
||||
mem_word &= 0x0FFF;
|
||||
mem_word |= (Rt << 12);
|
||||
Mem = mem_word;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
mem_word &= 0x00FF;
|
||||
mem_word |= (Rt << 8);
|
||||
Mem = mem_word;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
mem_word &= 0x000F;
|
||||
mem_word |= (Rt << 4);
|
||||
Mem = mem_word;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
Mem = Rt;
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("swr: bad offset");
|
||||
}
|
||||
#elif BYTE_ORDER == LITTLE_ENDIAN
|
||||
switch(offset)
|
||||
{
|
||||
case 0:
|
||||
Mem = Rt;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
mem_word &= 0x000F;
|
||||
mem_word |= (Rt << 4);
|
||||
Mem = mem_word;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
mem_word &= 0x00FF;
|
||||
mem_word |= (Rt << 8);
|
||||
Mem = mem_word;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
mem_word &= 0x0FFF;
|
||||
mem_word |= (Rt << 12);
|
||||
Mem = mem_word;
|
||||
break;
|
||||
|
||||
default:
|
||||
panic("swr: bad offset");
|
||||
}
|
||||
#endif
|
||||
}},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT);
|
||||
}
|
||||
|
||||
format WarnUnimpl {
|
||||
|
|
@ -891,7 +1178,7 @@ decode OPCODE_HI default Unknown::unknown() {
|
|||
}
|
||||
|
||||
0x6: decode OPCODE_LO default FailUnimpl::reserved() {
|
||||
0x0: WarnUnimpl::ll();
|
||||
0x0: FailUnimpl::ll();
|
||||
|
||||
format LoadMemory {
|
||||
0x1: lwc1({{ /*F_t<31:0> = Mem.sf; */}});
|
||||
|
|
@ -901,7 +1188,7 @@ decode OPCODE_HI default Unknown::unknown() {
|
|||
|
||||
|
||||
0x7: decode OPCODE_LO default FailUnimpl::reserved() {
|
||||
0x0: WarnUnimpl::sc();
|
||||
0x0: FailUnimpl::sc();
|
||||
|
||||
format StoreMemory {
|
||||
0x1: swc1({{ //Mem.sf = Ft<31:0>; }});
|
||||
|
|
|
|||
|
|
@ -179,7 +179,7 @@ output decoder {{
|
|||
ss << ",";
|
||||
}
|
||||
|
||||
Addr target = pc + 8 + disp;
|
||||
Addr target = pc + 4 + disp;
|
||||
|
||||
std::string str;
|
||||
if (symtab && symtab->findSymbol(target, str))
|
||||
|
|
|
|||
|
|
@ -29,17 +29,19 @@ output header {{
|
|||
{
|
||||
protected:
|
||||
|
||||
int32_t imm;
|
||||
int16_t imm;
|
||||
int32_t sextImm;
|
||||
uint32_t zextImm;
|
||||
|
||||
/// Constructor
|
||||
IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
|
||||
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
|
||||
MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
|
||||
sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
|
||||
{
|
||||
//If Bit 15 is 1 then Sign Extend
|
||||
int32_t temp = imm & 0x00008000;
|
||||
|
||||
int32_t temp = sextImm & 0x00008000;
|
||||
if (temp > 0 && mnemonic != "lui") {
|
||||
imm |= 0xFFFF0000;
|
||||
sextImm |= 0xFFFF0000;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -99,9 +101,9 @@ output decoder {{
|
|||
}
|
||||
|
||||
if( mnemonic == "lui")
|
||||
ccprintf(ss, "%08p ", imm);
|
||||
ccprintf(ss, "%08p ", sextImm);
|
||||
else
|
||||
ss << (int) imm;
|
||||
ss << (int) sextImm;
|
||||
|
||||
return ss.str();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -199,23 +199,8 @@ def template LoadMemAccExecute {{
|
|||
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
EA = xc->getEA();
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
|
||||
%(code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
//Fill in Code for Out-of-Order CPUs
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
|
@ -251,18 +236,8 @@ def template LoadInitiateAcc {{
|
|||
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_src_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
|
||||
}
|
||||
|
||||
//Fill in Code for Out-of-Order CPUs
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
|
@ -274,21 +249,7 @@ def template LoadCompleteAcc {{
|
|||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_src_decl)s;
|
||||
%(op_dest_decl)s;
|
||||
|
||||
memcpy(&Mem, data, sizeof(Mem));
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
//Fill in Code for Out-of-Order CPUs
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
|
@ -299,33 +260,8 @@ def template StoreMemAccExecute {{
|
|||
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
uint64_t write_result = 0;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_decl)s;
|
||||
%(op_rd)s;
|
||||
EA = xc->getEA();
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
|
||||
memAccessFlags, &write_result);
|
||||
if (traceData) { traceData->setData(Mem); }
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
//Fill in Code for Out-of-Order CPUs
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
|
@ -370,26 +306,8 @@ def template StoreInitiateAcc {{
|
|||
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
|
||||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Addr EA;
|
||||
Fault fault = NoFault;
|
||||
uint64_t write_result = 0;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_src_decl)s;
|
||||
%(op_dest_decl)s;
|
||||
%(op_rd)s;
|
||||
%(ea_code)s;
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(memacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
|
||||
memAccessFlags, &write_result);
|
||||
if (traceData) { traceData->setData(Mem); }
|
||||
}
|
||||
|
||||
//Fill in Code for Out-of-Order CPUs
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
|
@ -401,21 +319,7 @@ def template StoreCompleteAcc {{
|
|||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
Fault fault = NoFault;
|
||||
uint64_t write_result = 0;
|
||||
|
||||
%(fp_enable_check)s;
|
||||
%(op_dest_decl)s;
|
||||
|
||||
memcpy(&write_result, data, sizeof(write_result));
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(postacc_code)s;
|
||||
}
|
||||
|
||||
if (fault == NoFault) {
|
||||
%(op_wb)s;
|
||||
}
|
||||
|
||||
//Fill in Code for Out-of-Order CPUs
|
||||
return fault;
|
||||
}
|
||||
}};
|
||||
|
|
@ -448,6 +352,14 @@ def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
|
|||
exec_template_base = 'Store')
|
||||
}};
|
||||
|
||||
def format UnalignedStore(memacc_code, postacc_code,
|
||||
ea_code = {{ EA = Rb + disp; }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
(header_output, decoder_output, decode_block, exec_output) = \
|
||||
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
||||
postacc_code, exec_template_base = 'Store')
|
||||
}};
|
||||
|
||||
//FP loads are offloaded to these formats for now ...
|
||||
def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
|
||||
mem_flags = [], inst_flags = []) {{
|
||||
|
|
|
|||
|
|
@ -110,7 +110,8 @@ output exec {{
|
|||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
panic("attempt to execute unimplemented instruction '%s' "
|
||||
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
|
||||
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
|
||||
inst2string(machInst));
|
||||
return new UnimplementedOpcodeFault;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -26,12 +26,34 @@
|
|||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
output header {{
|
||||
std::string inst2string(MachInst machInst);
|
||||
}};
|
||||
output decoder {{
|
||||
|
||||
std::string inst2string(MachInst machInst)
|
||||
{
|
||||
string str = "";
|
||||
uint32_t mask = 0x80000000;
|
||||
|
||||
for(int i=0; i < 32; i++) {
|
||||
if ((machInst & mask) == 0) {
|
||||
str += "0";
|
||||
} else {
|
||||
str += "1";
|
||||
}
|
||||
|
||||
mask = mask >> 1;
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
|
||||
std::string
|
||||
Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
|
||||
{
|
||||
return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
|
||||
"unknown", machInst, OPCODE);
|
||||
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
|
||||
"unknown", machInst, OPCODE, inst2string(machInst));
|
||||
}
|
||||
}};
|
||||
|
||||
|
|
@ -41,7 +63,7 @@ output exec {{
|
|||
Trace::InstRecord *traceData) const
|
||||
{
|
||||
panic("attempt to execute unknown instruction "
|
||||
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
|
||||
"(inst 0x%08x, opcode 0x%x, binary: %s)", machInst, OPCODE, inst2string(machInst));
|
||||
return new UnimplementedOpcodeFault;
|
||||
}
|
||||
}};
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ def operands {{
|
|||
'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
|
||||
'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
|
||||
|
||||
'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
||||
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
|
||||
|
||||
'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
|
||||
'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ class SyscallReturn {
|
|||
template <class T>
|
||||
SyscallReturn(T v, bool s)
|
||||
{
|
||||
retval = (uint64_t)v;
|
||||
retval = (uint32_t)v;
|
||||
success = s;
|
||||
}
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ class SyscallReturn {
|
|||
SyscallReturn(T v)
|
||||
{
|
||||
success = (v >= 0);
|
||||
retval = (uint64_t)v;
|
||||
retval = (uint32_t)v;
|
||||
}
|
||||
|
||||
~SyscallReturn() {}
|
||||
|
|
@ -137,7 +137,7 @@ namespace MipsISA
|
|||
|
||||
const int SyscallNumReg = ReturnValueReg1;
|
||||
const int SyscallPseudoReturnReg = ReturnValueReg1;
|
||||
const int SyscallSuccessReg = ReturnValueReg1;
|
||||
const int SyscallSuccessReg = ArgumentReg3;
|
||||
|
||||
const int LogVMPageSize = 13; // 8K bytes
|
||||
const int VMPageSize = (1 << LogVMPageSize);
|
||||
|
|
@ -162,7 +162,7 @@ namespace MipsISA
|
|||
MiscReg_DepTag = 67
|
||||
};
|
||||
|
||||
typedef uint64_t IntReg;
|
||||
typedef uint32_t IntReg;
|
||||
typedef IntReg IntRegFile[NumIntRegs];
|
||||
|
||||
/* floating point register file entry type
|
||||
|
|
@ -240,7 +240,7 @@ namespace MipsISA
|
|||
|
||||
// cop-0/cop-1 system control register file
|
||||
typedef uint64_t MiscReg;
|
||||
//typedef MiscReg MiscRegFile[NumMiscRegs];
|
||||
//typedef MiscReg MiscRegFile[NumMiscRegs];
|
||||
class MiscRegFile {
|
||||
|
||||
protected:
|
||||
|
|
@ -451,6 +451,7 @@ namespace MipsISA
|
|||
Hi,
|
||||
Lo,
|
||||
FCSR,
|
||||
FIR,
|
||||
FPCR,
|
||||
|
||||
//Alpha Regs, but here now, for
|
||||
|
|
@ -589,21 +590,15 @@ extern const Addr PageOffset;
|
|||
|
||||
static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
|
||||
{
|
||||
// check for error condition. Alpha syscall convention is to
|
||||
// indicate success/failure in reg a3 (r19) and put the
|
||||
// return value itself in the standard return value reg (v0).
|
||||
if (return_value.successful()) {
|
||||
// no error
|
||||
regs->intRegFile[ReturnValueReg1] = 0;
|
||||
regs->intRegFile[ReturnValueReg2] = return_value.value();
|
||||
regs->intRegFile[SyscallSuccessReg] = 0;
|
||||
regs->intRegFile[ReturnValueReg1] = return_value.value();
|
||||
} else {
|
||||
// got an error, return details
|
||||
regs->intRegFile[ReturnValueReg1] = (IntReg) -1;
|
||||
regs->intRegFile[ReturnValueReg2] = -return_value.value();
|
||||
regs->intRegFile[SyscallSuccessReg] = (IntReg) -1;
|
||||
regs->intRegFile[ReturnValueReg1] = -return_value.value();
|
||||
}
|
||||
|
||||
//regs->intRegFile[ReturnValueReg1] = (IntReg)return_value;
|
||||
//panic("Returning from syscall\n");
|
||||
}
|
||||
|
||||
// Machine operations
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 14 */ SyscallDesc("mknod", unimplementedFunc),
|
||||
/* 15 */ SyscallDesc("chmod", chmodFunc<Linux>),
|
||||
/* 16 */ SyscallDesc("lchown", chownFunc),
|
||||
/* 17 */ SyscallDesc("break", unimplementedFunc), /*obreak*/
|
||||
/* 17 */ SyscallDesc("break", obreakFunc), /*obreak*/
|
||||
/* 18 */ SyscallDesc("unused#18", unimplementedFunc),
|
||||
/* 19 */ SyscallDesc("lseek", lseekFunc),
|
||||
/* 20 */ SyscallDesc("getpid", getpidFunc),
|
||||
|
|
@ -160,7 +160,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 42 */ SyscallDesc("pipe", unimplementedFunc),
|
||||
/* 43 */ SyscallDesc("times", unimplementedFunc),
|
||||
/* 44 */ SyscallDesc("prof", unimplementedFunc),
|
||||
/* 45 */ SyscallDesc("brk", unimplementedFunc),/*openFunc<Linux>*/
|
||||
/* 45 */ SyscallDesc("brk", obreakFunc),/*openFunc<Linux>*/
|
||||
/* 46 */ SyscallDesc("setgid", unimplementedFunc),
|
||||
/* 47 */ SyscallDesc("getgid", getgidFunc),
|
||||
/* 48 */ SyscallDesc("signal", ignoreFunc),
|
||||
|
|
@ -182,13 +182,13 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 64 */ SyscallDesc("getppid", getpagesizeFunc),
|
||||
/* 65 */ SyscallDesc("getpgrp", unimplementedFunc),
|
||||
/* 66 */ SyscallDesc("setsid", unimplementedFunc),
|
||||
/* 67 */ SyscallDesc("sigaction", statFunc<Linux>),
|
||||
/* 68 */ SyscallDesc("sgetmask", lstatFunc<Linux>),
|
||||
/* 67 */ SyscallDesc("sigaction",unimplementedFunc),
|
||||
/* 68 */ SyscallDesc("sgetmask", unimplementedFunc),
|
||||
/* 69 */ SyscallDesc("ssetmask", unimplementedFunc),
|
||||
/* 70 */ SyscallDesc("setreuid", unimplementedFunc),
|
||||
/* 71 */ SyscallDesc("setregid", mmapFunc<Linux>),
|
||||
/* 71 */ SyscallDesc("setregid", unimplementedFunc),
|
||||
/* 72 */ SyscallDesc("sigsuspend", unimplementedFunc),
|
||||
/* 73 */ SyscallDesc("sigpending", munmapFunc),
|
||||
/* 73 */ SyscallDesc("sigpending", unimplementedFunc),
|
||||
/* 74 */ SyscallDesc("sethostname", ignoreFunc),
|
||||
/* 75 */ SyscallDesc("setrlimit", unimplementedFunc),
|
||||
/* 76 */ SyscallDesc("getrlimit", unimplementedFunc),
|
||||
|
|
@ -206,7 +206,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 88 */ SyscallDesc("reboot", unimplementedFunc),
|
||||
/* 89 */ SyscallDesc("readdir", unimplementedFunc),
|
||||
/* 90 */ SyscallDesc("mmap", mmapFunc<Linux>),
|
||||
/* 91 */ SyscallDesc("munmap",unimplementedFunc),/*fstatFunc<Linux>*/
|
||||
/* 91 */ SyscallDesc("munmap",munmapFunc),
|
||||
/* 92 */ SyscallDesc("truncate", fcntlFunc),
|
||||
/* 93 */ SyscallDesc("ftruncate", unimplementedFunc),
|
||||
/* 94 */ SyscallDesc("fchmod", unimplementedFunc),
|
||||
|
|
@ -221,9 +221,9 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 103 */ SyscallDesc("syslog", unimplementedFunc),
|
||||
/* 104 */ SyscallDesc("setitimer", unimplementedFunc),
|
||||
/* 105 */ SyscallDesc("getitimer", unimplementedFunc),
|
||||
/* 106 */ SyscallDesc("stat", unimplementedFunc),
|
||||
/* 106 */ SyscallDesc("stat", statFunc<Linux>),
|
||||
/* 107 */ SyscallDesc("lstat", unimplementedFunc),
|
||||
/* 108 */ SyscallDesc("fstat", unimplementedFunc),
|
||||
/* 108 */ SyscallDesc("fstat", fstatFunc<Linux>),
|
||||
/* 109 */ SyscallDesc("unused#109", unimplementedFunc),
|
||||
/* 110 */ SyscallDesc("iopl", unimplementedFunc),
|
||||
/* 111 */ SyscallDesc("vhangup", unimplementedFunc),
|
||||
|
|
@ -240,7 +240,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 122 */ SyscallDesc("uname", unameFunc),
|
||||
/* 123 */ SyscallDesc("modify_ldt", unimplementedFunc),
|
||||
/* 124 */ SyscallDesc("adjtimex", unimplementedFunc),
|
||||
/* 125 */ SyscallDesc("mprotect", unimplementedFunc),
|
||||
/* 125 */ SyscallDesc("mprotect", ignoreFunc),
|
||||
/* 126 */ SyscallDesc("sigprocmask", unimplementedFunc),
|
||||
/* 127 */ SyscallDesc("create_module", unimplementedFunc),
|
||||
/* 128 */ SyscallDesc("init_module", unimplementedFunc),
|
||||
|
|
@ -329,8 +329,8 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 211 */ SyscallDesc("truncate64", unimplementedFunc),
|
||||
/* 212 */ SyscallDesc("ftruncate64", unimplementedFunc),
|
||||
/* 213 */ SyscallDesc("stat64", unimplementedFunc),
|
||||
/* 214 */ SyscallDesc("lstat64", unimplementedFunc),
|
||||
/* 215 */ SyscallDesc("fstat64", unimplementedFunc),
|
||||
/* 214 */ SyscallDesc("lstat64", lstat64Func<Linux>),
|
||||
/* 215 */ SyscallDesc("fstat64", fstat64Func<Linux>),
|
||||
/* 216 */ SyscallDesc("pivot_root", unimplementedFunc),
|
||||
/* 217 */ SyscallDesc("mincore", unimplementedFunc),
|
||||
/* 218 */ SyscallDesc("madvise", unimplementedFunc),
|
||||
|
|
@ -361,7 +361,7 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = {
|
|||
/* 243 */ SyscallDesc("io_getevents", unimplementedFunc),
|
||||
/* 244 */ SyscallDesc("io_submit", unimplementedFunc),
|
||||
/* 245 */ SyscallDesc("io_cancel", unimplementedFunc),
|
||||
/* 246 */ SyscallDesc("exit_group", unimplementedFunc),
|
||||
/* 246 */ SyscallDesc("exit_group", exitFunc),
|
||||
/* 247 */ SyscallDesc("lookup_dcookie", unimplementedFunc),
|
||||
/* 248 */ SyscallDesc("epoll_create", unimplementedFunc),
|
||||
/* 249 */ SyscallDesc("epoll_ctl", unimplementedFunc),
|
||||
|
|
@ -415,8 +415,6 @@ MipsLinuxProcess::MipsLinuxProcess(const std::string &name,
|
|||
//init_regs->intRegFile[0] = 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
SyscallDesc*
|
||||
MipsLinuxProcess::getDesc(int callnum)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -397,8 +397,9 @@ class StaticInst : public StaticInstBase
|
|||
int getRs() { return (machInst & 0x03E00000) >> 21; } //25...21
|
||||
int getRt() { return (machInst & 0x001F0000) >> 16; } //20...16
|
||||
int getRd() { return (machInst & 0x0000F800) >> 11; } //15...11
|
||||
int getOpname(){ return (machInst & 0x0000003F); }//5...0
|
||||
int getBranch(){ return (machInst & 0x0000FFFF); }//5...0
|
||||
int getImm() { return (machInst & 0x0000FFFF); } //15...0
|
||||
int getFunction(){ return (machInst & 0x0000003F); }//5...0
|
||||
int getBranch(){ return (machInst & 0x0000FFFF); }//15...0
|
||||
int getJump(){ return (machInst & 0x03FFFFFF); }//5...0
|
||||
int getHint(){ return (machInst & 0x000007C0) >> 6; } //10...6
|
||||
std::string getName() { return mnemonic; }
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ PageTable::~PageTable()
|
|||
}
|
||||
|
||||
Fault
|
||||
PageTable::page_check(Addr addr, int size) const
|
||||
PageTable::page_check(Addr addr, int size, uint32_t flags) const
|
||||
{
|
||||
if (size < sizeof(uint64_t)) {
|
||||
if (!isPowerOf2(size)) {
|
||||
|
|
@ -66,7 +66,7 @@ PageTable::page_check(Addr addr, int size) const
|
|||
return genMachineCheckFault();
|
||||
}
|
||||
|
||||
if ((size - 1) & addr)
|
||||
if (((size - 1) & addr) && (flags & NO_ALIGN_FAULT == 0))
|
||||
return genAlignmentFault();
|
||||
}
|
||||
else {
|
||||
|
|
@ -75,7 +75,7 @@ PageTable::page_check(Addr addr, int size) const
|
|||
return genMachineCheckFault();
|
||||
}
|
||||
|
||||
if ((sizeof(uint64_t) - 1) & addr)
|
||||
if (((sizeof(uint64_t) - 1) & addr) && (flags & NO_ALIGN_FAULT == 0))
|
||||
return genAlignmentFault();
|
||||
}
|
||||
|
||||
|
|
@ -127,5 +127,5 @@ PageTable::translate(CpuRequestPtr &req)
|
|||
if (!translate(req->vaddr, req->paddr)) {
|
||||
return genMachineCheckFault();
|
||||
}
|
||||
return page_check(req->paddr, req->size);
|
||||
return page_check(req->paddr, req->size, req->flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ class PageTable
|
|||
Addr pageAlign(Addr a) { return (a & ~offsetMask); }
|
||||
Addr pageOffset(Addr a) { return (a & offsetMask); }
|
||||
|
||||
Fault page_check(Addr addr, int size) const;
|
||||
Fault page_check(Addr addr, int size, uint32_t flags) const;
|
||||
|
||||
void allocate(Addr vaddr, int size);
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,8 @@ const unsigned NO_FAULT = 0x020;
|
|||
const unsigned PF_EXCLUSIVE = 0x100;
|
||||
/** The request should be marked as LRU. */
|
||||
const unsigned EVICT_NEXT = 0x200;
|
||||
/** The request should ignore unaligned access faults */
|
||||
const unsigned NO_ALIGN_FAULT = 0x400;
|
||||
|
||||
class Request
|
||||
{
|
||||
|
|
|
|||
|
|
@ -48,13 +48,15 @@ using namespace TheISA;
|
|||
void
|
||||
SyscallDesc::doSyscall(int callnum, Process *process, ExecContext *xc)
|
||||
{
|
||||
DPRINTFR(SyscallVerbose, "%s: syscall %s called\n",
|
||||
xc->getCpuPtr()->name(), name);
|
||||
DPRINTFR(SyscallVerbose, "%d: %s: syscall %s called w/arguments %d,%d,%d,%d\n",
|
||||
curTick,xc->getCpuPtr()->name(), name,
|
||||
xc->getSyscallArg(0),xc->getSyscallArg(1),
|
||||
xc->getSyscallArg(2),xc->getSyscallArg(3));
|
||||
|
||||
SyscallReturn retval = (*funcPtr)(this, callnum, process, xc);
|
||||
|
||||
DPRINTFR(SyscallVerbose, "%s: syscall %s returns %d\n",
|
||||
xc->getCpuPtr()->name(), name, retval.value());
|
||||
DPRINTFR(SyscallVerbose, "%d: %s: syscall %s returns %d\n",
|
||||
curTick,xc->getCpuPtr()->name(), name, retval.value());
|
||||
|
||||
if (!(flags & SyscallDesc::SuppressReturnValue))
|
||||
xc->setSyscallReturn(retval);
|
||||
|
|
@ -65,8 +67,6 @@ SyscallReturn
|
|||
unimplementedFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
//warn("ignoring syscall %s(%d, %d, ...)", desc->name,
|
||||
// xc->getSyscallArg(0), xc->getSyscallArg(1));
|
||||
fatal("syscall %s (#%d) unimplemented.", desc->name, callnum);
|
||||
|
||||
return 1;
|
||||
|
|
|
|||
Loading…
Reference in a new issue