Move op_class.hh out of encumbered/cpu/full and into cpu.
Pull opClassStrings array out of encumbered/cpu/full/fu_pool.cc and move to new cpu/op_class.cc file. SConscript: Add new cpu-model-independent file to define OpClass enum strings. cpu/op_class.hh: Fix comments etc. cpu/static_inst.hh: op_class.hh moved to cpu directory --HG-- rename : encumbered/cpu/full/op_class.hh => cpu/op_class.hh extra : convert_revision : 314ac5ab7cc5c6a34b43dc1c2f2adc3e02f6d07f
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4 changed files with 71 additions and 20 deletions
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@ -86,6 +86,7 @@ base_sources = Split('''
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cpu/base.cc
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cpu/exec_context.cc
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cpu/exetrace.cc
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cpu/op_class.cc
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cpu/pc_event.cc
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cpu/static_inst.cc
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cpu/sampler/sampler.cc
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50
cpu/op_class.cc
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50
cpu/op_class.cc
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@ -0,0 +1,50 @@
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/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/op_class.hh"
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/** OpClass enum -> description string */
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const char *
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opClassStrings[Num_OpClasses] =
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{
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"(null)",
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"IntAlu",
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"IntMult",
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"IntDiv",
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"FloatAdd",
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"FloatCmp",
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"FloatCvt",
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"FloatMult",
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"FloatDiv",
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"FloatSqrt",
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"MemRead",
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"MemWrite",
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"IprAccess",
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"InstPrefetch"
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};
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@ -26,8 +26,8 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ENCUMBERED_CPU_FULL_OP_CLASS_HH__
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#define __ENCUMBERED_CPU_FULL_OP_CLASS_HH__
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#ifndef __CPU__OP_CLASS_HH__
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#define __CPU__OP_CLASS_HH__
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/**
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* @file
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* assigning instructions to functional units.
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*/
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enum OpClass {
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No_OpClass = 0, /* inst does not use a functional unit */
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IntAluOp, /* integer ALU */
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IntMultOp, /* integer multiplier */
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IntDivOp, /* integer divider */
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FloatAddOp, /* floating point adder/subtractor */
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FloatCmpOp, /* floating point comparator */
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FloatCvtOp, /* floating point<->integer converter */
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FloatMultOp, /* floating point multiplier */
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FloatDivOp, /* floating point divider */
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FloatSqrtOp, /* floating point square root */
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MemReadOp, /* memory read port */
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MemWriteOp, /* memory write port */
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IprAccessOp, /* Internal Processor Register read/write port */
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InstPrefetchOp, /* instruction prefetch port (on I-cache) */
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Num_OpClasses /* total functional unit classes */
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No_OpClass = 0, ///< Instruction does not use a functional unit
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IntAluOp, ///< Integer ALU operaton (add/sub/logical)
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IntMultOp, ///< Integer multiply
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IntDivOp, ///< Integer divide
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FloatAddOp, ///< Floating point add/subtract
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FloatCmpOp, ///< Floating point comparison
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FloatCvtOp, ///< Floating point<->integer conversion
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FloatMultOp, ///< Floating point multiply
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FloatDivOp, ///< Floating point divide
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FloatSqrtOp, ///< Floating point square root
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MemReadOp, ///< Memory read port
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MemWriteOp, ///< Memory write port
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IprAccessOp, ///< Internal Processor Register read/write port
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InstPrefetchOp, ///< Instruction prefetch port (on I-cache)
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Num_OpClasses ///< Total number of operation classes
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};
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/**
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* Array mapping OpClass enum values to strings. Defined in fu_pool.cc.
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* Array mapping OpClass enum values to strings. Defined in op_class.cc.
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*/
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extern const char *opClassStrings[];
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#endif // __ENCUMBERED_CPU_FULL_OP_CLASS_HH__
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#endif // __CPU__OP_CLASS_HH__
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@ -34,7 +34,7 @@
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#include "base/hashmap.hh"
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#include "base/refcnt.hh"
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#include "encumbered/cpu/full/op_class.hh"
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#include "cpu/op_class.hh"
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#include "sim/host.hh"
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#include "targetarch/isa_traits.hh"
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