Commit graph

4046 commits

Author SHA1 Message Date
Ali Saidi
f72a999393 some forgotten commits
--HG--
extra : convert_revision : 213440066c700ed5891a6d4568928b7f3f2fe750
2007-02-12 18:40:08 -05:00
Ali Saidi
49a9378718 make hver match legion
--HG--
extra : convert_revision : 5bfe4b943ca5b3e30a7097a46cab4f93dadd714f
2007-02-12 13:58:03 -05:00
Ali Saidi
b9005f3562 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

src/cpu/simple/atomic.cc:
    merge steve's changes in.

--HG--
extra : convert_revision : a17eda37cd63c9380af6fe68b0aef4b1e1974231
2007-02-12 13:22:36 -05:00
Ali Saidi
b5a4d95811 rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
    add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
    Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
    Make atomic memory ops atomic
    Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
    add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
    remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
    swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
    add a post access code block
src/arch/sparc/isa/includes.isa:
    need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
    add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    add support for twinloads
    add support for swap and conditional swap instructions
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
    Add support for atomic swap memory commands
src/mem/packet_access.hh:
    Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
    Add support for atomic swap memory commands
    Rename sc code to extradata

--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2007-02-12 13:06:30 -05:00
Steve Reinhardt
ad17b32651 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 496428e23050122a8a0029e5fddea261bef5729e
2007-02-12 09:27:32 -08:00
Steve Reinhardt
f78bc80bd7 Move store conditional result checking from SimpleAtomicCpu write
function into Alpha ISA description.  write now just generically
returns a result value if the res pointer is non-null (which means
we can only provide a res pointer if we expect a valid result
value).

--HG--
extra : convert_revision : fb1c315515787f5fbbf7d1af7e428bdbfe8148b8
2007-02-12 09:26:47 -08:00
Nathan Binkert
da1ad46482 cleanup
--HG--
extra : convert_revision : 84114216854dfcd468115bbf5398333e98056a58
2007-02-12 06:26:52 -08:00
Nathan Binkert
88c1c20dc3 Get rid of the FetchTrace since it doesn't appear to be
used anywhere at all.

--HG--
extra : convert_revision : 141a45f2ec8ff3d82fdc787ded459ff28c109763
2007-02-12 06:24:39 -08:00
Nathan Binkert
184decd196 Clean up tracing stuff more, get rid of the trace log since
its not all that useful. Fix a few bugs with python/C++
integration.

--HG--
extra : convert_revision : a706512f7dc8b0c88f1ff96fe35ab8fbf9548b78
2007-02-10 15:14:50 -08:00
Nathan Binkert
63a8240059 Get rid of the Random context and add the support directly to python.
We don't currently use randomness much, so I didn't go too far, but
in the future, we may want to actually expose the random number values
themselves to python.  For now, I'll at least let you seed it.
While we're at it, clean up a clearly bad way for generating random
doubles.

--HG--
extra : convert_revision : df2aa8b58dd0d9c2a7c771668a760b2df8db1e11
2007-02-09 16:44:02 -08:00
Nathan Binkert
81c5d0e3d8 Clean up from my last commit to the trace stuff.
--HG--
extra : convert_revision : b6a975d1c4195a764ba875bc3aaaa064be4955b7
2007-02-09 16:30:06 -08:00
Nathan Binkert
895716248f Remove tracing file that's no longer needed
--HG--
extra : convert_revision : 2c216ae8bb6a2ae70aea7ecc641d2417b3f5e0b5
2007-02-09 14:49:14 -08:00
Nathan Binkert
a24ccc1ef2 Get rid of the Trace ParamContext and give python direct
access to enabling/disabling tracing.  Command line is
unchanged except for the removal of --trace-cycle since
it's not so clear what that means.

--HG--
extra : convert_revision : c0164d92d3615d76d0c6acaabaafd92a9278212a
2007-02-09 14:39:56 -08:00
Nathan Binkert
27c2138882 Use c99 variadic macros for non gnu compilers
--HG--
extra : convert_revision : 4e9fda42e9f5ed3e9f66e5bd178c45537792073b
2007-02-08 20:59:11 -08:00
Nathan Binkert
1f834b569c Get rid of the gross operator,()/variadic macro hack
that made ccprintf and friends work, turn it into a
normal function (though it still has a slightly strange
implementation.)  All instances of variadic macros
are not yet removed, but I know how, and it will happen.

One side effect of this new implementation is that a
cprintf statement can now only have 16 parameters, though
it's easy enough to raise this number if needed.

--HG--
extra : convert_revision : 85cb3c17f8e2ecf9cd2f31ea80a760a28ea127a7
2007-02-07 22:11:30 -08:00
Nathan Binkert
af698e8b05 Quick program to time how long ccprintf takes to write
to a stream compared to sprintf to a buffer.

--HG--
extra : convert_revision : de80724943d18aa110aa39cde9414252d9a7944c
2007-02-07 22:02:09 -08:00
Steve Reinhardt
2ec4a6c071 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : c56b8160b403fde235636ca5b5b4cecd206ffa4c
2007-02-07 22:33:44 -05:00
Ali Saidi
fdaff2b108 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 60aabc4b93ef9d742f7e07363bd51f24170b85b8
2007-02-07 16:43:47 -05:00
Steve Reinhardt
6b37bb6710 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
2007-02-07 10:55:14 -08:00
Steve Reinhardt
997fc505a8 Make memory commands dense again to avoid cache stat table explosion.
Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.

--HG--
extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-07 10:53:37 -08:00
Steve Reinhardt
23d970e6b9 More DPRINTF cleanup.
--HG--
extra : convert_revision : db89cea42b46476d19333038522a6c144eafdab1
2007-02-06 23:53:48 -08:00
Nathan Binkert
a19e9ea5fc Initialize the variable to something.
--HG--
extra : convert_revision : bfe1e70130719ff239987d725b089c6d7152c541
2007-02-06 22:32:37 -08:00
Nathan Binkert
38db47005c Include compiler.hh since we use some of the #defines
--HG--
extra : convert_revision : 1040addcf3f52d8d9fed2930890dadf524205af9
2007-02-06 22:31:15 -08:00
Steve Reinhardt
51e54f519d Minor DPRINTF fixes.
--HG--
extra : convert_revision : 41956c9a480163ecac7807982215027e8ff1a4a9
2007-02-06 21:53:05 -08:00
Steve Reinhardt
d486700149 Add short memtest run to quick regressions.
Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.

--HG--
extra : convert_revision : 210fe4abecc19fbab0b15402c6cb4863650bab66
2007-02-06 21:16:33 -08:00
Ali Saidi
8ffd12e807 merge my index fix and lisa's fix
--HG--
extra : convert_revision : 5f2c7d46c96fa061bbfb66edf188d405ca600020
2007-02-06 18:47:42 -05:00
Ali Saidi
c7a1fdacd6 mark ldst[0] instrutions at DelayedCommit so we don't take an interrupt in the middle of one
--HG--
extra : convert_revision : 671549c2f0361679bc1e128744dcb60f44ea021e
2007-02-06 18:22:33 -05:00
Kevin Lim
310d8f0992 Fix for LL/SC that Ron sent me.
--HG--
extra : convert_revision : b3510a23d8a9eb466939f38491a109c3a65a7363
2007-02-06 15:54:44 -05:00
Ali Saidi
ebb6972dd3 more fp fixes
fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
    get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
    move the cexec into the aexec field
src/cpu/exetrace.cc:
    copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
    fix unaligned accesses in the memory mapped disk device

--HG--
extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528
2007-02-06 15:52:33 -05:00
Steve Reinhardt
98ef836ca6 Use perl FindBin package to set path to rundiff to the
directory where tracediff is.

--HG--
extra : convert_revision : f0cc0af264aa624cbacbf3ba42b6b64f90a8e759
2007-02-06 10:06:11 -08:00
Steve Reinhardt
572addee5d Fix for previous commit: need to ifdef NDEBUG on the
definition as well as the declaration.

--HG--
extra : convert_revision : 4f073fa6b47bf21abf58d92cb1c9eed699c9c89e
2007-02-06 10:04:44 -08:00
Steve Reinhardt
f5a803f56e Use an instance counter to give Events repeatable IDs
in debugging mode (especially valuable for tracediff).

--HG--
extra : convert_revision : 227434a06b5271a8300f2f6861bd06c4ac19e6c4
2007-02-05 22:05:00 -08:00
Ali Saidi
ecef27f172 more sparc fixes
src/arch/sparc/isa/decoder.isa:
    fix rdgsr fault check
src/arch/sparc/tlb.cc:
    block asis are now supported

--HG--
extra : convert_revision : cf55d648d2c5184fab03b6fe057d0e33c1dfc393
2007-02-02 19:02:27 -05:00
Ali Saidi
665ddde57a make interrupt code serialize itself and fix indenting
--HG--
extra : convert_revision : d0bb23c7922568586b640084ac719e809cc8422f
2007-02-02 18:05:21 -05:00
Ali Saidi
592f35ac0f fix mostly floating point related
src/arch/sparc/floatregfile.cc:
    fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
    fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
    add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
    include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
    print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
    fix printing of float registers

--HG--
extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
2007-02-02 18:04:42 -05:00
Lisa Hsu
17cbfe55fd Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5

--HG--
extra : convert_revision : 62a0017a1147631513db7878f4e4d08fca776bc1
2007-02-01 15:35:26 -05:00
Lisa Hsu
1e8bbb81cb only increment numPosted if an interrupt of that type hasn't been posted before.
--HG--
extra : convert_revision : 6671c594b78d2e38449069157f39af96b81340f2
2007-02-01 15:34:52 -05:00
Gabe Black
8a244ef040 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem

--HG--
extra : convert_revision : c02e184f69251dc6eeccdcb244788365aa12f7ee
2007-01-31 19:44:50 -05:00
Gabe Black
559460e33a Create reference outputs for this regression.
--HG--
extra : convert_revision : 91e0144fef3f66d413417ad0318f43f752494e3c
2007-01-31 18:47:23 -05:00
Ali Saidi
5c7192daed make sparc fs less chatty
src/SConscript:
    strip doesn't take a src and dest in solaris

--HG--
extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
2007-01-31 18:32:27 -05:00
Ali Saidi
36a1912bf0 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : 276b640c5c5a51e88e9bd630960ad462d9f0cb8d
2007-01-30 18:27:16 -05:00
Ali Saidi
ac36fb6e64 add fsr to the list of registers we are interested in
--HG--
extra : convert_revision : 2cc0d0144abab264aa0ec8c07242cdab2dffd4f8
2007-01-30 18:27:04 -05:00
Ali Saidi
fc79ace502 Make SPARC checkpointing work
src/arch/sparc/floatregfile.cc:
    Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
    fix serialization for intreg
src/arch/sparc/miscregfile.cc:
    fix serialization from miscreg
src/arch/sparc/pagetable.cc:
    fix serialization for page table
src/arch/sparc/regfile.cc:
    need to serialize nnpc
src/arch/sparc/tlb.cc:
    write serialization code for tlb
src/cpu/base.cc:
    provide a way to find the thread number a context is
    serialize the instruction counter
src/cpu/base.hh:
    provide a way to find the thread number a context is
    and given a thread number find a context pointer
src/cpu/cpuevent.hh:
    provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
    nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
    Make findObj() work (it hasn't since we did the python conversion stuff)

--HG--
extra : convert_revision : a95bc4e3c3354304171efbe3797556fdb146bea2
2007-01-30 18:25:39 -05:00
Ali Saidi
3fa5816dcf fix some checkpointing annoyances
-m works as you think it should
Ctrl-C actually ends the simulation now

--HG--
extra : convert_revision : f2269dc90d165c716459ec61f5f7b1ea3c1d4ae2
2007-01-30 18:21:42 -05:00
Gabe Black
cf0ba1dfb0 Merge zizzer:/bk/newmem
into  zower.eecs.umich.edu:/eecshome/m5/newmem

--HG--
extra : convert_revision : 7b332ee4c737206511d26db391117eb1fe5ea290
2007-01-30 16:12:47 -05:00
Gabe Black
efb14c585b Implemented fbfss and fbpfcc instructions, and cleaned up branch code a little.
src/arch/sparc/isa/base.isa:
    Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
    Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
    Minor cleanup.

--HG--
extra : convert_revision : 6586b46418f1f70bace41407f267fee30c657714
2007-01-30 16:12:38 -05:00
Ali Saidi
8bc4925775 change std::isnan() to a using namespace std and isnan(). We need a better way to do this.
--HG--
extra : convert_revision : 4f59ca8e6425db23f57a1f3f65a4874e483d0ecc
2007-01-30 14:43:25 -05:00
Ali Saidi
e82e5b5084 use std:: for isnan() and fix decoding of fcmpe*
--HG--
extra : convert_revision : 06be0f8572e26c3c7e761b482248304ce1afa038
2007-01-30 11:22:22 -05:00
Gabe Black
0cdcd207ac sizeof with a pointer to dynamically allocated memory will return the size of the pointer, not the memory.
--HG--
extra : convert_revision : 04647d9fa0c464960d37797717f8171862cf48f8
2007-01-30 02:45:59 -05:00
Gabe Black
a4a87daad1 Make clearSingleStep in SPARC a warning, and rephrase the panic for setSingleStep
--HG--
extra : convert_revision : fde27a1faa6c03a24a4321a153dfa89a438f9a32
2007-01-30 02:44:24 -05:00