Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : c56b8160b403fde235636ca5b5b4cecd206ffa4c
This commit is contained in:
commit
2ec4a6c071
10 changed files with 377 additions and 229 deletions
|
@ -69,22 +69,25 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
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switch(width)
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{
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case SingleWidth:
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float32_t result32;
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uint32_t result32;
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float32_t fresult32;
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memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
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result = htog(result32);
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DPRINTF(Sparc, "Read FP32 register %d = 0x%x\n", floatReg, result);
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result32 = htog(result32);
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memcpy(&fresult32, &result32, sizeof(result32));
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result = fresult32;
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DPRINTF(Sparc, "Read FP32 register %d = [%f]0x%x\n", floatReg, result, result32);
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break;
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case DoubleWidth:
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float64_t result64;
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uint64_t result64;
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float64_t fresult64;
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memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
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result = htog(result64);
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DPRINTF(Sparc, "Read FP64 register %d = 0x%x\n", floatReg, result);
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result64 = htog(result64);
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memcpy(&fresult64, &result64, sizeof(result64));
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result = fresult64;
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DPRINTF(Sparc, "Read FP64 register %d = [%f]0x%x\n", floatReg, result, result64);
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break;
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case QuadWidth:
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float128_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
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result = htog(result128);
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DPRINTF(Sparc, "Read FP128 register %d = 0x%x\n", floatReg, result);
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -113,10 +116,7 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
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DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result);
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break;
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case QuadWidth:
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uint64_t result128;
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memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
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result = htog(result128);
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DPRINTF(Sparc, "Read FP128 bits register %d = 0x%x\n", floatReg, result);
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panic("Quad width FP not implemented.");
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break;
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default:
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panic("Attempted to read a %d bit floating point register!", width);
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@ -132,15 +132,21 @@ Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
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uint32_t result32;
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uint64_t result64;
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float32_t fresult32;
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float64_t fresult64;
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switch(width)
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{
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case SingleWidth:
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result32 = gtoh((uint32_t)val);
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fresult32 = val;
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memcpy(&result32, &fresult32, sizeof(result32));
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result32 = gtoh(result32);
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memcpy(regSpace + 4 * floatReg, &result32, sizeof(result32));
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DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result32);
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break;
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case DoubleWidth:
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result64 = gtoh((uint64_t)val);
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fresult64 = val;
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memcpy(&result64, &fresult64, sizeof(result64));
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result64 = gtoh(result64);
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memcpy(regSpace + 4 * floatReg, &result64, sizeof(result64));
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DPRINTF(Sparc, "Write FP64 register %d = 0x%x\n", floatReg, result64);
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break;
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@ -46,164 +46,167 @@ enum interrupts_t {
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num_interrupt_types
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};
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class Interrupts
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class Interrupts
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{
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private:
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bool interrupts[num_interrupt_types];
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int numPosted;
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public:
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Interrupts()
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{
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for (int i = 0; i < num_interrupt_types; ++i) {
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interrupts[i] = false;
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}
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numPosted = 0;
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}
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void post(int int_type)
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{
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if (int_type < 0 || int_type >= num_interrupt_types)
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panic("posting unknown interrupt!\n");
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if (interrupts[int_type] == false) {
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interrupts[int_type] = true;
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++numPosted;
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}
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}
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void post(int int_num, int index)
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{
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private:
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}
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bool interrupts[num_interrupt_types];
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int numPosted;
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void clear(int int_num, int index)
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{
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public:
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Interrupts()
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{
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for (int i = 0; i < num_interrupt_types; ++i) {
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interrupts[i] = false;
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}
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numPosted = 0;
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}
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}
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void post(int int_type)
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{
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if (int_type < 0 || int_type >= num_interrupt_types)
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panic("posting unknown interrupt!\n");
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void clear_all()
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{
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if (interrupts[int_type] == false) {
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interrupts[int_type] = true;
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++numPosted;
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}
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}
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}
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void post(int int_num, int index)
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{
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bool check_interrupts(ThreadContext * tc) const
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{
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if (numPosted)
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return true;
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else
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return false;
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}
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}
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Fault getInterrupt(ThreadContext * tc)
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{
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int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
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int pstate = tc->readMiscReg(MISCREG_PSTATE);
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bool ie = pstate & PSTATE::ie;
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void clear(int int_num, int index)
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{
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}
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void clear_all()
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{
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}
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bool check_interrupts(ThreadContext * tc) const
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{
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if (numPosted)
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return true;
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else
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return false;
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}
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Fault getInterrupt(ThreadContext * tc)
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{
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int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
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int pstate = tc->readMiscReg(MISCREG_PSTATE);
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bool ie = pstate & PSTATE::ie;
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// THESE ARE IN ORDER OF PRIORITY
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// since there are early returns, and the highest
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// priority interrupts should get serviced,
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// it is v. important that new interrupts are inserted
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// in the right order of processing
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if (hpstate & HPSTATE::hpriv) {
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if (ie) {
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if (interrupts[hstick_match]) {
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if (tc->readMiscReg(MISCREG_HINTP) & 1) {
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interrupts[hstick_match] = false;
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--numPosted;
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return new HstickMatch;
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}
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}
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if (interrupts[interrupt_vector]) {
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed THIS YET
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return NoFault;
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}
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} else {
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if (interrupts[hstick_match]) {
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return NoFault;
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}
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}
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} else {
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if (interrupts[trap_level_zero]) {
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if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
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interrupts[trap_level_zero] = false;
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--numPosted;
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return new TrapLevelZero;
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}
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}
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// THESE ARE IN ORDER OF PRIORITY
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// since there are early returns, and the highest
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// priority interrupts should get serviced,
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// it is v. important that new interrupts are inserted
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// in the right order of processing
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if (hpstate & HPSTATE::hpriv) {
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if (ie) {
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if (interrupts[hstick_match]) {
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if (tc->readMiscReg(MISCREG_HINTP) & 1) {
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interrupts[hstick_match] = false;
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--numPosted;
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return new HstickMatch;
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}
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}
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}
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if (ie) {
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if (interrupts[cpu_mondo]) {
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interrupts[cpu_mondo] = false;
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--numPosted;
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return new CpuMondo;
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}
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if (interrupts[dev_mondo]) {
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interrupts[dev_mondo] = false;
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--numPosted;
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return new DevMondo;
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}
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if (interrupts[soft_interrupt]) {
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int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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// it seems that interrupt vectors are right in
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// the middle of interrupt levels with regard to
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// priority, so have to check
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if ((il < 6) &&
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interrupts[interrupt_vector]) {
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// may require more details here since there
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// may be lots of interrupts embedded in an
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// platform interrupt vector
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed YET
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return NoFault;
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} else {
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if (il > tc->readMiscReg(MISCREG_PIL)) {
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uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
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uint64_t more = si & ~(1 << (il + 1));
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if (!InterruptLevel(more)) {
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interrupts[soft_interrupt] = false;
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--numPosted;
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}
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return new InterruptLevelN(il);
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}
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}
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}
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if (interrupts[resumable_error]) {
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interrupts[resumable_error] = false;
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--numPosted;
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return new ResumableError;
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}
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if (interrupts[interrupt_vector]) {
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed THIS YET
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return NoFault;
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}
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} else {
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if (interrupts[hstick_match]) {
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return NoFault;
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}
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}
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} else {
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if (interrupts[trap_level_zero]) {
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if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
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interrupts[trap_level_zero] = false;
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--numPosted;
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return new TrapLevelZero;
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}
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}
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if (interrupts[hstick_match]) {
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if (tc->readMiscReg(MISCREG_HINTP) & 1) {
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interrupts[hstick_match] = false;
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--numPosted;
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return new HstickMatch;
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}
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}
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if (ie) {
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if (interrupts[cpu_mondo]) {
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interrupts[cpu_mondo] = false;
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--numPosted;
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return new CpuMondo;
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}
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if (interrupts[dev_mondo]) {
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interrupts[dev_mondo] = false;
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--numPosted;
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return new DevMondo;
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}
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if (interrupts[soft_interrupt]) {
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int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
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// it seems that interrupt vectors are right in
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// the middle of interrupt levels with regard to
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// priority, so have to check
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if ((il < 6) &&
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interrupts[interrupt_vector]) {
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// may require more details here since there
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// may be lots of interrupts embedded in an
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// platform interrupt vector
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interrupts[interrupt_vector] = false;
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--numPosted;
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//HAVEN'T IMPLed YET
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return NoFault;
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} else {
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if (il > tc->readMiscReg(MISCREG_PIL)) {
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uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
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uint64_t more = si & ~(1 << (il + 1));
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if (!InterruptLevel(more)) {
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interrupts[soft_interrupt] = false;
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--numPosted;
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}
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return new InterruptLevelN(il);
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}
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}
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}
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if (interrupts[resumable_error]) {
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interrupts[resumable_error] = false;
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--numPosted;
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return new ResumableError;
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}
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}
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return NoFault;
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}
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return NoFault;
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}
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void updateIntrInfo(ThreadContext * tc)
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{
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void updateIntrInfo(ThreadContext * tc)
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{
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}
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}
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void serialize(std::ostream &os)
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{
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}
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void serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(interrupts,num_interrupt_types);
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SERIALIZE_SCALAR(numPosted);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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}
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};
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(interrupts,num_interrupt_types);
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UNSERIALIZE_SCALAR(numPosted);
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}
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};
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} // namespace SPARC_ISA
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#endif // __ARCH_SPARC_INTERRUPT_HH__
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@ -479,10 +479,10 @@ decode OP default Unknown::unknown()
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0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
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//0x12 should cause an illegal instruction exception
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0x13: NoPriv::rdgsr({{
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if(Fprs<2:> == 0 || Pstate<4:> == 0)
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Rd = Gsr;
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else
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fault = new FpDisabled;
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fault = checkFpEnableFault(xc);
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if (fault)
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return fault;
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Rd = Gsr;
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}});
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//0x14-0x15 should cause an illegal instruction exception
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0x16: Priv::rdsoftint({{Rd = Softint;}});
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@ -718,7 +718,7 @@ decode OP default Unknown::unknown()
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0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
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}
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0x34: decode OPF{
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format BasicOperate{
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format FpBasic{
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0x01: fmovs({{
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Frds.uw = Frs2s.uw;
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//fsr.ftt = fsr.cexc = 0
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|
@ -765,7 +765,7 @@ decode OP default Unknown::unknown()
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0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
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0x43: FpUnimpl::faddq();
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0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
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0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
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0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
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0x47: FpUnimpl::fsubq();
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0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
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0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
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|
@ -776,26 +776,26 @@ decode OP default Unknown::unknown()
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0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
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0x6E: FpUnimpl::fdmulq();
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0x81: fstox({{
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Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
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Frd.sdw = static_cast<int64_t>(Frs2s.sf);
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}});
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0x82: fdtox({{
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Frd.df = (double)static_cast<int64_t>(Frs2.df);
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Frd.sdw = static_cast<int64_t>(Frs2.df);
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}});
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0x83: FpUnimpl::fqtox();
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0x84: fxtos({{
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Frds.sf = static_cast<float>((int64_t)Frs2.df);
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Frds.sf = static_cast<float>(Frs2.sdw);
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}});
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0x88: fxtod({{
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Frd.df = static_cast<double>((int64_t)Frs2.df);
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Frd.df = static_cast<double>(Frs2.sdw);
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}});
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0x8C: FpUnimpl::fxtoq();
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0xC4: fitos({{
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Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
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Frds.sf = static_cast<float>(Frs2s.sw);
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}});
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0xC6: fdtos({{Frds.sf = Frs2.df;}});
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0xC7: FpUnimpl::fqtos();
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0xC8: fitod({{
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Frd.df = static_cast<double>((int32_t)Frs2s.sf);
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Frd.df = static_cast<double>(Frs2s.sw);
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}});
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0xC9: fstod({{Frd.df = Frs2s.sf;}});
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0xCB: FpUnimpl::fqtod();
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|
@ -803,17 +803,23 @@ decode OP default Unknown::unknown()
|
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0xCD: FpUnimpl::fstoq();
|
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0xCE: FpUnimpl::fdtoq();
|
||||
0xD1: fstoi({{
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Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
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Frds.sw = static_cast<int32_t>(Frs2s.sf);
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||||
float t = Frds.sw;
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if (t != Frs2s.sf)
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Fsr = insertBits(Fsr, 4,0, 0x01);
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||||
}});
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0xD2: fdtoi({{
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||||
Frds.sf = (float)static_cast<int32_t>(Frs2.df);
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Frds.sw = static_cast<int32_t>(Frs2.df);
|
||||
double t = Frds.sw;
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||||
if (t != Frs2.df)
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||||
Fsr = insertBits(Fsr, 4,0, 0x01);
|
||||
}});
|
||||
0xD3: FpUnimpl::fqtoi();
|
||||
default: FailUnimpl::fpop1();
|
||||
}
|
||||
}
|
||||
0x35: decode OPF{
|
||||
format BasicOperate{
|
||||
format FpBasic{
|
||||
0x51: fcmps({{
|
||||
uint8_t fcc;
|
||||
if(isnan(Frs1s) || isnan(Frs2s))
|
||||
|
@ -831,11 +837,11 @@ decode OP default Unknown::unknown()
|
|||
}});
|
||||
0x52: fcmpd({{
|
||||
uint8_t fcc;
|
||||
if(isnan(Frs1s) || isnan(Frs2s))
|
||||
if(isnan(Frs1) || isnan(Frs2))
|
||||
fcc = 3;
|
||||
else if(Frs1s < Frs2s)
|
||||
else if(Frs1 < Frs2)
|
||||
fcc = 1;
|
||||
else if(Frs1s > Frs2s)
|
||||
else if(Frs1 > Frs2)
|
||||
fcc = 2;
|
||||
else
|
||||
fcc = 0;
|
||||
|
@ -860,11 +866,11 @@ decode OP default Unknown::unknown()
|
|||
}});
|
||||
0x56: fcmped({{
|
||||
uint8_t fcc = 0;
|
||||
if(isnan(Frs1s) || isnan(Frs2s))
|
||||
if(isnan(Frs1) || isnan(Frs2))
|
||||
fault = new FpExceptionIEEE754;
|
||||
if(Frs1s < Frs2s)
|
||||
if(Frs1 < Frs2)
|
||||
fcc = 1;
|
||||
else if(Frs1s > Frs2s)
|
||||
else if(Frs1 > Frs2)
|
||||
fcc = 2;
|
||||
uint8_t firstbit = 10;
|
||||
if(FCMPCC)
|
||||
|
@ -960,24 +966,24 @@ decode OP default Unknown::unknown()
|
|||
0x55: FailUnimpl::fpsub16s();
|
||||
0x56: FailUnimpl::fpsub32();
|
||||
0x57: FailUnimpl::fpsub32s();
|
||||
0x60: BasicOperate::fzero({{Frd.df = 0;}});
|
||||
0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
|
||||
0x60: FpBasic::fzero({{Frd.df = 0;}});
|
||||
0x61: FpBasic::fzeros({{Frds.sf = 0;}});
|
||||
0x62: FailUnimpl::fnor();
|
||||
0x63: FailUnimpl::fnors();
|
||||
0x64: FailUnimpl::fandnot2();
|
||||
0x65: FailUnimpl::fandnot2s();
|
||||
0x66: BasicOperate::fnot2({{
|
||||
0x66: FpBasic::fnot2({{
|
||||
Frd.df = (double)(~((uint64_t)Frs2.df));
|
||||
}});
|
||||
0x67: BasicOperate::fnot2s({{
|
||||
0x67: FpBasic::fnot2s({{
|
||||
Frds.sf = (float)(~((uint32_t)Frs2s.sf));
|
||||
}});
|
||||
0x68: FailUnimpl::fandnot1();
|
||||
0x69: FailUnimpl::fandnot1s();
|
||||
0x6A: BasicOperate::fnot1({{
|
||||
0x6A: FpBasic::fnot1({{
|
||||
Frd.df = (double)(~((uint64_t)Frs1.df));
|
||||
}});
|
||||
0x6B: BasicOperate::fnot1s({{
|
||||
0x6B: FpBasic::fnot1s({{
|
||||
Frds.sf = (float)(~((uint32_t)Frs1s.sf));
|
||||
}});
|
||||
0x6C: FailUnimpl::fxor();
|
||||
|
@ -988,18 +994,18 @@ decode OP default Unknown::unknown()
|
|||
0x71: FailUnimpl::fands();
|
||||
0x72: FailUnimpl::fxnor();
|
||||
0x73: FailUnimpl::fxnors();
|
||||
0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
|
||||
0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
|
||||
0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
|
||||
0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
|
||||
0x76: FailUnimpl::fornot2();
|
||||
0x77: FailUnimpl::fornot2s();
|
||||
0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
|
||||
0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
|
||||
0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
|
||||
0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
|
||||
0x7A: FailUnimpl::fornot1();
|
||||
0x7B: FailUnimpl::fornot1s();
|
||||
0x7C: FailUnimpl::for();
|
||||
0x7D: FailUnimpl::fors();
|
||||
0x7E: BasicOperate::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
|
||||
0x7F: BasicOperate::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
|
||||
0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
|
||||
0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
|
||||
0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
|
||||
0x81: FailUnimpl::siam();
|
||||
}
|
||||
|
@ -1236,16 +1242,32 @@ decode OP default Unknown::unknown()
|
|||
Rd.uw = uReg0;}}, {{EXT_ASI}});
|
||||
format Trap {
|
||||
0x20: Load::ldf({{Frds.uw = Mem.uw;}});
|
||||
0x21: decode X {
|
||||
0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
|
||||
0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
|
||||
0x21: decode RD {
|
||||
0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
|
||||
if (fault)
|
||||
return fault;
|
||||
Fsr = Mem.uw | Fsr<63:32>;}});
|
||||
0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
|
||||
if (fault)
|
||||
return fault;
|
||||
Fsr = Mem.udw;}});
|
||||
default: FailUnimpl::ldfsrOther();
|
||||
}
|
||||
0x22: ldqf({{fault = new FpDisabled;}});
|
||||
0x23: Load::lddf({{Frd.udw = Mem.udw;}});
|
||||
0x24: Store::stf({{Mem.uw = Frds.uw;}});
|
||||
0x25: decode X {
|
||||
0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
|
||||
0x1: Store::stxfsr({{Mem.udw = Fsr;}});
|
||||
0x25: decode RD {
|
||||
0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
|
||||
if (fault)
|
||||
return fault;
|
||||
Mem.uw = Fsr<31:0>;
|
||||
Fsr = insertBits(Fsr,16,14,0);}});
|
||||
0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
|
||||
if (fault)
|
||||
return fault;
|
||||
Mem.udw = Fsr;
|
||||
Fsr = insertBits(Fsr,16,14,0);}});
|
||||
default: FailUnimpl::stfsrOther();
|
||||
}
|
||||
0x26: stqf({{fault = new FpDisabled;}});
|
||||
0x27: Store::stdf({{Mem.udw = Frd.udw;}});
|
||||
|
|
|
@ -103,3 +103,46 @@ def format BasicOperate(code, *flags) {{
|
|||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
||||
def format FpBasic(code, *flags) {{
|
||||
fp_code = """
|
||||
Fsr |= bits(Fsr,4,0) << 5;
|
||||
Fsr = insertBits(Fsr,4,0,0);
|
||||
#if defined(__sun) || defined (__OpenBSD__)
|
||||
fp_rnd newrnd = FP_RN;
|
||||
switch (Fsr<31:30>) {
|
||||
case 0: newrnd = FP_RN; break;
|
||||
case 1: newrnd = FP_RZ; break;
|
||||
case 2: newrnd = FP_RP; break;
|
||||
case 3: newrnd = FP_RM; break;
|
||||
}
|
||||
fp_rnd oldrnd = fpsetround(newrnd);
|
||||
#else
|
||||
int newrnd = FE_TONEAREST;
|
||||
switch (Fsr<31:30>) {
|
||||
case 0: newrnd = FE_TONEAREST; break;
|
||||
case 1: newrnd = FE_TOWARDZERO; break;
|
||||
case 2: newrnd = FE_UPWARD; break;
|
||||
case 3: newrnd = FE_DOWNWARD; break;
|
||||
}
|
||||
int oldrnd = fegetround();
|
||||
fesetround(newrnd);
|
||||
#endif
|
||||
"""
|
||||
|
||||
fp_code += code
|
||||
|
||||
|
||||
fp_code += """
|
||||
#if defined(__sun) || defined (__OpenBSD__)
|
||||
fpsetround(oldrnd);
|
||||
#else
|
||||
fesetround(oldrnd);
|
||||
#endif
|
||||
"""
|
||||
iop = InstObjParams(name, Name, 'SparcStaticInst', fp_code, flags)
|
||||
header_output = BasicDeclare.subst(iop)
|
||||
decoder_output = BasicConstructor.subst(iop)
|
||||
decode_block = BasicDecode.subst(iop)
|
||||
exec_output = BasicExecute.subst(iop)
|
||||
}};
|
||||
|
|
|
@ -53,7 +53,7 @@ output decoder {{
|
|||
#include "cpu/thread_context.hh" // for Jump::branchTarget()
|
||||
#include "mem/packet.hh"
|
||||
|
||||
#if defined(linux)
|
||||
#if defined(linux) || defined(__APPLE__)
|
||||
#include <fenv.h>
|
||||
#endif
|
||||
#include <algorithm>
|
||||
|
@ -62,9 +62,14 @@ using namespace SparcISA;
|
|||
}};
|
||||
|
||||
output exec {{
|
||||
#if defined(linux)
|
||||
#if defined(linux) || defined(__APPLE__)
|
||||
#include <fenv.h>
|
||||
#endif
|
||||
|
||||
#if defined(__sun) || defined (__OpenBSD__)
|
||||
#include <ieeefp.h>
|
||||
#endif
|
||||
|
||||
#include <limits>
|
||||
|
||||
#include <cmath>
|
||||
|
|
|
@ -232,6 +232,7 @@ MiscReg MiscRegFile::readReg(int miscReg)
|
|||
|
||||
/** Floating Point Status Register */
|
||||
case MISCREG_FSR:
|
||||
DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
|
||||
return fsr;
|
||||
|
||||
case MISCREG_MMU_P_CONTEXT:
|
||||
|
@ -337,10 +338,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
|
|||
case MISCREG_PCR:
|
||||
case MISCREG_PIC:
|
||||
panic("Performance Instrumentation not impl\n");
|
||||
/** Floating Point Status Register */
|
||||
case MISCREG_FSR:
|
||||
warn("Reading FSR Floating Point not implemented\n");
|
||||
break;
|
||||
case MISCREG_SOFTINT_CLR:
|
||||
case MISCREG_SOFTINT_SET:
|
||||
panic("Can read from softint clr/set\n");
|
||||
|
@ -488,6 +485,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
|
|||
/** Floating Point Status Register */
|
||||
case MISCREG_FSR:
|
||||
fsr = val;
|
||||
DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
|
||||
break;
|
||||
|
||||
case MISCREG_MMU_P_CONTEXT:
|
||||
|
|
|
@ -668,8 +668,6 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
|
|||
if (!implicit && asi != ASI_P && asi != ASI_S) {
|
||||
if (AsiIsLittle(asi))
|
||||
panic("Little Endian ASIs not supported\n");
|
||||
if (AsiIsBlock(asi))
|
||||
panic("Block ASIs not supported\n");
|
||||
if (AsiIsNoFault(asi))
|
||||
panic("No Fault ASIs not supported\n");
|
||||
|
||||
|
@ -688,7 +686,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
|
|||
goto handleSparcErrorRegAccess;
|
||||
|
||||
if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
|
||||
!AsiIsTwin(asi))
|
||||
!AsiIsTwin(asi) && !AsiIsBlock(asi))
|
||||
panic("Accessing ASI %#X. Should we?\n", asi);
|
||||
}
|
||||
|
||||
|
|
|
@ -411,8 +411,14 @@ Trace::InstRecord::dump(ostream &outs)
|
|||
if(shared_data->y !=
|
||||
thread->readIntReg(NumIntArchRegs + 1))
|
||||
diffY = true;
|
||||
if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR))
|
||||
if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) {
|
||||
diffFsr = true;
|
||||
if (mbits(shared_data->fsr, 63,10) ==
|
||||
mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) {
|
||||
thread->setMiscReg(MISCREG_FSR, shared_data->fsr);
|
||||
diffFsr = false;
|
||||
}
|
||||
}
|
||||
//if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
|
||||
if(shared_data->ccr !=
|
||||
thread->readIntReg(NumIntArchRegs + 2))
|
||||
|
@ -450,16 +456,13 @@ Trace::InstRecord::dump(ostream &outs)
|
|||
diffTlb = true;
|
||||
}
|
||||
|
||||
if ((diffPC || diffCC || diffInst || diffIntRegs ||
|
||||
if (diffPC || diffCC || diffInst || diffIntRegs ||
|
||||
diffFpRegs || diffTpc || diffTnpc || diffTstate ||
|
||||
diffTt || diffHpstate || diffHtstate || diffHtba ||
|
||||
diffPstate || diffY || diffCcr || diffTl || diffFsr ||
|
||||
diffGl || diffAsi || diffPil || diffCwp || diffCansave ||
|
||||
diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
|
||||
&& !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
|
||||
&& !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
|
||||
&& shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1)
|
||||
) {
|
||||
{
|
||||
|
||||
outs << "Differences found between M5 and Legion:";
|
||||
if (diffPC)
|
||||
|
@ -639,7 +642,7 @@ Trace::InstRecord::dump(ostream &outs)
|
|||
char label[8];
|
||||
sprintf(label, "%%f%d", x);
|
||||
printRegPair(outs, label,
|
||||
thread->readFloatRegBits(x,FloatRegFile::DoubleWidth),
|
||||
thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth),
|
||||
shared_data->fpregs[x]);
|
||||
}
|
||||
}
|
||||
|
@ -667,7 +670,7 @@ Trace::InstRecord::dump(ostream &outs)
|
|||
}
|
||||
|
||||
diffcount++;
|
||||
if (diffcount > 2)
|
||||
if (diffcount > 3)
|
||||
fatal("Differences found between Legion and M5\n");
|
||||
} else
|
||||
diffcount = 0;
|
||||
|
|
|
@ -47,7 +47,7 @@
|
|||
MmDisk::MmDisk(Params *p)
|
||||
: BasicPioDevice(p), image(p->image), curSector((uint64_t)-1), dirty(false)
|
||||
{
|
||||
std::memset(&bytes, 0, SectorSize);
|
||||
std::memset(&diskData, 0, SectorSize);
|
||||
pioSize = image->size() * SectorSize;
|
||||
}
|
||||
|
||||
|
@ -57,9 +57,9 @@ MmDisk::read(PacketPtr pkt)
|
|||
Addr accessAddr;
|
||||
off_t sector;
|
||||
off_t bytes_read;
|
||||
uint16_t *d16;
|
||||
uint32_t *d32;
|
||||
uint64_t *d64;
|
||||
uint16_t d16;
|
||||
uint32_t d32;
|
||||
uint64_t d64;
|
||||
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
|
@ -68,26 +68,34 @@ MmDisk::read(PacketPtr pkt)
|
|||
sector = accessAddr / SectorSize;
|
||||
|
||||
if (sector != curSector) {
|
||||
if (dirty)
|
||||
bytes_read = image->write(bytes, curSector);
|
||||
bytes_read = image->read(bytes, sector);
|
||||
if (dirty) {
|
||||
bytes_read = image->write(diskData, curSector);
|
||||
assert(bytes_read == SectorSize);
|
||||
}
|
||||
bytes_read = image->read(diskData, sector);
|
||||
assert(bytes_read == SectorSize);
|
||||
curSector = sector;
|
||||
}
|
||||
switch (pkt->getSize()) {
|
||||
case sizeof(uint8_t):
|
||||
pkt->set(bytes[accessAddr % SectorSize]);
|
||||
pkt->set(diskData[accessAddr % SectorSize]);
|
||||
DPRINTF(IdeDisk, "reading byte %#x value= %#x\n", accessAddr, diskData[accessAddr %
|
||||
SectorSize]);
|
||||
break;
|
||||
case sizeof(uint16_t):
|
||||
d16 = (uint16_t*)bytes + (accessAddr % SectorSize)/2;
|
||||
pkt->set(htobe(*d16));
|
||||
memcpy(&d16, diskData + (accessAddr % SectorSize), 2);
|
||||
pkt->set(htobe(d32));
|
||||
DPRINTF(IdeDisk, "reading word %#x value= %#x\n", accessAddr, d16);
|
||||
break;
|
||||
case sizeof(uint32_t):
|
||||
d32 = (uint32_t*)bytes + (accessAddr % SectorSize)/4;
|
||||
pkt->set(htobe(*d32));
|
||||
memcpy(&d32, diskData + (accessAddr % SectorSize), 4);
|
||||
pkt->set(htobe(d32));
|
||||
DPRINTF(IdeDisk, "reading dword %#x value= %#x\n", accessAddr, d32);
|
||||
break;
|
||||
case sizeof(uint64_t):
|
||||
d64 = (uint64_t*)bytes + (accessAddr % SectorSize)/8;
|
||||
pkt->set(htobe(*d64));
|
||||
memcpy(&d64, diskData + (accessAddr % SectorSize), 8);
|
||||
pkt->set(htobe(d64));
|
||||
DPRINTF(IdeDisk, "reading qword %#x value= %#x\n", accessAddr, d64);
|
||||
break;
|
||||
default:
|
||||
panic("Invalid access size\n");
|
||||
|
@ -100,10 +108,73 @@ MmDisk::read(PacketPtr pkt)
|
|||
Tick
|
||||
MmDisk::write(PacketPtr pkt)
|
||||
{
|
||||
panic("need to implement\n");
|
||||
M5_DUMMY_RETURN
|
||||
Addr accessAddr;
|
||||
off_t sector;
|
||||
off_t bytes_read;
|
||||
uint16_t d16;
|
||||
uint32_t d32;
|
||||
uint64_t d64;
|
||||
|
||||
assert(pkt->result == Packet::Unknown);
|
||||
assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
|
||||
accessAddr = pkt->getAddr() - pioAddr;
|
||||
|
||||
sector = accessAddr / SectorSize;
|
||||
|
||||
if (sector != curSector) {
|
||||
if (dirty) {
|
||||
bytes_read = image->write(diskData, curSector);
|
||||
assert(bytes_read == SectorSize);
|
||||
}
|
||||
bytes_read = image->read(diskData, sector);
|
||||
assert(bytes_read == SectorSize);
|
||||
curSector = sector;
|
||||
}
|
||||
dirty = true;
|
||||
|
||||
switch (pkt->getSize()) {
|
||||
case sizeof(uint8_t):
|
||||
diskData[accessAddr % SectorSize] = htobe(pkt->get<uint8_t>());
|
||||
DPRINTF(IdeDisk, "writing byte %#x value= %#x\n", accessAddr, diskData[accessAddr %
|
||||
SectorSize]);
|
||||
break;
|
||||
case sizeof(uint16_t):
|
||||
d16 = htobe(pkt->get<uint16_t>());
|
||||
memcpy(diskData + (accessAddr % SectorSize), &d16, 2);
|
||||
DPRINTF(IdeDisk, "writing word %#x value= %#x\n", accessAddr, d16);
|
||||
break;
|
||||
case sizeof(uint32_t):
|
||||
d32 = htobe(pkt->get<uint32_t>());
|
||||
memcpy(diskData + (accessAddr % SectorSize), &d32, 4);
|
||||
DPRINTF(IdeDisk, "writing dword %#x value= %#x\n", accessAddr, d32);
|
||||
break;
|
||||
case sizeof(uint64_t):
|
||||
d64 = htobe(pkt->get<uint64_t>());
|
||||
memcpy(diskData + (accessAddr % SectorSize), &d64, 8);
|
||||
DPRINTF(IdeDisk, "writing qword %#x value= %#x\n", accessAddr, d64);
|
||||
break;
|
||||
default:
|
||||
panic("Invalid access size\n");
|
||||
}
|
||||
|
||||
pkt->result = Packet::Success;
|
||||
return pioDelay;
|
||||
}
|
||||
|
||||
void
|
||||
MmDisk::serialize(std::ostream &os)
|
||||
{
|
||||
// just write any dirty changes to the cow layer it will take care of
|
||||
// serialization
|
||||
int bytes_read;
|
||||
if (dirty) {
|
||||
bytes_read = image->write(diskData, curSector);
|
||||
assert(bytes_read == SectorSize);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
|
||||
Param<Addr> pio_addr;
|
||||
|
|
|
@ -46,10 +46,7 @@ class MmDisk : public BasicPioDevice
|
|||
DiskImage *image;
|
||||
off_t curSector;
|
||||
bool dirty;
|
||||
union {
|
||||
uint8_t bytes[SectorSize];
|
||||
uint32_t words[SectorSize/4];
|
||||
};
|
||||
uint8_t diskData[SectorSize];
|
||||
|
||||
public:
|
||||
struct Params : public BasicPioDevice::Params
|
||||
|
@ -64,6 +61,8 @@ class MmDisk : public BasicPioDevice
|
|||
|
||||
virtual Tick read(PacketPtr pkt);
|
||||
virtual Tick write(PacketPtr pkt);
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
};
|
||||
|
||||
#endif //__DEV_SPARC_MM_DISK_HH__
|
||||
|
|
Loading…
Reference in a new issue