Commit graph

229 commits

Author SHA1 Message Date
Steve Reinhardt
d727c2b6cf Fix Lisa's CPU trace system check for syscall emulation.
cpu/exetrace.cc:
    CPU system name check doesn't work under syscall emulation, so don't
    compile it in.

--HG--
extra : convert_revision : 2c128bf759877222107652fd86323be6dc71a34c
2005-11-10 20:30:04 -05:00
Lisa Hsu
3532a661c5 just commit what i need for dumping traces compatible with intel's casper
--HG--
extra : convert_revision : a0c4a68a576fa771fd553eaedd6a07255a04dca2
2005-11-09 16:42:36 -05:00
Nathan Binkert
a81c03737a Add new function profiling stuff, wrap the pc_sample stuff into it.
SConscript:
    Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
    DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
    Add profiling stuff
kern/kernel_stats.hh:
    Use a smart pointer
sim/system.cc:
sim/system.hh:
    Create a new symbol table that has all of the symbols for a
    particular system
util/stats/categories.py:
    change around the categories, add categories for function
    profiling stuff
util/stats/profile.py:
    No profile parsing and display code to deal with function
    profiling stuff, graph, dot, and text outputs.

--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
2005-10-18 19:07:42 -04:00
Lisa Hsu
7b04cd9561 add a flag that supercedes all other InstExec flags to print a trace in the Intel sim compatible format.
--HG--
extra : convert_revision : 19569e5645f2d68fb68a0352753c08c2a24bfdc4
2005-10-09 18:20:54 -04:00
Steve Reinhardt
e90332ff7a Minor cleanup of memtest.
cpu/memtest/memtest.cc:
    Call random() consistently (not sometimes rand() and sometimes random()).
    Don't bother to call random() for copy-only parameters unless we're
    actually doing a copy.

--HG--
extra : convert_revision : 50ef72594ad53ba531584b3c9dde61ac036a4e38
2005-10-03 09:13:56 -04:00
Steve Reinhardt
d60de7122d Add functions to System object to set up function-based events,
including automatically fixing up addresses to deal with
optionally executed Alpha gp update prolog.

SConscript:
    Remove freebsd_events.cc and linux_events.cc.
base/remote_gdb.cc:
cpu/pc_event.cc:
kern/system_events.cc:
kern/system_events.hh:
    PCEvents now schedule themselves in constructor.
cpu/pc_event.hh:
    PCEvents now schedule themselves in the constructor.
    Get rid of constructor versions that don't take an address and
    all the schedule() methods that are now unnecessary.
kern/freebsd/freebsd_system.cc:
kern/freebsd/freebsd_system.hh:
    Use new System methods to schedule function-based events.
    Move FreeBSD-specific function event classes into FreebsdSystem.
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
    Use new System methods to schedule function-based events.
    Move Linux-specific function event classes into LinuxSystem.
kern/tru64/tru64_events.hh:
    PCEvents now schedule themselves in constructor.
    Add DebugPrintfrEvent to encapsulate raw setting as new type
    (to work better with new System function-event method.)
kern/tru64/tru64_system.cc:
    Use new System methods to schedule function-based events.
kern/tru64/tru64_system.hh:
    Add DebugPrintfrEvent to encapsulate raw setting as new type
    (to work better with new System function-event method.)
sim/system.cc:
sim/system.hh:
    Add functions to set up function-based events, including
    automatically fixing up addresses to deal with optionally
    executed Alpha gp update prolog.

--HG--
extra : convert_revision : c2cf09144297b6602afe755a34a0a2227023783f
2005-09-24 14:20:29 -04:00
Steve Reinhardt
c4793184bd Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.  Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.

SConscript:
    MySQL detection moved to SConstruct.
    Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
    Revamp fenv.h support... most of the ugliness is hidden
    in base/fenv.hh now.
base/mysql.hh:
    Fix typo in #ifndef guard.
build/SConstruct:
    Build options are set via a build_options file in the
    build directory instead of being inferred from the name
    of the build directory.
    Options are passed to C++ via config/*.hh files instead of
    via the command line.
python/SConscript:
    Generate m5_build_env directly from scons options
    instead of indirectly via CPPDEFINES.
python/m5/convert.py:
    Allow '0' and '1' for booleans.
    Rewrite toBool to use dict.
base/fenv.hh:
    Revamp <fenv.h> support to make it a compile option
    (so we can test w/o it even if it's present) and to
    make isa_desc cleaner.

--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
2005-08-30 13:18:54 -04:00
Miguel Serrano
b64eae5e52 Changes for getting FreeBSD to run.
SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
2005-08-15 16:59:58 -04:00
Nathan Binkert
8a0bc84022 Allow CPUs to specify their own CPU ids.
Make the AlphaConsole calculate the number of CPUs instead
of passing that in as a parameter.

cpu/base.cc:
    pass the desired cpu_id into registerExecContext, offsetting it
    by the thread number.  a cpu_id of -1 means that it should be
    generated for you.
cpu/base.hh:
    Take the cpu_id as a parameter
cpu/o3/alpha_cpu_builder.cc:
cpu/simple/cpu.cc:
    Accept the cpu_id as a parameter
    while we're here, let's remove the multiplier since it is
    not used.
dev/alpha_console.cc:
    don't take the number of CPUs as a parameter.  Calculate it from
    the system based on the number of CPUs that have been registered.
    move init() code to startup() to ensure that all CPUs are registerd.
dev/alpha_console.hh:
python/m5/objects/AlphaConsole.py:
    don't take the number of CPUs as a parameter.
    move init() code to startup() to ensure that all CPUs are registerd.
python/m5/objects/BaseCPU.py:
    take the cpu_id as a parameter.  Default it to -1 which means
    that it will be generated.
sim/system.cc:
    allow the registerExecContext functioin to take a desired
    cpu_id as a parameter.  Check to ensure that the id isn't
    already used.  Accept -1 as a request to have an id assigned.
sim/system.hh:
    keep track of the number of registered exec contexts.
    provide a function for accessing the number of exec contexts
    that checks to ensure that they are all registered correctly.

--HG--
extra : convert_revision : 8e12f96ff8a49fa16cdbbdb4c05c651376c35788
2005-06-29 01:20:41 -04:00
Nathan Binkert
6ff9439afe Cleanup copyright stuff. Add our copyright files that
are ours

arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
sim/process.cc:
sim/process.hh:
    remove $Id$ string
cpu/ozone/cpu.cc:
cpu/ozone/cpu_impl.hh:
cpu/ozone/ea_list.cc:
cpu/ozone/ea_list.hh:
kern/linux/sched.hh:
kern/linux/thread_info.hh:
    Add M5 Copyright
cpu/trace/opt_cpu.cc:
dev/rtcreg.h:
    nit
kern/linux/aligned.hh:
kern/linux/hwrpb.hh:
util/oprofile-top.py:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
    Cleanup copyright

--HG--
extra : convert_revision : 4274e9121ef7543e0b3999b31e935edb19c54d46
2005-06-05 11:02:38 -04:00
Steve Reinhardt
5f0f42f166 Fix minor doxygen issues.
Doxyfile:
    Turn on EXTRACT_ALL so we get full class hierarchy info.
base/range.hh:
cpu/o3/fetch.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
dev/ide_disk.cc:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
    Fix doxygen issues.

--HG--
extra : convert_revision : 9e0e8d3510b35db201459b8a3211c5e6ad5f0bb4
2005-06-05 08:08:29 -04:00
Steve Reinhardt
ad8b9636f8 Many files:
Update copyright dates and author list

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
    Update copyright dates and author list

--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
2005-06-05 05:16:00 -04:00
Kevin Lim
77b9829f13 Update #defines for the O3CPU. Also include the copyright.
base/timebuf.hh:
    Updated copyright.
cpu/o3/2bit_local_pred.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/btb.hh:
cpu/o3/comm.hh:
cpu/o3/commit.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/cpu_policy.hh:
cpu/o3/decode.hh:
cpu/o3/fetch.hh:
cpu/o3/free_list.hh:
cpu/o3/iew.hh:
cpu/o3/inst_queue.hh:
cpu/o3/mem_dep_unit.hh:
cpu/o3/ras.hh:
cpu/o3/regfile.hh:
cpu/o3/rename.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.cc:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.hh:
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Updated #define to have correct path.
docs/footer.html:
    Remove e-mail addr.

--HG--
extra : convert_revision : 68d7af52674621dc3b6d6ac0d564790ffd595fe3
2005-06-05 03:25:26 -04:00
Nathan Binkert
11f0c01207 Merge zizzer.eecs.umich.edu:/bk/m5
into crampon.my.domain:/z/binkertn/research/m5/head

--HG--
extra : convert_revision : d46f23e63e4a8c6325bcdeaf6cdd76b9e6208707
2005-06-05 02:59:44 -04:00
Steve Reinhardt
550003e1b7 Change SamplingCPU to Sampler.
--HG--
extra : convert_revision : ddba327a572804954adcebfff1182b97d474c020
2005-06-05 02:59:43 -04:00
Nathan Binkert
e71ee12eac move eio stuff to encumbered
--HG--
extra : convert_revision : 9061382dba285c84931f8825e7159db0e9899944
2005-06-05 02:26:19 -04:00
Nathan Binkert
13c005a8af shuffle files around for new directory structure
--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-04 20:50:10 -04:00
Nathan Binkert
6b6445eeb9 more portable
arch/alpha/alpha_tru64_process.cc:
    Sort #includes
    Make code more portable. g++ doesn't seem to always like
    struct ::stat (and others). So, we typedef stat outside of
    the namespace as something else and use the typedef
base/hostinfo.cc:
    use snprintf to quell warning
base/inifile.cc:
    use strncpy to quell warning
base/stats/events.cc:
    don't use strcpy
cpu/beta_cpu/btb.cc:
    use FloorLog2 instead of log2
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/inst_queue.hh:
cpu/beta_cpu/sat_counter.hh:
    use sim/host.hh instead of stdint.h

--HG--
extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
2005-06-04 14:16:04 -04:00
Steve Reinhardt
62fa781fee Rename sim/universe.{cc,hh} to root.{cc,hh} (since the
object defined there was renamed Root long ago).

SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
base/misc.cc:
base/pollevent.cc:
base/pollevent.hh:
base/stats/events.cc:
base/trace.hh:
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/full_cpu.cc:
cpu/beta_cpu/inst_queue_impl.hh:
cpu/pc_event.cc:
cpu/static_inst.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ide_disk.cc:
dev/pcidev.cc:
sim/builder.cc:
sim/eventq.cc:
sim/main.cc:
sim/root.cc:
sim/stat_control.cc:
    Rename sim/universe.{cc,hh} to root.{cc,hh}.

--HG--
rename : sim/universe.cc => sim/root.cc
extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-06-01 21:59:27 -04:00
Steve Reinhardt
8031cd93b5 Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01 21:44:00 -04:00
Kevin Lim
2a85931c5e Added copyright.
--HG--
extra : convert_revision : f6d53ac5130ea9f77f39f7c1aa35eeb1d5107599
2005-05-26 23:30:12 -04:00
Steve Reinhardt
432e779fb0 Little debugging things.
cpu/base_cpu.cc:
    Get rid of leftover debugging code.

--HG--
extra : convert_revision : b33b2279499456b12a6242a9472ea5be724b37be
2005-05-24 16:37:30 -04:00
Steve Reinhardt
9725c13a0b Minor changes to get new cpu to compile with FULL_SYSTEM.
cpu/beta_cpu/full_cpu.hh:
    Make cpu_id protected rather than private so derived
    classes can access it.
cpu/beta_cpu/regfile.hh:
    Get rid of troublesome debugging statement.

--HG--
extra : convert_revision : ae1f841697ea8d736579b8278eaf8fc6bdf3b6c5
2005-05-20 17:13:37 -04:00
Kevin Lim
c2fcac7c0d Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes.
cpu/base_dyn_inst.cc:
    Remove unused commented out code.
cpu/base_dyn_inst.hh:
    Fix up comments.
cpu/beta_cpu/2bit_local_pred.cc:
    Reorder code to match header file.
cpu/beta_cpu/2bit_local_pred.hh:
    Update comments.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Remove useless comments.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
cpu/beta_cpu/alpha_full_cpu_impl.hh:
cpu/beta_cpu/comm.hh:
cpu/beta_cpu/iew_impl.hh:
    Remove unused commented code.
cpu/beta_cpu/alpha_full_cpu.hh:
    Remove obsolete comment.
cpu/beta_cpu/alpha_impl.hh:
cpu/beta_cpu/full_cpu.hh:
    Alphabetize includes.
cpu/beta_cpu/bpred_unit.hh:
    Remove unused global history code.
cpu/beta_cpu/btb.hh:
cpu/beta_cpu/free_list.hh:
    Use full path in #defines.
cpu/beta_cpu/commit.hh:
cpu/beta_cpu/decode.hh:
    Reorder functions.
cpu/beta_cpu/commit_impl.hh:
    Remove obsolete commented code.
cpu/beta_cpu/fetch.hh:
    Remove obsolete comments.
cpu/beta_cpu/fetch_impl.hh:
cpu/beta_cpu/rename_impl.hh:
    Remove commented code.
cpu/beta_cpu/full_cpu.cc:
    Remove useless defines.
cpu/beta_cpu/inst_queue.hh:
    Use full path for #defines.
cpu/beta_cpu/inst_queue_impl.hh:
    Reorder functions to match header file.
cpu/beta_cpu/mem_dep_unit.hh:
    Use full path name for #defines.
cpu/beta_cpu/ras.hh:
    Use full path names for #defines.  Remove mod operation.
cpu/beta_cpu/regfile.hh:
    Remove unused commented code, fix up current comments.
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Update programming style.

--HG--
extra : convert_revision : fb9d18a853f58a1108ff827e3c123d5b52a0608a
2005-05-19 01:28:25 -04:00
Kevin Lim
61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00
Kevin Lim
6191d3e444 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-05-02 14:16:33 -04:00
Ron Dreslinski
e07fee31cb Clean up output for pc break events, and remove a unneeded break event.
cpu/pc_event.cc:
    Add a newline to the printout to clean up output
kern/linux/linux_system.cc:
    Remove the die_if_kernel pc break event, it is being called when not the kernel and leads to unneeded printouts

--HG--
extra : convert_revision : c359532db31c961074894cc6c44c8452592caca8
2005-04-28 17:24:04 -04:00
Kevin Lim
26d6d97f5d Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 0baadd8d68bfa6f8e96307eb2d4426b0d9e0b8b4
2005-04-14 16:06:34 -04:00
Nathan Binkert
5eab6c4b41 Make the notion of a global event tick independent of the actual
CPU cycle ticks.  This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency.  For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.

arch/alpha/ev5.cc:
    The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
    frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
    frequency isn't the cpu parameter anymore, cycleTime is.
    create several public functions for getting the cpu frequency
    and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
    Now that ticks aren't cpu cycles, fixup code to advance
    by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
    Provide a function to get the number of ticks for a given
    number of cycles.
dev/alpha_console.cc:
    Update for changes in the way that frequencies and latencies are
    accessed.  Move some stuff to init()
dev/alpha_console.hh:
    Need a pointer to the system and the cpu to get the frequency
    so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
    outline the constructor and destructor
dev/platform.hh:
    outline the constructor and destructor.
    don't keep track of the interrupt frequency.  Only provide the
    accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
    outline the constructor and destructor
    Don't set the interrupt frequency here.  Get it from the actual device
    that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make the interrupt interval a configuration parameter.  (And convert
    the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
kern/tru64/tru64_system.cc:
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
python/m5/config.py:
    Fix support for cycle_time relative latencies and frequencies.
    Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
    All CPUs now have a cycle_time.  The default is the global frequency,
    but it is now possible to set the global frequency to some large value
    (like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
    Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
    We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
    Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
    this frequency isn't needed.  We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
    The clock generator should hold the frequency
sim/eventq.hh:
    Need to remove this assertion because the writeback event
    queue is different from the CPU's event queue which can cause
    this assertion to fail.
sim/process.cc:
    Fix comment.
sim/system.hh:
    Struct member to hold the boot CPU's frequency.
sim/universe.cc:
    remove unneeded variable.

--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-11 15:32:06 -04:00
Kevin Lim
cfa4221e19 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : cbf8da2fe5c4155d9ed8318597d543ff105449d3
2005-03-18 15:32:53 -05:00
Ali Saidi
caf16a99cc during a cache miss in the simple cpu we were finalizing the trace
data too early (before the cache miss completed) and therefore
writing freeded memory after the cache miss completed.

Also removed some spurious setAddr() and setData() calls.

--HG--
extra : convert_revision : 3da82540c69c4c417aba3ed155e167d09431a1b2
2005-03-15 17:31:18 -05:00
Kevin Lim
3833533a64 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 1391d03656a1d75809217c5b2e2aecca6f8a04ba
2005-03-15 15:13:24 -05:00
Nathan Binkert
0acb2d0108 small cleanup to sampling cpu code.
cpu/base_cpu.cc:
    By default we should panic if the system doesn't explicitly support
    switchover.

--HG--
extra : convert_revision : 4da2ec316d609cfb351fc5ceaa6d8fe36be14d4e
2005-03-15 12:17:22 -05:00
Kevin Lim
c12a665c31 Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : a58535776cf5a3d17f8d9f65144cdf8db54289aa
2005-03-10 15:53:27 -05:00
Ron Dreslinski
e51850f1d2 Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : a5ee8e5187503203058da35ca44918f1ff7ae1eb
2005-03-10 11:56:07 -05:00
Ali Saidi
232134a816 Changed all syscalls to use syscall return object.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
cpu/exec_context.hh:
sim/process.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Changed all syscalls to use syscall return object
arch/alpha/isa_traits.hh:
    Added syscall return object that packages return value and return
    status into an object.
sim/process.cc:
    renamed variable name to nm so base class function name() can be called

--HG--
extra : convert_revision : 6609c5ffecc9e3519d7a0cd160879fd21d54abfc
2005-03-09 15:52:10 -05:00
Kevin Lim
2162b433ad Hand-merge static_inst.hh. These execute functions are within an external file in the new CPU case.
cpu/static_inst.hh:
    Hand-merge.  These execute functions are within an external file in the new CPU case.

--HG--
extra : convert_revision : a34112f471fa31bdd5bb53552ddd704b9571c110
2005-03-08 21:03:20 -05:00
Ron Dreslinski
b290ecf1bb Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 2b73bffea88cb0e3bb5dff232a15afea8498f4e3
2005-03-07 10:58:15 -05:00
Steve Reinhardt
58c29640b7 Add a new operation class for IPR accesses, and have IPR-accessing
instructions use it (instead of IntALU, as before).  Default config
has a single non-pipelined 3-cycle unit.  A bit conservative for the
ev6 (some are 1, some are 3).

arch/alpha/isa_desc:
    Make hw_mfpr and hw_mtpr use IprAccessOp op class.
cpu/full_cpu/op_class.hh:
    Add IprAccess.

--HG--
extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442
2005-03-01 00:39:57 -05:00
Steve Reinhardt
89dc94f3bc Make all StaticInst methods const. StaticInst objects represent a
particular binary machine instruction and should be immutable after
they are constructed.

cpu/simple_cpu/simple_cpu.hh:
    Make StaticInst parameters const.

--HG--
extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba
2005-02-25 21:44:33 -05:00
Kevin Lim
bb41c21d6a Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : ba556bbc93275fcd920a0529383fd480bb7218de
2005-02-25 18:01:19 -05:00
Kevin Lim
5c4714c1a9 Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.
SConscript:
    Include new files.
arch/alpha/isa_desc:
    Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them.
arch/alpha/isa_traits.hh:
    Add enum for total number of data registers.
arch/isa_parser.py:
base/traceflags.py:
    Include new light-weight OoO CPU model.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
    Changes to abstract more away from the base dyn inst class.
cpu/beta_cpu/2bit_local_pred.cc:
cpu/beta_cpu/2bit_local_pred.hh:
cpu/beta_cpu/tournament_pred.cc:
cpu/beta_cpu/tournament_pred.hh:
    Remove redundant SatCounter class.
cpu/beta_cpu/alpha_dyn_inst.cc:
cpu/beta_cpu/alpha_full_cpu.cc:
cpu/beta_cpu/alpha_full_cpu.hh:
cpu/beta_cpu/bpred_unit.cc:
cpu/beta_cpu/inst_queue.cc:
cpu/beta_cpu/mem_dep_unit.cc:
cpu/beta_cpu/ras.cc:
cpu/beta_cpu/rename_map.cc:
cpu/beta_cpu/rename_map.hh:
cpu/beta_cpu/rob.cc:
    Fix for gcc-3.4
cpu/beta_cpu/alpha_dyn_inst.hh:
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Fixes for gcc-3.4.
    Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Make params match the current params inherited from BaseCPU.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Fixes for gcc-3.4
cpu/beta_cpu/full_cpu.cc:
    Use new params pointer in BaseCPU.
    Fix for gcc-3.4.
cpu/beta_cpu/full_cpu.hh:
    Use new params class from BaseCPU.
cpu/beta_cpu/iew_impl.hh:
    Remove unused function.
cpu/simple_cpu/simple_cpu.cc:
    Remove unused global variable.
cpu/static_inst.hh:
    Include OoODynInst for new lightweight OoO CPU

--HG--
extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
2005-02-25 18:00:49 -05:00
Ron Dreslinski
45eb26e67c Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : e7d839327b07393bfcda0b77758b0832eaf1c1c0
2005-02-25 15:12:05 -05:00
Steve Reinhardt
368882a847 Fix timing modeling of faults: functionally the very next instruction after
a faulting instruction is the fault handler, which appears as an independent
instruction to the timing model.  New code will stall fetch and not fetch the
fault handler as long as there's a faulting instruction in the pipeline (i.e.,
the faulting inst has to commit first).

Also fix Ali's bad-address assertion that doesn't apply to full system.

Added some more debugging support in the process.  Hopefully we'll move to the new
cpu model soon and we won't need it anymore.

arch/alpha/alpha_memory.cc:
    Reorganize lookup() so we can trace the result of the lookup as well.
arch/alpha/isa_traits.hh:
    Add NoopMachInst (so we can insert them in the pipeline on ifetch faults).
base/traceflags.py:
    Replace "Dispatch" flag with "Pipeline" (since I added similar
    DPRINTFs in other pipe stages).
cpu/exetrace.cc:
    Change default for printing mis-speculated instructions to true (since
    that's often what we want, and right now you can't change it from the
    command line...).

--HG--
extra : convert_revision : a29a98a373076d62bbbb1d6f40ba51ecae436dbc
2005-02-25 12:41:08 -05:00
Kevin Lim
e8a564b0fd Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5

--HG--
extra : convert_revision : 8a558785c64b7c33e64523d3d887ea6e760c3d2b
2005-02-22 16:03:30 -05:00
Ron Dreslinski
9dd1ab1dba Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : db688679bfd9c670ef44611de71640c3bf564fc0
2005-02-21 16:50:38 -05:00
Nathan Binkert
9b1e2db811 Clean up CPU stuff and make it use params structs
cpu/base_cpu.cc:
cpu/base_cpu.hh:
    Convert the CPU stuff to use a params struct
cpu/memtest/memtest.cc:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
    Don't have any default parameters.
cpu/memtest/memtest.hh:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
cpu/simple_cpu/simple_cpu.cc:
    Convert to use a params struct.
    remove default parameters
cpu/simple_cpu/simple_cpu.hh:
    convert to use a params struct
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
    this isn't really a cpu.  don't derive from BaseCPU
objects/MemTest.mpy:
    we only need one max_loads parameter
sim/main.cc:
    Don't check for the number of CPUs since we may be doing something
    else going on.  If we don't have anything to simulate, the
    simulator will exit anyway.

--HG--
extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
2005-02-19 11:46:41 -05:00
Ron Dreslinski
f825d103da Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 8fb4bbf165b8c65a54db5fea18ec5aa95172a173
2005-02-18 13:10:37 -05:00
Nathan Binkert
dd4220ec10 rename the simple cpu's multiplier parameter. call it width.
it makes more sense and is less confusing.

cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    width is a better name than multiplier

--HG--
extra : convert_revision : ea2fa4faa160f5657aece41df469bbc9f7244b21
2005-02-17 14:02:03 -05:00
Ron Dreslinski
45ef238e3f Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 88afcacc41f5b0fae0ed1ac1821b7ca88c407e85
2005-02-17 12:14:04 -05:00