Commit graph

492 commits

Author SHA1 Message Date
Steve Reinhardt
f064aa3060 sim: revamp unserialization procedure
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject.  The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects.  However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found.  (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead.  This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
2010-08-17 05:17:06 -07:00
Gabe Black
52a90a5998 CPU: Tidy up endianness handling for mmapped "IPR"s. 2010-08-13 06:10:45 -07:00
Steve Reinhardt
d0af5e9df6 More minor gdb-related cleanup.
Found several more stale includes and forward decls.
2010-06-03 19:41:34 -07:00
Gabe Black
c5c559b6ab SPARC: Implement the version of movcc that uses the fp condition codes. 2010-05-14 14:22:51 -07:00
Timothy M. Jones
29e8bcead5 O3PCU: Split loads and stores that cross cache line boundaries.
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.

This modifies the LSQSenderState class to record both packets in a split
load or store.

Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
2010-02-12 19:53:20 +00:00
Gabe Black
3f722b991f Syscalls: Make system calls access arguments like a stack, not an array.
When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
2009-10-30 00:44:55 -07:00
Vince Weaver
9b8e61beb3 Syscalls: Implement sysinfo() syscall. 2009-09-15 22:36:47 -07:00
Vince Weaver
0f569b4d9d SPARC: Make resTemp in udivcc wide enough to hold all the bits we need. 2009-09-15 05:48:20 -07:00
Steve Reinhardt
1c28004654 Clean up some inconsistencies with Request flags. 2009-08-01 22:50:13 -07:00
Gabe Black
ef4e8b04a6 SPARC: Fix a minor compile bug in native trace on gcc > 4.1. 2009-07-25 15:14:00 -07:00
Gabe Black
3e8e813218 CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-19 23:54:56 -07:00
Gabe Black
64fe7af51a SPARC: Set up a lookup table for integer register flattening.
Using a look up table changed the run time of the SPARC_FS solaris boot
regression from:

real    14m45.951s
user    13m57.528s
sys     0m3.452s

to:

real    12m19.777s
user    12m2.685s
sys     0m2.420s
2009-07-10 01:01:47 -07:00
Gabe Black
60d47aa5f9 SPARC: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:50 -07:00
Gabe Black
c9a27d85b9 Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. 2009-07-08 23:02:22 -07:00
Gabe Black
b398b8ff1b Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08 23:02:21 -07:00
Gabe Black
5c37d10624 Registers: Eliminate the ISA defined RegFile class. 2009-07-08 23:02:21 -07:00
Gabe Black
43345bff6c Registers: Move the PCs out of the ISAs and into the CPUs. 2009-07-08 23:02:21 -07:00
Gabe Black
faa6ebebe1 SPARC: Phase out SPARC's intregfile.hh. 2009-07-08 23:02:20 -07:00
Gabe Black
a480ba00b9 Registers: Eliminate the ISA defined integer register file. 2009-07-08 23:02:20 -07:00
Gabe Black
0cb180ea0d Registers: Eliminate the ISA defined floating point register file. 2009-07-08 23:02:20 -07:00
Gabe Black
25884a8773 Registers: Get rid of the float register width parameter. 2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
2009-07-08 23:02:20 -07:00
Gabe Black
240e214236 SPARC: Fix the parenthesis in inUserMode. 2009-07-05 16:07:09 -07:00
Nathan Binkert
8d2e51c7f5 includes: sort includes again 2009-05-17 14:34:52 -07:00
Nathan Binkert
709d859530 includes: use base/types.hh not inttypes.h or stdint.h 2009-05-17 14:34:51 -07:00
Nathan Binkert
eef3a2e142 types: Move stuff for global types into src/base/types.hh
--HG--
rename : src/sim/host.hh => src/base/types.hh
2009-05-17 14:34:50 -07:00
Gabe Black
9d0fa27d09 SPARC: Tighten up the clone system call and SPARCs copyRegs. 2009-04-24 23:11:21 -07:00
Steve Reinhardt
52b6764f31 syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. 2009-04-21 08:17:36 -07:00
Daniel Sanchez
b0e9654f86 Commit m5threads package.
This patch adds limited multithreading support in syscall-emulation
mode, by using the clone system call.  The clone system call works
for Alpha, SPARC and x86, and multithreaded applications run
correctly in Alpha and SPARC.
2009-04-21 08:17:36 -07:00
Gabe Black
ca85981478 SE mode: Make keeping track of the number of syscalls less hacky. 2009-04-19 04:15:32 -07:00
Steve Reinhardt
8882dc1283 Get rid of the Unallocated thread context state.
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
 - InOrderCPU's setThreadRescheduleCondition.
 - ThreadContext::exit().  This function was there to avoid terminating
   simulation when one thread out of a multi-thread workload exits, but we
   need to find a better (non-cpu-centric) way.
2009-04-15 13:13:47 -07:00
Nathan Binkert
e0de2c3443 tlb: More fixing of unified TLB 2009-04-08 22:21:27 -07:00
Gabe Black
7b5a96f06b tlb: Don't separate the TLB classes into an instruction TLB and a data TLB 2009-04-08 22:21:27 -07:00
Steve Reinhardt
307905095c Fix Num_Syscall_Descs check bug in non-x86 ISAs.
(See cset d35d2b28df38 for x86 fix.)
2009-02-28 20:14:22 -05:00
Gabe Black
9a000c5173 Processes: Make getting and setting system call arguments part of a process object. 2009-02-27 09:22:14 -08:00
Gabe Black
437b02884d ISA: Get rid of the get*RegName functions. 2009-02-25 10:22:31 -08:00
Gabe Black
3b01535ec1 SPARC: Get rid of the state keeping track of register frames. 2009-02-25 10:22:25 -08:00
Gabe Black
4633677145 ISA: Set up common trace flags for tracing registers. 2009-02-25 10:22:17 -08:00
Gabe Black
44d5351071 ISA: Get rid of FlattenIntIndex function. 2009-02-25 10:22:09 -08:00
Gabe Black
c1c61d52a0 SPARC: Get rid of flattenIndex in the int register file. 2009-02-25 10:21:59 -08:00
Gabe Black
ce2e50a64c ISA: Use the "Stack" traceflag for DPRINTFs about the initial stack frame. 2009-02-25 10:21:52 -08:00
Gabe Black
9d5b6e377f SPARC: Get rid of the setGlobals function. 2009-02-25 10:21:46 -08:00
Gabe Black
f41ce6b5e9 SPARC: Get rid of the setCWP function. 2009-02-25 10:21:40 -08:00
Gabe Black
88ee7d4c32 SPARC: Add a traceflag for register windows. 2009-02-25 10:21:33 -08:00
Gabe Black
6ed47e9464 CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. 2009-02-25 10:16:15 -08:00
Gabe Black
15940d06b5 SPARC: Adjust a few instructions to not write registers in initiateAcc. 2009-02-25 10:16:04 -08:00
Gabe Black
5605079b1f ISA: Replace the translate functions in the TLBs with translateAtomic. 2009-02-25 10:15:44 -08:00
Lisa Hsu
5d029ff11e sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though. 2009-02-16 17:47:39 -05:00
Ali Saidi
e7293dd24e Errors: Use the correct panic/warn/fatal/info message in some places. 2009-01-30 20:04:17 -05:00
Gabe Black
d9794784ba CPU: Add a setCPU function to the interrupt objects. 2009-01-25 20:29:03 -08:00