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gem5/src/arch/sparc
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Steve Reinhardt f064aa3060 sim: revamp unserialization procedure 
Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject.  The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects.  However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found.  (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead.  This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
2010-08-17 05:17:06 -07:00
..
isa SPARC: Implement the version of movcc that uses the fp condition codes. 2010-05-14 14:22:51 -07:00
linux Syscalls: Make system calls access arguments like a stack, not an array. 2009-10-30 00:44:55 -07:00
solaris Syscalls: Make system calls access arguments like a stack, not an array. 2009-10-30 00:44:55 -07:00
asi.cc Panic if any CMT registers are accessed 2007-03-08 21:49:13 -05:00
asi.hh Panic if any CMT registers are accessed 2007-03-08 21:49:13 -05:00
faults.cc gcc: Add extra parens to quell warnings. 2008-09-27 21:03:49 -07:00
faults.hh Address translation: Make the page table more flexible. 2007-08-26 20:33:57 -07:00
handlers.hh SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work. 2007-08-13 16:02:47 -07:00
interrupts.cc Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
interrupts.hh SPARC: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:50 -07:00
isa.cc SPARC: Set up a lookup table for integer register flattening. 2009-07-10 01:01:47 -07:00
isa.hh SPARC: Set up a lookup table for integer register flattening. 2009-07-10 01:01:47 -07:00
isa_traits.hh O3PCU: Split loads and stores that cross cache line boundaries. 2010-02-12 19:53:20 +00:00
kernel_stats.hh Put kernel_stats back into arch. 2006-11-07 22:34:34 -05:00
locked_mem.hh Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) 2006-10-08 10:53:24 -07:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
miscregs.hh Registers: Add a registers.hh file as an ISA switched header. 2009-07-08 23:02:21 -07:00
mmaped_ipr.hh reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes) 2006-12-04 19:39:57 -05:00
nativetrace.cc SPARC: Fix a minor compile bug in native trace on gcc > 4.1. 2009-07-25 15:14:00 -07:00
nativetrace.hh CPU: Separate out native trace into ISA (in)dependent code and SimObjects. 2009-07-19 23:54:56 -07:00
pagetable.cc Make SPARC checkpointing work 2007-01-30 18:25:39 -05:00
pagetable.hh sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though. 2009-02-16 17:47:39 -05:00
predecoder.hh SPARC: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:50 -07:00
process.cc sim: revamp unserialization procedure 2010-08-17 05:17:06 -07:00
process.hh sim: revamp unserialization procedure 2010-08-17 05:17:06 -07:00
registers.hh Registers: Add a registers.hh file as an ISA switched header. 2009-07-08 23:02:21 -07:00
remote_gdb.cc arch: TheISA shouldn't really ever be used in the arch directory. 2008-09-27 21:03:46 -07:00
remote_gdb.hh SPARC,Remote GDB: Fix an accounting bug in the remote gdb stuff. 2007-10-02 18:24:24 -07:00
SConscript CPU: Separate out native trace into ISA (in)dependent code and SimObjects. 2009-07-19 23:54:56 -07:00
SConsopts Rework the way SCons recurses into subdirectories, making it 2007-03-10 23:00:54 -08:00
sparc_traits.hh Registers: Eliminate the ISA defined floating point register file. 2009-07-08 23:02:20 -07:00
SparcInterrupts.py Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 2008-10-12 09:09:56 -07:00
SparcNativeTrace.py CPU: Separate out native trace into ISA (in)dependent code and SimObjects. 2009-07-19 23:54:56 -07:00
SparcSystem.py Move SimObject python files alongside the C++ and fix 2007-05-27 19:21:17 -07:00
SparcTLB.py tlb: Don't separate the TLB classes into an instruction TLB and a data TLB 2009-04-08 22:21:27 -07:00
stacktrace.cc arch: TheISA shouldn't really ever be used in the arch directory. 2008-09-27 21:03:46 -07:00
stacktrace.hh arch: TheISA shouldn't really ever be used in the arch directory. 2008-09-27 21:03:46 -07:00
system.cc More minor gdb-related cleanup. 2010-06-03 19:41:34 -07:00
system.hh Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
tlb.cc CPU: Tidy up endianness handling for mmapped "IPR"s. 2010-08-13 06:10:45 -07:00
tlb.hh tlb: More fixing of unified TLB 2009-04-08 22:21:27 -07:00
tlb_map.hh When nesting if statements, use braces to avoid ambiguous else clauses. 2008-09-26 08:18:57 -07:00
types.hh Registers: Add a registers.hh file as an ISA switched header. 2009-07-08 23:02:21 -07:00
ua2005.cc SPARC: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:50 -07:00
utility.cc SPARC: Set up a lookup table for integer register flattening. 2009-07-10 01:01:47 -07:00
utility.hh SPARC: Fold the MiscRegFile all the way into the ISA object. 2009-07-09 20:28:50 -07:00
vtophys.cc tlb: Don't separate the TLB classes into an instruction TLB and a data TLB 2009-04-08 22:21:27 -07:00
vtophys.hh implement vtophys and 32bit gdb support 2007-02-18 19:57:46 -05:00