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CPU: Tidy up endianness handling for mmapped "IPR"s.

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This commit is contained in:
Gabe Black 2010-08-13 06:10:45 -07:00
parent 2e9e75447a
commit 52a90a5998
2 changed files with 3 additions and 5 deletions
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2
src/arch/sparc/tlb.cc
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@ -1049,7 +1049,7 @@ doMmuReadError:
Tick
TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
{
uint64_t data = gtoh(pkt->get<uint64_t>());
uint64_t data = pkt->get<uint64_t>();
Addr va = pkt->getAddr();
ASI asi = (ASI)pkt->req->getAsi();

6
src/cpu/simple/atomic.cc
View file

@ -450,6 +450,8 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
traceData->setData(data);
}
data = htog(data);
//The block size of our peer.
unsigned blockSize = dcachePort.peerBlockSize();
//The size of the data we're trying to read.
@ -496,10 +498,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
//XXX This needs to be outside of the loop in order to
//work properly for cache line boundary crossing
//accesses in transendian simulations.
data = htog(data);
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
dcache_latency += physmemPort.sendAtomic(&pkt);
else