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isa
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SPARC: Make resTemp in udivcc wide enough to hold all the bits we need.
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2009-09-15 05:48:20 -07:00 |
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linux
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Registers: Add a registers.hh file as an ISA switched header.
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2009-07-08 23:02:21 -07:00 |
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solaris
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Registers: Add a registers.hh file as an ISA switched header.
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2009-07-08 23:02:21 -07:00 |
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asi.cc
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Panic if any CMT registers are accessed
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2007-03-08 21:49:13 -05:00 |
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asi.hh
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Panic if any CMT registers are accessed
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2007-03-08 21:49:13 -05:00 |
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faults.cc
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gcc: Add extra parens to quell warnings.
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2008-09-27 21:03:49 -07:00 |
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faults.hh
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Address translation: Make the page table more flexible.
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2007-08-26 20:33:57 -07:00 |
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handlers.hh
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SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work.
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2007-08-13 16:02:47 -07:00 |
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interrupts.cc
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Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
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2008-10-12 09:09:56 -07:00 |
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interrupts.hh
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SPARC: Fold the MiscRegFile all the way into the ISA object.
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2009-07-09 20:28:50 -07:00 |
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isa.cc
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SPARC: Set up a lookup table for integer register flattening.
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2009-07-10 01:01:47 -07:00 |
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isa.hh
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SPARC: Set up a lookup table for integer register flattening.
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2009-07-10 01:01:47 -07:00 |
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isa_traits.hh
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Registers: Add a registers.hh file as an ISA switched header.
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2009-07-08 23:02:21 -07:00 |
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kernel_stats.hh
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Put kernel_stats back into arch.
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2006-11-07 22:34:34 -05:00 |
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locked_mem.hh
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Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
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2006-10-08 10:53:24 -07:00 |
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microcode_rom.hh
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CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
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2008-10-12 15:59:21 -07:00 |
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miscregs.hh
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Registers: Add a registers.hh file as an ISA switched header.
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2009-07-08 23:02:21 -07:00 |
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mmaped_ipr.hh
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reogranize code to split off FS only misc regs with effect into their own file (reducing the number of if FULL_SYSTEM defines and includes)
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2006-12-04 19:39:57 -05:00 |
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nativetrace.cc
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SPARC: Fix a minor compile bug in native trace on gcc > 4.1.
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2009-07-25 15:14:00 -07:00 |
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nativetrace.hh
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CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
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2009-07-19 23:54:56 -07:00 |
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pagetable.cc
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Make SPARC checkpointing work
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2007-01-30 18:25:39 -05:00 |
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pagetable.hh
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sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.
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2009-02-16 17:47:39 -05:00 |
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predecoder.hh
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SPARC: Fold the MiscRegFile all the way into the ISA object.
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2009-07-09 20:28:50 -07:00 |
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process.cc
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SPARC: Set up a lookup table for integer register flattening.
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2009-07-10 01:01:47 -07:00 |
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process.hh
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Processes: Make getting and setting system call arguments part of a process object.
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2009-02-27 09:22:14 -08:00 |
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registers.hh
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Registers: Add a registers.hh file as an ISA switched header.
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2009-07-08 23:02:21 -07:00 |
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remote_gdb.cc
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arch: TheISA shouldn't really ever be used in the arch directory.
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2008-09-27 21:03:46 -07:00 |
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remote_gdb.hh
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SPARC,Remote GDB: Fix an accounting bug in the remote gdb stuff.
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2007-10-02 18:24:24 -07:00 |
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SConscript
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CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
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2009-07-19 23:54:56 -07:00 |
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SConsopts
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Rework the way SCons recurses into subdirectories, making it
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2007-03-10 23:00:54 -08:00 |
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sparc_traits.hh
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Registers: Eliminate the ISA defined floating point register file.
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2009-07-08 23:02:20 -07:00 |
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SparcInterrupts.py
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Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
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2008-10-12 09:09:56 -07:00 |
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SparcNativeTrace.py
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CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
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2009-07-19 23:54:56 -07:00 |
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SparcSystem.py
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Move SimObject python files alongside the C++ and fix
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2007-05-27 19:21:17 -07:00 |
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SparcTLB.py
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tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
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2009-04-08 22:21:27 -07:00 |
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stacktrace.cc
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arch: TheISA shouldn't really ever be used in the arch directory.
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2008-09-27 21:03:46 -07:00 |
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stacktrace.hh
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arch: TheISA shouldn't really ever be used in the arch directory.
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2008-09-27 21:03:46 -07:00 |
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system.cc
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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system.hh
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Major changes to how SimObjects are created and initialized. Almost all
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2007-07-23 21:51:38 -07:00 |
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tlb.cc
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Clean up some inconsistencies with Request flags.
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2009-08-01 22:50:13 -07:00 |
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tlb.hh
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tlb: More fixing of unified TLB
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2009-04-08 22:21:27 -07:00 |
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tlb_map.hh
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When nesting if statements, use braces to avoid ambiguous else clauses.
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2008-09-26 08:18:57 -07:00 |
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types.hh
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Registers: Add a registers.hh file as an ISA switched header.
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2009-07-08 23:02:21 -07:00 |
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ua2005.cc
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SPARC: Fold the MiscRegFile all the way into the ISA object.
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2009-07-09 20:28:50 -07:00 |
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utility.cc
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SPARC: Set up a lookup table for integer register flattening.
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2009-07-10 01:01:47 -07:00 |
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utility.hh
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SPARC: Fold the MiscRegFile all the way into the ISA object.
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2009-07-09 20:28:50 -07:00 |
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vtophys.cc
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tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
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2009-04-08 22:21:27 -07:00 |
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vtophys.hh
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implement vtophys and 32bit gdb support
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2007-02-18 19:57:46 -05:00 |
