Commit graph

3125 commits

Author SHA1 Message Date
Kevin Lim
cada047319 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 1010a4ee8e1abec0e8290637feee523ca9ef9a9b
2006-10-02 18:12:21 -04:00
Kevin Lim
c78b6634a2 Be sure to set progress interval.
--HG--
extra : convert_revision : 793ca7d6af1deedf6b1fb4676288b11114f583a6
2006-10-02 18:10:10 -04:00
Kevin Lim
f2acc3a4a3 Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 9bfd96dfbd1d58d56ceaf0e266807c31cb578c34
2006-10-02 12:06:30 -04:00
Kevin Lim
e08aa72b3d Add in ability to start a trace at a specific cycle.
--HG--
extra : convert_revision : 54098f3974d2a05d60e57113f7ceb46cb7a26672
2006-10-02 12:04:24 -04:00
Kevin Lim
568fa11084 Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh:
    This got changed to the wrong version by accident.
src/cpu/base.cc:
    Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
    Fix up the CPU Progress Event to not print itself if it's set to 0.  Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
    Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
    Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
    Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
    Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
    Switch out updates from the version of m5 I have.  Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
    Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
    Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
    Use proper method to get flags.  Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
    Support profiling.
src/cpu/ozone/cpu.hh:
    Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
    Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
    Get flags correctly.
src/cpu/ozone/thread_state.hh:
    Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
    Allow for loading of symbol file.  Be sure to use ThreadContext and not ExecContext.

--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
2006-10-02 11:58:09 -04:00
Steve Reinhardt
85436fd413 Move Python setup into Configure section so we can test whether the
setup is correct and provide meeaningful error messages when it's not.
Also fix for building on Cygwin where python lib is in /bin and not /lib.

--HG--
extra : convert_revision : 7a29ba17463de60c72b3d8b04e4c4f81fc64bf61
2006-10-01 01:42:18 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-09-30 23:43:23 -04:00
Kevin Lim
30b719fd76 Updates to Ozone CPU.
cpu/ozone/cpu_impl.hh:
    Be sure to update rename tables.
cpu/ozone/front_end_impl.hh:
    Handle serialize instructions slightly differently.  This allows front end to continue even if back end hasn't processed it yet.
cpu/ozone/lw_back_end_impl.hh:
    Handle stores with faults properly.
cpu/ozone/lw_lsq.hh:
    Handle committed stores properly.
cpu/ozone/lw_lsq_impl.hh:
    Handle uncacheable loads properly.

--HG--
extra : convert_revision : 093edc2eee890139a9962c97c938575e6d313f09
2006-09-28 00:14:15 -04:00
Kevin Lim
51f19f2e28 Minor changes plus updates to O3.
cpu/base.cc:
    Have output message regardless of build.
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Be sure to include all parameters.
cpu/o3/cpu.cc:
    IEW also needs to switch out.
cpu/o3/iew_impl.hh:
    Handle stores with faults properly.
cpu/o3/inst_queue_impl.hh:
    Switch out properly, handle squashing properly.
cpu/o3/lsq_unit_impl.hh:
    Minor fixes.
cpu/o3/mem_dep_unit_impl.hh:
    Make sure mem dep unit is switched out properly.
cpu/o3/rename_impl.hh:
    Switch out fix.

--HG--
extra : convert_revision : b94deb83f724225c01166c84a1b3fdd3543cbe9a
2006-09-28 00:09:27 -04:00
Steve Reinhardt
51425382ca Add CoherenceProtocol object to objects list.
--HG--
extra : convert_revision : 46c14f37906c44100eaf4e7b66b882ff42fed014
2006-09-18 17:12:46 -07:00
Ali Saidi
17b0e9714d add boiler plate intel nic code
src/SConscript:
    add intel nic to sconscript
src/dev/pcidev.cc:
    fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
    add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
    Move config_latency into pci where it belogs

--HG--
extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
2006-09-18 20:12:45 -04:00
Gabe Black
b7d0395126 Adding what was tracedump but is now statetrace to the tree. Let me know if statetrace is also already taken.
util/statetrace/Makefile:
    Makefile to build statetrace. Targets are:

    statetrace: alias to build using the "native" compiler
    statetrace-native: use the native compiler
    statetrace-sparc: use the sparc cross compiler

    I'll make this a little more fancy and capable later.
util/statetrace/arch/tracechild_i386.cc:
    Implementation of i386 support
util/statetrace/arch/tracechild_i386.hh:
    Declaration of i386 support
util/statetrace/arch/tracechild_sparc.cc:
    implementation of SPARC support
util/statetrace/arch/tracechild_sparc.hh:
    declaration of SPARC support
util/statetrace/printer.cc:
    Implementation of the "Printer" objects which parse and output the state of the process after each instruction. There are currently two types of printers, nested ones and register ones. These are called NestingPrinter and RegPrinter respectively.
util/statetrace/printer.hh:
    Declaration of "Printer" objects
util/statetrace/refcnt.hh:
    This is copied from m5. I should use the one already in the tree, but I'll do that later.
util/statetrace/regstate.hh:
    Interface for accessing registers.
util/statetrace/statetrace.cc:
    Main file with argument parsing and the "main" function which contains the tracing loop.
util/statetrace/tracechild.cc:
    Implementation of the base tracechild class.
util/statetrace/tracechild.hh:
    Declaration of the base tracechild class.
util/statetrace/tracechild_arch.cc:
    This file hooks in support for the appropriate architecture. Just the implementation is brought in, since the main program should ideally not have to know anything at all about an architecture other than it's interface.
util/statetrace/x86.format:
    An example output template for x86. A few example SPARC templates will be added later.

--HG--
extra : convert_revision : 7c8bf8230907aba42ed1e707b9ca2d6da0d4e6d4
2006-09-17 03:46:30 -04:00
Gabe Black
30b87e90f8 Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters.
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
    Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
    Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.

--HG--
extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
2006-09-17 03:00:55 -04:00
Gabe Black
e4fcef5851 Changes to correct stat behavior
--HG--
extra : convert_revision : 43e5788105738aebd79acb05301bb7da68bfe129
2006-09-15 21:43:12 -04:00
Gabe Black
8abab05c83 Merge zizzer.eecs.umich.edu:/bk/newmem
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 91aacb435c223e8c37f6ba0a458b0dee55edcaf2
2006-09-15 00:59:39 -04:00
Ali Saidi
44c6f953b0 Merge zizzer:/bk/newmem
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 14ac24236ff65b7e489c1ce4b4e9a295966013b8
2006-09-11 17:57:30 -04:00
Ali Saidi
46502851ab add annotation code to m5
configs/common/Benchmarks.py:
    add annotate test app
src/SConscript:
    add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
    add annotate instructions
src/base/traceflags.py:
    Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
    add anotate ops

--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
2006-09-11 17:57:20 -04:00
Steve Reinhardt
9e6d12b095 Added cscope-find.py utility to generate file list for cscope.
--HG--
extra : convert_revision : 80f2db90f1c2406039d0447b84aa0442b7b974f8
2006-09-08 19:22:25 -04:00
Steve Reinhardt
a7e8a78958 Add support for assigning lists of ports or proxies to VectorPorts.
Includes support for printing readable VectorPort and Proxy names
(via __str__).

--HG--
extra : convert_revision : c48534a498b3036fe6ac45ff1606656546c79afb
2006-09-08 19:10:11 -04:00
Steve Reinhardt
886c7f7458 Update port numbers from new unproxy ordering.
--HG--
extra : convert_revision : 514d2c53bd6afa6bea43c37c1242b6775e86c556
2006-09-07 02:07:06 -04:00
Steve Reinhardt
c15e6d8e0a Try to make unproxy order more deterministic.
--HG--
extra : convert_revision : 0bc543014dced6dfed4122d4c1b8f22e6c8d7a13
2006-09-06 22:37:35 -07:00
Steve Reinhardt
54698f6be8 Delete some output files that never should have been
committed.

--HG--
extra : convert_revision : 29780a4cc82dc397681a2b4a61eaa658e6eed83e
2006-09-06 15:36:50 -07:00
Steve Reinhardt
545cbec5f7 Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().

src/python/m5/multidict.py:
    Make get() return None by default, to match semantics
    of built-in dictionary objects.

--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
2006-09-05 22:04:34 -07:00
Steve Reinhardt
6c7a490c2b Update reference config.ini files to include port mappings.
--HG--
extra : convert_revision : f9e91a60fa09b707d2a26be57f265b7ab1c07263
2006-09-05 16:24:47 -04:00
Steve Reinhardt
89f0bc9e4c Print ports in config.ini as well.
--HG--
extra : convert_revision : 703d3a57250613315735709de8f40a9956cee6e2
2006-09-05 12:22:47 -07:00
Steve Reinhardt
c39aea440c More Python hacking to deal with config.py split
and resulting recursive import trickiness.

--HG--
extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
2006-09-04 17:14:07 -07:00
Steve Reinhardt
1233dbb998 Split config.py into multiple files.
Some tweaking to deal with mutually recursive imports.

--HG--
rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
2006-09-04 10:52:26 -07:00
Steve Reinhardt
a658d25d42 config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.

src/python/m5/config.py:
    Import of changes for auto-generation of C++ param structs
    from my old m5 working directory.
    This code is *broken* because pieces need to be shuffled around
    to satisfy name dependencies, but that really messes up the
    diff, so I want to make an intermediate commit here.

--HG--
extra : convert_revision : cb25ee1f4f77d1902511ee9aa766403733dd8841
2006-09-04 10:40:33 -07:00
Gabe Black
b11018ca12 Made system calls use the uid, etc parameters from the live process.
--HG--
extra : convert_revision : 2aadb87b4602324423aadb903010f5b49fcef41b
2006-09-03 02:12:11 -04:00
Gabe Black
c32ef326d2 Fix up the parameters to getInstRecord
--HG--
extra : convert_revision : 0fac43035a2510d3a3f596d3d8f57193045570f6
2006-09-03 02:10:05 -04:00
Gabe Black
936d8c3e65 Make the ASI constants available to the decoder.
--HG--
extra : convert_revision : 65f2e02ce8f5e4f0c8727ebf16c927c7a6a4fe7f
2006-09-03 02:09:25 -04:00
Gabe Black
16f9b901be Make the auxiliary vectors use the uid, euid, gid and egid parameters from the live process
--HG--
extra : convert_revision : 945b5883a15a6df35709edea2731f54a2448e418
2006-09-03 02:08:24 -04:00
Gabe Black
387bbe40d1 Fixing up parameters of getInstRecord
--HG--
extra : convert_revision : 4ce06ac4f7d135cc04b39cf0e957a2539c7e946d
2006-09-03 02:05:44 -04:00
Gabe Black
96dabdc9b0 Added uid, euid, gid, egid, pid and ppid parameters to a live process.
--HG--
extra : convert_revision : 2101be8000bcdaf683730cfc079b4b78e34365d0
2006-09-03 02:04:25 -04:00
Gabe Black
14cc9baba5 A quick fix to isolate the tracing code to SPARC
--HG--
extra : convert_revision : 90c77f4d01101cad55f60d528b2a8be92d2f9aba
2006-09-03 02:02:56 -04:00
Steve Reinhardt
f6f3ce1311 regress:
Clean up help output.

util/regress:
    Clean up help output.

--HG--
extra : convert_revision : 8375d58a9d72e1871a15690991dc8fc60d47a2b3
2006-09-02 08:20:54 -07:00
Steve Reinhardt
abe18be544 Merge zizzer.eecs.umich.edu:/bk/newmem
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
2006-09-01 17:12:43 -07:00
Steve Reinhardt
d8501ec17c Get rid of extra stuff in util/regress only needed by cron job,
to make it more usable by regular folks.

util/regress:
    Get rid of extra stuff only needed by cron job,
    to make it more usable by regular folks.

--HG--
extra : convert_revision : e113c05af5eec846db526d734cce8ff66aa95d72
2006-09-01 20:11:50 -04:00
Steve Reinhardt
2c9dc949ce Add o3-timing configuration for ALPHA_SE "Hello world" tests.
build_opts/ALPHA_SE:
    Add O3CPU to default CPU model list.
tests/SConscript:
    Add o3-timing configuration.

--HG--
extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 17:59:36 -04:00
Steve Reinhardt
e9ab841497 diff-out:
Don't consider it a success if no stats at all were found.

tests/diff-out:
    Don't consider it a success if no stats at all were found.

--HG--
extra : convert_revision : 733f10abdf17d1f7eeca912f84f3df37e56fe510
2006-09-01 16:27:24 -04:00
Steve Reinhardt
30c93db065 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 54c63c9a8c7146bb45ecfa9a177ab0bda9541d1b
2006-09-01 12:59:48 -04:00
Steve Reinhardt
edeb8f39a7 Tweak proxy resolution error message.
--HG--
extra : convert_revision : 3b186209515975be0d8bc9acc214425adcaa16f2
2006-08-31 17:58:46 -07:00
Korey Sewell
82862e0e15 add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a
2006-08-31 20:51:30 -04:00
Steve Reinhardt
f9ae0dcf10 Move more common functionality into SimpleTimingPort,
allowing derived classes to be simplified.

--HG--
extra : convert_revision : c980d3aec5e6c044d8f41e96252726fe9a256605
2006-08-30 16:24:26 -07:00
Gabe Black
fa0fca3227 Change the cpu pointer in the InstRecord object to a thread context pointer.
--HG--
extra : convert_revision : 7efb2680cef4219281b94d680a4a7c75c123f89d
2006-08-30 19:08:24 -04:00
Gabe Black
05177abbc9 Forgot some commas
--HG--
extra : convert_revision : d178c87ba156be6302f871f1ab1030889586168f
2006-08-30 18:33:47 -04:00
Steve Reinhardt
a8a7ce2b88 Minor include file & formatting cleanup.
--HG--
extra : convert_revision : fa23563b2897687752379d63ddab5cccb92484ba
2006-08-30 09:57:46 -07:00
Steve Reinhardt
8bc3c2b192 Add FULL_SYSTEM check to example/fs.py.
--HG--
extra : convert_revision : 4cab46e73f29d2c9d24d9c0c847d598bf6d5c389
2006-08-29 14:36:35 -07:00
Steve Reinhardt
b0bf1e84e4 Add missing cpu mem param to example/se.py.
configs/example/se.py:
    Add missing cpu mem param.

--HG--
extra : convert_revision : 29a11b09524612f079b8998e99b8f5ee8c67c8a6
2006-08-29 14:14:29 -07:00
Gabe Black
bdb5df86a3 ASI constants.
--HG--
extra : convert_revision : 888024c9f7e909fa377de6d67a41ea1d4cf9945a
2006-08-29 16:08:56 -04:00