Commit graph

449 commits

Author SHA1 Message Date
Andreas Hansson
ade53def92 Ruby: Connect system port in Ruby network test
This patch moves the connection of the system port to create_system in
Ruby.py. Thereby it allows the failing Ruby test (and other Ruby
systems) to run again.
2012-01-30 09:37:06 -05:00
Nilay Vaish
f19b3f30b4 X86 Regressions: Update stats due to introduction of TSO 2012-01-28 19:09:17 -06:00
Ali Saidi
a17dbdf883 stats: Update stats for final tick and memory bandwidth patches 2012-01-25 17:19:50 +00:00
Andreas Hansson
2208ea049f MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the
bus ports to be a master port and a slave port. This greatly
simplifies the assumptions on both sides as either port only has to
deal with requests or responses. The following patches introduce the
notion of master and slave ports, and would not be possible without
this split of responsibilities.

In making the bridge unidirectional, the address range mechanism of
the bridge is also changed. For the cases where communication is
taking place both ways, an additional bridge is needed. This causes
issues with the existing mechanism, as the busses cannot determine
when to stop iterating the address updates from the two bridges. To
avoid this issue, and also greatly simplify the specification, the
bridge now has a fixed set of address ranges, specified at creation
time.
2012-01-17 12:55:09 -06:00
Andreas Hansson
f85286b3de MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.

The following replacements are made:
FunctionalPort      > PortProxy
TranslatingPort     > SETranslatingPortProxy
VirtualPort         > FSTranslatingPortProxy

--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-17 12:55:08 -06:00
Andreas Hansson
06c39a154c Ruby: Change the access permissions for MOESI hammer
Regression statistics update.
2012-01-17 12:55:07 -06:00
Ali Saidi
8c7936c40c stats: undo parser change from initparam change 2012-01-16 22:37:05 -05:00
Nilay Vaish
d272bdb1bf MOESI Hammer: Update regression test output 2012-01-10 17:28:49 -06:00
Nilay Vaish
a5a2b9ecbd X86 Regressions: Update stats due to fence instruction 2012-01-10 09:59:01 -06:00
Ali Saidi
8d757038b5 stats: Update stats for ARM init param changes. 2012-01-09 18:08:20 -06:00
Brad Beckmann
cb6ea0492f regress: updated hammer memtest and rubytest outputs
--HG--
extra : rebase_source : b02ad38b477d87bf28f7677c985ec7fe9a7d4694
2011-12-01 11:54:30 -08:00
Ali Saidi
d1dd7a24db imported patch ext/stats_updates.patch
--HG--
extra : rebase_source : 4697ba9eb1ca8c67fe0915fb8340d7d4ae94caba
2011-12-01 00:15:23 -08:00
Chander Sudanthi
61c14da751 O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.

--HG--
extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b
2011-12-01 00:15:22 -08:00
Ali Saidi
e436d187e7 SPARC: update SE stats for FP fix
--HG--
extra : rebase_source : 954a009a9f8eef6cae6050ee99f264e0fb456f85
2011-11-30 18:57:11 -05:00
Gabe Black
0e621fd136 SPARC: Update the FS stats for the recent FP fix.
--HG--
extra : rebase_source : 643e3541507576e30d9cd4dec045e5b94532c342
2011-11-28 04:19:57 -05:00
Nilay Vaish
f171a29118 Regression: Update statistics for x86 long regression tests
This patch updates reference statistics for the regression tests. This
update was necessitated by a recent change in behavior of some instructions
in the x86 architecture.
2011-11-17 22:53:56 -06:00
Nilay Vaish
472645d62a Tests: Update stats due to addition of fence microop 2011-11-05 15:32:23 -05:00
Steve Reinhardt
c6dd122fee tests: fix spurious scons "Error 1" messages
Turns out these are due to diff reporting that files
acutally differed via a non-zero exit code.
2011-10-22 16:52:07 -07:00
Ali Saidi
ae62d97158 MIPS: Fix regressions tests 2011-09-17 12:34:03 -04:00
Ali Saidi
28a2236ec1 O3: Update stats for new ordering fix. 2011-09-13 12:58:09 -04:00
Gabe Black
c5fd6f4fec MIPS: Update MIPS stats for cleaned up operand checks. 2011-09-09 01:35:05 -07:00
Ali Saidi
ba265abbfd ARM: Add some MP regressions and clean up the disk images and kernels a bit 2011-08-19 15:08:09 -05:00
Ali Saidi
999cd8aef5 StoreSet: Update stats for store-set clearing 2011-08-19 15:08:08 -05:00
Ali Saidi
f125ef22b9 O3: Update stats for LSQ changes. 2011-08-19 15:08:06 -05:00
Gabe Black
cbf7982081 X86: Add an X86_FS o3 regression. 2011-08-14 18:34:17 -07:00
Gabe Black
a81d4a8fcd Stats: Small update to stats for change to x86 inst flags. 2011-08-13 23:03:21 -07:00
Gabe Black
6bbd74e2d9 SCons,tests: Tell scons about pc-o3-timing regressions. 2011-08-09 11:33:12 -07:00
Gabe Black
c3e7b57fe7 Stats: Update stats for the end of macroop O3 fix. 2011-08-09 11:31:48 -07:00
Gabe Black
8586a800b7 Stats: Update stats for the recent O3 interrupt change. 2011-08-09 03:37:45 -07:00
Nilay Vaish
821dfc1289 BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
2011-08-08 10:50:13 -05:00
Gabe Black
9c806fe65a Stats: Update stats for the previous change. 2011-08-07 15:41:09 -07:00
Gabe Black
a1aaeac2f9 Stats: Update the stats after the uninitialized branch predictor variable fix. 2011-08-07 09:22:18 -07:00
Nilay Vaish
1b49c56679 Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
2011-08-02 00:10:08 -05:00
Gabe Black
6308ca27ff Stats: Update stats for the recent fix to fetch. 2011-07-30 23:23:01 -07:00
Korey Sewell
145deb7c88 inorder-fs: temp. regression removal
remove this regression till the fix for the hwrei instruction is put in
2011-07-15 21:26:18 -04:00
Ali Saidi
09914cdf8f ARM: Update stats for better miscreg support for MP configurations. 2011-07-15 11:53:35 -05:00
Ali Saidi
3ebfe2eb01 O3: Update stats for fetch and bp changes. 2011-07-10 12:56:09 -05:00
Gabe Black
a4bd05dc37 X86: Add a config for an FS regression on O3. 2011-07-05 17:46:46 -07:00
Gabe Black
d42e471baa Stats: Update stats for the x86 store fault fix. 2011-07-02 22:31:42 -07:00
Brad Beckmann
12dc51ff0d Regression: Updates regression outputs for Ruby memtest
This patch updates the regression outputs for Ruby memtest. This was
required because of the changes carried out by the addition of functional
access support to Ruby.
2011-06-30 19:57:26 -05:00
Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
c86f849d5a Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
2011-06-30 19:49:26 -05:00
Korey Sewell
6630d4c64b inorder: sparc: add 02.insttest regression 2011-06-20 22:44:24 -04:00
Korey Sewell
d1e8be9a73 inorder: sparc: add hello world regression
- add InOrderCPU compile option to SPARC
- add hello regression for SPARC
2011-06-20 22:44:22 -04:00
Korey Sewell
08c1a6f41b merge regression updates 2011-06-20 18:58:31 -04:00
Korey Sewell
b5736ba4ef alpha:o3:simple: update simout/err files
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning

Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
2011-06-20 18:57:14 -04:00
Korey Sewell
9124f46587 inorder: alpha-hello regression update 2011-06-20 12:21:10 -04:00
Korey Sewell
97449ef3da inorder: update eon regr w/eon info
previous commit copied over O3 stats, this one puts the inorder ones in the right place
2011-06-19 21:54:53 -04:00
Korey Sewell
d16b0dc319 inorder: add 10.linux-boot regression 2011-06-19 21:43:43 -04:00
Korey Sewell
60da569846 inorder: add eon regression 2011-06-19 21:43:43 -04:00
Korey Sewell
55dce6419d inorder: update SE regressions 2011-06-19 21:43:42 -04:00