Gabe Black
9e32ff3491
ARM: Implement the VFP version of vabs.
2010-06-02 12:58:14 -05:00
Gabe Black
cd0a6a1303
ARM: Implement the VFP version of vneg.
2010-06-02 12:58:14 -05:00
Gabe Black
65f5204325
ARM: Implement the VFP version of vmul.
2010-06-02 12:58:14 -05:00
Gabe Black
19e05d7e8d
ARM: Move the VFP data operation decode into a function.
2010-06-02 12:58:14 -05:00
Gabe Black
4491170df6
ARM: Make integer division by zero return a fault.
2010-06-02 12:58:13 -05:00
Gabe Black
c5a8a1d673
ARM: Decode ARM unconditional MRC and MCR instructions.
2010-06-02 12:58:13 -05:00
Gabe Black
98fe7b0fbe
ARM: Move the CP15 decode block into a function.
2010-06-02 12:58:13 -05:00
Gabe Black
5d9191a428
ARM: Decode the unconditional version of ARM fp instructions.
2010-06-02 12:58:13 -05:00
Gabe Black
81b7c3d264
ARM: Move the FP decode blocks into functions.
2010-06-02 12:58:13 -05:00
Gabe Black
e21f93702a
ARM: Warn/ignore when TLB maintenance operations are performed.
2010-06-02 12:58:13 -05:00
Gabe Black
b5cfa9361b
ARM: Convert the CP15 registers from MPU to MMU.
2010-06-02 12:58:13 -05:00
Ali Saidi
556ea0ee57
ARM: Add some support for wfi/wfe/yield/etc
2010-06-02 12:58:13 -05:00
Ali Saidi
65a5177b53
ARM: Undef instruction on invalid user CP15 access
2010-06-02 12:58:13 -05:00
Gabe Black
2e4ddbd234
ARM: Decode the VSTR instruction.
2010-06-02 12:58:12 -05:00
Gabe Black
6106bd18cd
ARM: Implement the vstr instruction.
2010-06-02 12:58:12 -05:00
Ali Saidi
f64c8bafd2
ARM: BXJ should be BX when there is no J support
2010-06-02 12:58:12 -05:00
Gabe Black
67766cbf17
ARM: Fix the implementation of the VFP ldm and stm macroops.
...
There were four bugs in these instructions. First, the loaded value was being
stored into a floating point register as floating point, changing the value as
it was transfered. Second, the meaning of the "up" bit had been reversed.
Third, the statically sized microop array wasn't bit enough for all possible
inputs. It's now dynamically sized and should always be big enough. Fourth,
the offset was stored as an unsigned 8 bit value. Negative offsets would look
like moderately large positive offsets.
2010-06-02 12:58:12 -05:00
Gabe Black
ad9c5af945
ARM: Fix up thumb decoding of coproc instructions.
2010-06-02 12:58:12 -05:00
Gabe Black
dea707704f
ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC.
2010-06-02 12:58:12 -05:00
Gabe Black
943b77b9bb
ARM: Decode the VLDR instruction.
2010-06-02 12:58:12 -05:00
Gabe Black
4f130683e0
ARM: Implement the VLDR instruction.
2010-06-02 12:58:12 -05:00
Gabe Black
dbec303864
ARM: Decode all the various forms of vmov.
2010-06-02 12:58:12 -05:00
Gabe Black
ff3996b24d
ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11.
2010-06-02 12:58:12 -05:00
Gabe Black
dd1aedc98b
ARM: Implement the various versions of VMOV.
2010-06-02 12:58:12 -05:00
Gabe Black
1f059541d6
ARM: Add a new RegImmOp base class.
2010-06-02 12:58:12 -05:00
Gabe Black
6976b4890a
ARM: Add a RegRegImmOp base class.
2010-06-02 12:58:12 -05:00
Gabe Black
186cfe3ae3
ARM: Widen the immediate fields in the misc instruction classes.
2010-06-02 12:58:12 -05:00
Gabe Black
abda50173c
ARM: Add fp operands to operands.isa.
2010-06-02 12:58:12 -05:00
Gabe Black
6365d29c21
ARM: Decode the VMRS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
aade63a8fe
ARM: Implement the VMRS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
a8b56b452c
ARM: Decode the VMSR instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
06008c54eb
ARM: Implement the VMSR instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
0ff71c7c34
ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.
2010-06-02 12:58:11 -05:00
Gabe Black
c3bf29bbea
ARM: Implement the udiv instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
f3e65c2de2
ARM: Implement the sdiv instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
ba33db8fd6
ARM: Decode the CPS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
7861b084f6
ARM: Implement the CPS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
eb1447302d
ARM: Decode the SRS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
bb6fea91da
ARM: Implement the SRS instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
dbee6e0c54
ARM: Add a base class for SRS.
2010-06-02 12:58:11 -05:00
Gabe Black
a5ea52bb45
ARM: Allow flattening into any mode.
2010-06-02 12:58:11 -05:00
Gabe Black
698ee26c6b
ARM: Decode TBB and TBH.
2010-06-02 12:58:11 -05:00
Gabe Black
6fa713a66c
ARM: Decode the setend instruction.
2010-06-02 12:58:11 -05:00
Gabe Black
4683cd1655
ARM: Define the setend instruction.
2010-06-02 12:58:10 -05:00
Gabe Black
fb23297914
ARM: Make a base class for instructions that use only an immediate.
2010-06-02 12:58:10 -05:00
Gabe Black
247acd93c4
ARM: Decode the arm version of ldrexd.
2010-06-02 12:58:10 -05:00
Gabe Black
3ad31f61c2
ARM: Decode the strex instructions.
2010-06-02 12:58:10 -05:00
Gabe Black
54ab07e636
ARM: Implement the strex instructions.
2010-06-02 12:58:10 -05:00
Gabe Black
6fb5189c47
ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.
2010-06-02 12:58:10 -05:00
Gabe Black
3aa8faf177
ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.
2010-06-02 12:58:10 -05:00
