gem5/src/arch/arm/isa
2010-06-02 12:58:12 -05:00
..
decoder ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC. 2010-06-02 12:58:12 -05:00
formats ARM: Decode the VLDR instruction. 2010-06-02 12:58:12 -05:00
insts ARM: Implement the VLDR instruction. 2010-06-02 12:58:12 -05:00
templates ARM: Add a new RegImmOp base class. 2010-06-02 12:58:12 -05:00
bitfields.isa ARM: Rearrange the load/store double/exclusive, table branch thumb decoding. 2010-06-02 12:58:07 -05:00
copyright.txt ARM: Remove IsControl from operands that don't imply control transfers. 2010-06-02 12:57:59 -05:00
includes.isa ARM: Define versions of MSR and MRS outside the decoder. 2010-06-02 12:58:05 -05:00
main.isa ARM: Define the load instructions from outside the decoder. 2010-06-02 12:58:01 -05:00
operands.isa ARM: Add fp operands to operands.isa. 2010-06-02 12:58:12 -05:00