Gabe Black 1f059541d6 ARM: Add a new RegImmOp base class.		2010-06-02 12:58:12 -05:00
..
decoder	ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.	2010-06-02 12:58:11 -05:00
formats	ARM: Decode the VMRS instruction.	2010-06-02 12:58:11 -05:00
insts	ARM: Implement the VMRS instruction.	2010-06-02 12:58:11 -05:00
templates	ARM: Add a new RegImmOp base class.	2010-06-02 12:58:12 -05:00
bitfields.isa	ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.	2010-06-02 12:58:07 -05:00
copyright.txt	ARM: Remove IsControl from operands that don't imply control transfers.	2010-06-02 12:57:59 -05:00
includes.isa	ARM: Define versions of MSR and MRS outside the decoder.	2010-06-02 12:58:05 -05:00
main.isa	ARM: Define the load instructions from outside the decoder.	2010-06-02 12:58:01 -05:00
operands.isa	ARM: Add fp operands to operands.isa.	2010-06-02 12:58:12 -05:00