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378 commits

Author SHA1 Message Date
Lisa Hsu
868d112578 fix the argument to m5.simulate() on a checkpoint. 
src/sim/stat_control.cc:
    add curTick to reset stats printf.

--HG--
extra : convert_revision : da8cf5921e81b73f47d6831d539ca1fbdace3d1d
 2006-10-05 13:18:32 -04:00
Nathan Binkert
4142f8f7c0 Static global object don't work well, if the variables are 
accessed during the construction of another static global
object because there are no guarantees on ordering of
construction, so stick the static global into a function
as a static local and return a reference to the variable.
This fixes the exit callback stuff on my Mac.

--HG--
extra : convert_revision : 63a3844d0b5ee18e2011f1bc7ca7bb703284da94
 2006-10-05 03:37:43 -07:00
Kevin Lim
51c8eab7b3 Oops, forgot to assign the option to the param context. 
--HG--
extra : convert_revision : 022c3efaa3ade3fca3dfe554ececa4eeb396dc9c
 2006-10-02 18:13:42 -04:00
Kevin Lim
cada047319 Merge ktlim@zizzer:/bk/newmem 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/newmem

--HG--
extra : convert_revision : 1010a4ee8e1abec0e8290637feee523ca9ef9a9b
 2006-10-02 18:12:21 -04:00
Kevin Lim
c78b6634a2 Be sure to set progress interval. 
--HG--
extra : convert_revision : 793ca7d6af1deedf6b1fb4676288b11114f583a6
 2006-10-02 18:10:10 -04:00
Kevin Lim
e08aa72b3d Add in ability to start a trace at a specific cycle. 
--HG--
extra : convert_revision : 54098f3974d2a05d60e57113f7ceb46cb7a26672
 2006-10-02 12:04:24 -04:00
Kevin Lim
568fa11084 Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs. 
src/arch/alpha/isa_traits.hh:
    This got changed to the wrong version by accident.
src/cpu/base.cc:
    Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
    Fix up the CPU Progress Event to not print itself if it's set to 0.  Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
    Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
    Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
    Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
    Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
    Switch out updates from the version of m5 I have.  Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
    Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
    Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
    Use proper method to get flags.  Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
    Support profiling.
src/cpu/ozone/cpu.hh:
    Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
    Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
    Get flags correctly.
src/cpu/ozone/thread_state.hh:
    Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
    Allow for loading of symbol file.  Be sure to use ThreadContext and not ExecContext.

--HG--
extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
 2006-10-02 11:58:09 -04:00
Kevin Lim
4ed184eade Merge ktlim@zamp:./local/clean/o3-merge/m5 
into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
    Hand merge.

--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
 2006-09-30 23:43:23 -04:00
Ali Saidi
17b0e9714d add boiler plate intel nic code 
src/SConscript:
    add intel nic to sconscript
src/dev/pcidev.cc:
    fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
    add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
    Move config_latency into pci where it belogs

--HG--
extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d
 2006-09-18 20:12:45 -04:00
Gabe Black
30b87e90f8 Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters. 
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
    Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
    Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.

--HG--
extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
 2006-09-17 03:00:55 -04:00
Gabe Black
e4fcef5851 Changes to correct stat behavior 
--HG--
extra : convert_revision : 43e5788105738aebd79acb05301bb7da68bfe129
 2006-09-15 21:43:12 -04:00
Gabe Black
8abab05c83 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 91aacb435c223e8c37f6ba0a458b0dee55edcaf2
 2006-09-15 00:59:39 -04:00
Ali Saidi
44c6f953b0 Merge zizzer:/bk/newmem 
into  zeep.pool:/z/saidi/work/m5.newmem.head

--HG--
extra : convert_revision : 14ac24236ff65b7e489c1ce4b4e9a295966013b8
 2006-09-11 17:57:30 -04:00
Ali Saidi
46502851ab add annotation code to m5 
configs/common/Benchmarks.py:
    add annotate test app
src/SConscript:
    add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
    add annotate instructions
src/base/traceflags.py:
    Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
    add anotate ops

--HG--
extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
 2006-09-11 17:57:20 -04:00
Steve Reinhardt
a7e8a78958 Add support for assigning lists of ports or proxies to VectorPorts. 
Includes support for printing readable VectorPort and Proxy names
(via __str__).

--HG--
extra : convert_revision : c48534a498b3036fe6ac45ff1606656546c79afb
 2006-09-08 19:10:11 -04:00
Steve Reinhardt
c15e6d8e0a Try to make unproxy order more deterministic. 
--HG--
extra : convert_revision : 0bc543014dced6dfed4122d4c1b8f22e6c8d7a13
 2006-09-06 22:37:35 -07:00
Steve Reinhardt
545cbec5f7 Enable proxies (Self/Parent) for specifying ports. 
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().

src/python/m5/multidict.py:
    Make get() return None by default, to match semantics
    of built-in dictionary objects.

--HG--
extra : convert_revision : db73b6cdd004a82a08b2402afd1e16544cb902a4
 2006-09-05 22:04:34 -07:00
Steve Reinhardt
89f0bc9e4c Print ports in config.ini as well. 
--HG--
extra : convert_revision : 703d3a57250613315735709de8f40a9956cee6e2
 2006-09-05 12:22:47 -07:00
Steve Reinhardt
c39aea440c More Python hacking to deal with config.py split 
and resulting recursive import trickiness.

--HG--
extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
 2006-09-04 17:14:07 -07:00
Steve Reinhardt
1233dbb998 Split config.py into multiple files. 
Some tweaking to deal with mutually recursive imports.

--HG--
rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
 2006-09-04 10:52:26 -07:00
Steve Reinhardt
a658d25d42 config.py: 
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.

src/python/m5/config.py:
    Import of changes for auto-generation of C++ param structs
    from my old m5 working directory.
    This code is *broken* because pieces need to be shuffled around
    to satisfy name dependencies, but that really messes up the
    diff, so I want to make an intermediate commit here.

--HG--
extra : convert_revision : cb25ee1f4f77d1902511ee9aa766403733dd8841
 2006-09-04 10:40:33 -07:00
Gabe Black
b11018ca12 Made system calls use the uid, etc parameters from the live process. 
--HG--
extra : convert_revision : 2aadb87b4602324423aadb903010f5b49fcef41b
 2006-09-03 02:12:11 -04:00
Gabe Black
c32ef326d2 Fix up the parameters to getInstRecord 
--HG--
extra : convert_revision : 0fac43035a2510d3a3f596d3d8f57193045570f6
 2006-09-03 02:10:05 -04:00
Gabe Black
936d8c3e65 Make the ASI constants available to the decoder. 
--HG--
extra : convert_revision : 65f2e02ce8f5e4f0c8727ebf16c927c7a6a4fe7f
 2006-09-03 02:09:25 -04:00
Gabe Black
16f9b901be Make the auxiliary vectors use the uid, euid, gid and egid parameters from the live process 
--HG--
extra : convert_revision : 945b5883a15a6df35709edea2731f54a2448e418
 2006-09-03 02:08:24 -04:00
Gabe Black
387bbe40d1 Fixing up parameters of getInstRecord 
--HG--
extra : convert_revision : 4ce06ac4f7d135cc04b39cf0e957a2539c7e946d
 2006-09-03 02:05:44 -04:00
Gabe Black
96dabdc9b0 Added uid, euid, gid, egid, pid and ppid parameters to a live process. 
--HG--
extra : convert_revision : 2101be8000bcdaf683730cfc079b4b78e34365d0
 2006-09-03 02:04:25 -04:00
Gabe Black
14cc9baba5 A quick fix to isolate the tracing code to SPARC 
--HG--
extra : convert_revision : 90c77f4d01101cad55f60d528b2a8be92d2f9aba
 2006-09-03 02:02:56 -04:00
Steve Reinhardt
abe18be544 Merge zizzer.eecs.umich.edu:/bk/newmem 
into  vm1.(none):/home/stever/bk/newmem-head

--HG--
extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
 2006-09-01 17:12:43 -07:00
Steve Reinhardt
30c93db065 Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem 
into  zizzer.eecs.umich.edu:/z/stever/bk/newmem-head

--HG--
extra : convert_revision : 54c63c9a8c7146bb45ecfa9a177ab0bda9541d1b
 2006-09-01 12:59:48 -04:00
Steve Reinhardt
edeb8f39a7 Tweak proxy resolution error message. 
--HG--
extra : convert_revision : 3b186209515975be0d8bc9acc214425adcaa16f2
 2006-08-31 17:58:46 -07:00
Korey Sewell
82862e0e15 add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models 
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a
 2006-08-31 20:51:30 -04:00
Steve Reinhardt
f9ae0dcf10 Move more common functionality into SimpleTimingPort, 
allowing derived classes to be simplified.

--HG--
extra : convert_revision : c980d3aec5e6c044d8f41e96252726fe9a256605
 2006-08-30 16:24:26 -07:00
Gabe Black
fa0fca3227 Change the cpu pointer in the InstRecord object to a thread context pointer. 
--HG--
extra : convert_revision : 7efb2680cef4219281b94d680a4a7c75c123f89d
 2006-08-30 19:08:24 -04:00
Gabe Black
05177abbc9 Forgot some commas 
--HG--
extra : convert_revision : d178c87ba156be6302f871f1ab1030889586168f
 2006-08-30 18:33:47 -04:00
Steve Reinhardt
a8a7ce2b88 Minor include file & formatting cleanup. 
--HG--
extra : convert_revision : fa23563b2897687752379d63ddab5cccb92484ba
 2006-08-30 09:57:46 -07:00
Gabe Black
bdb5df86a3 ASI constants. 
--HG--
extra : convert_revision : 888024c9f7e909fa377de6d67a41ea1d4cf9945a
 2006-08-29 16:08:56 -04:00
Gabe Black
02f3b21c42 Set both xcc.c and icc.c on return from a syscall. 
--HG--
extra : convert_revision : 9c2b32d735b816021cdd3af24002f309e22a8d64
 2006-08-29 16:07:22 -04:00
Gabe Black
9231d2235d Don't store if there's a fault. 
--HG--
extra : convert_revision : fc852bee572b36daab7a34ee1820f856ccd71ca5
 2006-08-29 16:06:27 -04:00
Gabe Black
df0cbf890a Extended the reg delta output. 
--HG--
extra : convert_revision : 61c714a8c4faeb30d784b1ef1da0295474b8dc45
 2006-08-29 16:04:28 -04:00
Gabe Black
292d3ae14a Fiddled with the floating point accessors. 
--HG--
extra : convert_revision : 78cbd0c28d3fa1109eb2eacaf2a8009f13158a9b
 2006-08-29 16:02:54 -04:00
Gabe Black
7ac1d10eb5 Cleaned up floating point by removing unnecessary conversions and by implementing faligndata more correctly. 
--HG--
extra : convert_revision : 44e778ce8f8d8606b6a50f3f12f0b87e1bf0ed66
 2006-08-29 02:40:24 -04:00
Steve Reinhardt
72eb4f5f12 Clean up BAR setting code. 
--HG--
extra : convert_revision : 8378be6cd6f55af7a199296cb2ff61ee94849bf7
 2006-08-28 11:17:49 -07:00
Steve Reinhardt
b77da23e1a Get rid of unneeded union. 
Verify that BAR sizes are powers of two.

--HG--
extra : convert_revision : ce8dca07aaf1a340cc166b99b5858613a954e2fd
 2006-08-28 11:01:25 -07:00
Steve Reinhardt
19d51452b1 Get rid of unused BARAddrs[] in PciConfigData object. 
--HG--
extra : convert_revision : a82e05326ca6150c70cb288b28f9f6eee89ad93d
 2006-08-28 10:34:15 -07:00
Steve Reinhardt
acfa88f732 Cleanup: formatting, comments, DPRINTFs. 
--HG--
extra : convert_revision : 565ab099f1c0744a13959e721c19dd03b7630f04
 2006-08-28 10:28:31 -07:00
Steve Reinhardt
55bde23071 Fix remote gdb buffer overflow. 
--HG--
extra : convert_revision : e5e5206bdd48120cebcb1e339b1dab2e10f4b6cf
 2006-08-28 09:58:03 -07:00
Steve Reinhardt
98e71d9ba6 Make address formats consistent in DPRINTFs. 
--HG--
extra : convert_revision : 73c6616aa9228c08e21fcc134dd0e675cd57aee6
 2006-08-28 09:55:13 -07:00
Steve Reinhardt
c5384366b6 Add dup() support (from Antti Miettinen). 
--HG--
extra : convert_revision : 72c834666afa3c353da026617ad5e7a762eb645f
 2006-08-28 07:39:56 -07:00
Ron Dreslinski
95e7b85c8b Still need LL/SC support in cache, add hack to always return success for now 
--HG--
extra : convert_revision : b354bd91be8c1bbb3aca7b4ba9e7e3e117ced164
 2006-08-22 16:09:34 -04:00