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Still need LL/SC support in cache, add hack to always return success for now

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--HG--
extra : convert_revision : b354bd91be8c1bbb3aca7b4ba9e7e3e117ced164
This commit is contained in:
Ron Dreslinski 2006-08-22 16:09:34 -04:00
parent 9f18764441
commit 95e7b85c8b
1 changed files with 14 additions and 0 deletions
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14
src/mem/cache/cache_impl.hh vendored
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@ -60,6 +60,9 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
{
if (isCpuSide)
{
if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
pkt->req->setScResult(1);
}
access(pkt);
}
else
@ -79,6 +82,11 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
{
if (isCpuSide)
{
//Temporary solution to LL/SC
if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
pkt->req->setScResult(1);
}
probe(pkt, true);
//TEMP ALWAYS SUCCES FOR NOW
pkt->result = Packet::Success;
@ -103,6 +111,12 @@ doFunctionalAccess(Packet *pkt, bool isCpuSide)
{
//TEMP USE CPU?THREAD 0 0
pkt->req->setThreadContext(0,0);
//Temporary solution to LL/SC
if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
assert("Can't handle LL/SC on functional path\n");
}
probe(pkt, true);
//TEMP ALWAYS SUCCESFUL FOR NOW
pkt->result = Packet::Success;