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Author SHA1 Message Date
Ali Saidi
e6d3fe8a0c ARM: Update regression tests for ldr/str microcode changes. 2010-08-25 19:10:42 -05:00
Gene WU
4d8f4db8d1 ARM: Use fewer micro-ops for register update loads if possible. 
Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
 2010-08-25 19:10:42 -05:00
Ali Saidi
c2d5d2b53d ARM: Set the high bits in the part number so it's considered new by some code. 2010-08-25 19:10:42 -05:00
Ali Saidi
99fafb72b8 ARM: Fix VFP enabled checks for mem instructions 2010-08-25 19:10:42 -05:00
Gabe Black
63464d950e ARM: Seperate out the renamable bits in the FPSCR. 2010-08-25 19:10:42 -05:00
Gabe Black
93ce7238bf ARM: Eliminate some unused enums. 2010-08-25 19:10:42 -05:00
Gabe Black
0efe2f6769 ARM: Fix type comparison warnings in Neon. 2010-08-25 19:10:42 -05:00
Gabe Black
54a919f225 ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled. 2010-08-25 19:10:42 -05:00
Gabe Black
6368edb281 ARM: Implement all ARM SIMD instructions. 2010-08-25 19:10:42 -05:00
Gabe Black
f4f6b31df1 ARM: Expand the mode checking utility functions. 
inUserMode now can take either a threadcontext or a CPSR value directly. If
given a thread context it just extracts the CPSR and calls the other version.
An inPrivelegedMode function was also implemented which just returns the
opposite of inUserMode.
 2010-08-25 19:10:41 -05:00
Ali Saidi
75955d6c42 Tracing: Fix trace so 'Predicated False' doesn't show up 2010-08-25 19:10:41 -05:00
Steve Reinhardt
62c06c1403 mem: fix dumb typo in copyrights 2010-08-25 14:08:27 -07:00
Brad Beckmann
d4318457d1 config: changed ruby config file names to be consistent 2010-08-24 14:08:23 -07:00
Brad Beckmann
0e610290d0 config: remove ruby's requirement on the timing cmd line param 
Since ruby only works in timing mode, explicitly requiring the timing cmd line
param to be specified is not necessary.
 2010-08-24 13:20:32 -07:00
Brad Beckmann
8572d8fd91 config: fixed ruby dma device connections 2010-08-24 13:20:31 -07:00
Brad Beckmann
e983ef9e8c testers: move testers to a new directory 
This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.

--HG--
rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py
rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc
rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh
rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc
rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh
rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc
rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh
rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py
rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript
rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc
rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh
rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py
rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript
rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc
rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh
rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc
rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh
rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc
rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh
rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc
rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh
rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py
rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
 2010-08-24 12:07:22 -07:00
Brad Beckmann
20b2f0ce9f MOESI_hammer: fixed bug for dma reads in single cpu systems 2010-08-24 12:06:53 -07:00
Gabe Black
c13640a89c Faults: Get rid of some commented out code in sim/faults.hh. 2010-08-23 16:23:47 -07:00
Gabe Black
25ffa8eb8b X86: Create a directory for files that define register indexes. 
This is to help tidy up arch/x86. These files should not be used external to
the ISA.

--HG--
rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh
rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh
rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh
rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh
rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh
 2010-08-23 16:14:24 -07:00
Gabe Black
7a6ed1b10b Power: Get rid of unused checkFpEnableFault. 
This function was brought in from another ISA and doesn't actually do anything
or get used.
 2010-08-23 16:14:23 -07:00
Gabe Black
943c171480 ISA: Get rid of old, unused utility functions cluttering up the ISAs. 2010-08-23 16:14:20 -07:00
Gabe Black
9581562e65 X86: Get rid of the flagless microop constructor. 
This will reduce clutter in the source and hopefully speed up compilation.
 2010-08-23 09:44:19 -07:00
Gabe Black
f6182f948b X86: Make the TLB fault instead of panic when something is unmapped in SE mode. 
The fault object, if invoked, would then panic. This is a bit less direct, but
it means speculative execution won't panic the simulator.
 2010-08-23 09:44:19 -07:00
Gabe Black
172e45fc97 X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR. 
--HG--
rename : src/arch/x86/types.hh => src/arch/x86/types.cc
 2010-08-23 09:44:19 -07:00
Gabe Black
249549f9c3 X86: Define a noop ExtMachInst. 2010-08-23 09:44:19 -07:00
Gabe Black
d43eb42d00 X86: Mark serializing macroops and regular instructions as such. 2010-08-23 09:44:19 -07:00
Gabe Black
69fc2af006 X86: Add a .serializing directive that makes a macroop serializing. 
This directive really just tells the macroop to set IsSerializing and
IsSerializeAfter on its final microop.
 2010-08-23 09:44:19 -07:00
Gabe Black
5a1dbe4d99 X86: Consolidate extra microop flags into one parameter. 
This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
 2010-08-23 09:44:19 -07:00
Gabe Black
b187e7c9cc CPU: Make the constants for StaticInst flags visible outside the class. 2010-08-23 09:44:19 -07:00
Ali Saidi
6f24da359f BUILD: GCC 4.4.1/2 have a bug in their auto-vectorizer that we trip on 2010-08-23 11:18:42 -05:00
Ali Saidi
03584ad439 ALPHA: The previous O3 patch causes a slight stats change with fullsys. 2010-08-23 11:18:42 -05:00
Min Kyu Jeong
d8d6b869a2 O3: Skipping mem-order violation check for uncachable loads. 
Uncachable load is not executed until it reaches the head of the ROB,
hence cannot cause one.
 2010-08-23 11:18:42 -05:00
Min Kyu Jeong
e6a0be648e ARM: Improve printing of uop disassembly. 2010-08-23 11:18:42 -05:00
Min Kyu Jeong
d2fac84b95 ARM: Clean up flattening for SPSR adding 2010-08-23 11:18:41 -05:00
Gene Wu
a02d82f9f8 ARM: Implement DBG instruction that doesn't do much for now. 2010-08-23 11:18:41 -05:00
Gene Wu
d6736384b2 MEM: Make CLREX a first class request operation and clear locks in caches when it in received 2010-08-23 11:18:41 -05:00
Gene Wu
23626d99af ARM: Make sure that software prefetch instructions can't change the state of the TLB 2010-08-23 11:18:41 -05:00
Gene Wu
1fd104fc35 ARM: Don't write tracedata on writes, it might have been freed already. 2010-08-23 11:18:41 -05:00
Gene Wu
9db2ab8a62 ARM: Implement CLREX init/complete acc methods 2010-08-23 11:18:41 -05:00
Gene Wu
f29e09746a ARM: Fix Uncachable TLB requests and decoding of xn bit 2010-08-23 11:18:41 -05:00
Gene Wu
4b9de42439 Devices: Allow a device to specify that a request is uncachable. 2010-08-23 11:18:41 -05:00
Gene Wu
aa601750f8 ARM: For non-cachable accesses set the UNCACHABLE flag 2010-08-23 11:18:41 -05:00
Gene Wu
7405f4b774 ARM: Implement DSB, DMB, ISB 2010-08-23 11:18:41 -05:00
Gene Wu
aabf478920 ARM: Get SCTLR TE bit from reset SCTLR 2010-08-23 11:18:41 -05:00
Gene Wu
1f032ad345 ARM: Implement CLREX 2010-08-23 11:18:41 -05:00
Gene Wu
66bcbec96e ARM: BX instruction can be contitional if last instruction in a IT block 
Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.
 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
ad2c3b008d CPU: Print out flatten-out register index as with IntRegs/FloatRegs traceflag 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
03286e9d4e CPU: Make Exec trace to print predication result (if false) for memory instructions 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
92ae620be8 ARM: mark msr/mrs instructions as SerializeBefore/After 
Since miscellaneous registers bypass wakeup logic, force serialization
to resolve data dependencies through them
* * *
ARM: adding non-speculative/serialize flags for instructions change CPSR
 2010-08-23 11:18:41 -05:00
Min Kyu Jeong
43c938d23e O3: Handle loads when the destination is the PC. 
For loads that PC is the destination, check if the load
was mispredicted again when the value being loaded returns from memory
 2010-08-23 11:18:40 -05:00