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X86: Consolidate extra microop flags into one parameter.

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This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
This commit is contained in:
Gabe Black 2010-08-23 09:44:19 -07:00
parent b187e7c9cc
commit 5a1dbe4d99
15 changed files with 116 additions and 195 deletions
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6
src/arch/x86/insts/microfpop.hh
View file

@ -60,13 +60,11 @@ namespace X86ISA
// Constructor
FpOp(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, int8_t _spm,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), src2(_src2.idx), dest(_dest.idx),
dataSize(_dataSize), spm(_spm)

5
src/arch/x86/insts/microldstop.hh
View file

@ -74,15 +74,14 @@ namespace X86ISA
//Constructor
LdStOp(ExtMachInst _machInst,
const char * mnem, const char * _instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
uint64_t setFlags,
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
uint64_t _disp, InstRegIndex _segment,
InstRegIndex _data,
uint8_t _dataSize, uint8_t _addressSize,
Request::FlagsType _memFlags,
OpClass __opClass) :
X86MicroopBase(machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast, __opClass),
X86MicroopBase(machInst, mnem, _instMnem, setFlags, __opClass),
scale(_scale), index(_index.idx), base(_base.idx),
disp(_disp), segment(_segment.idx),
data(_data.idx),

21
src/arch/x86/insts/micromediaop.hh
View file

@ -53,14 +53,11 @@ namespace X86ISA
// Constructor
MediaOpBase(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), dest(_dest.idx),
srcSize(_srcSize), destSize(_destSize), ext(_ext)
@ -98,14 +95,11 @@ namespace X86ISA
// Constructor
MediaOpReg(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
MediaOpBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
MediaOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _srcSize, _destSize, _ext,
__opClass),
src2(_src2.idx)
@ -122,14 +116,11 @@ namespace X86ISA
// Constructor
MediaOpImm(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint8_t _ext,
OpClass __opClass) :
MediaOpBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
MediaOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _srcSize, _destSize, _ext,
__opClass),
imm8(_imm8)

9
src/arch/x86/insts/microop.hh
View file

@ -96,16 +96,11 @@ namespace X86ISA
X86MicroopBase(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
OpClass __opClass) :
uint64_t setFlags, OpClass __opClass) :
X86ISA::X86StaticInst(mnem, _machInst, __opClass),
instMnem(_instMnem)
{
flags[IsMicroop] = isMicro;
flags[IsDelayedCommit] = isDelayed;
flags[IsFirstMicroop] = isFirst;
flags[IsLastMicroop] = isLast;
flags |= setFlags;
}
std::string generateDisassembly(Addr pc,

21
src/arch/x86/insts/microregop.hh
View file

@ -58,14 +58,11 @@ namespace X86ISA
// Constructor
RegOpBase(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
X86MicroopBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
X86MicroopBase(_machInst, mnem, _instMnem, setFlags,
__opClass),
src1(_src1.idx), dest(_dest.idx),
dataSize(_dataSize), ext(_ext)
@ -86,14 +83,11 @@ namespace X86ISA
// Constructor
RegOp(ExtMachInst _machInst,
const char *mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
const char *mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
RegOpBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
RegOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _dataSize, _ext,
__opClass),
src2(_src2.idx)
@ -111,14 +105,11 @@ namespace X86ISA
// Constructor
RegOpImm(ExtMachInst _machInst,
const char * mnem, const char *_instMnem,
bool isMicro, bool isDelayed,
bool isFirst, bool isLast,
const char * mnem, const char *_instMnem, uint64_t setFlags,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext,
OpClass __opClass) :
RegOpBase(_machInst, mnem, _instMnem,
isMicro, isDelayed, isFirst, isLast,
RegOpBase(_machInst, mnem, _instMnem, setFlags,
_src1, _dest, _dataSize, _ext,
__opClass),
imm8(_imm8)

11
src/arch/x86/isa/macroop.isa
View file

@ -185,11 +185,16 @@ let {{
allocMicroops = ''
micropc = 0
for op in self.microops:
isLast = (micropc == numMicroops - 1)
flags = ["IsMicroop"]
if micropc == numMicroops - 1:
flags.append("IsLastMicroop")
else:
flags.append("IsDelayedCommit")
if micropc == 0:
flags.append("IsFirstMicroop")
allocMicroops += \
"microops[%d] = %s;\n" % \
(micropc, op.getAllocator(True, not isLast,
micropc == 0, isLast))
(micropc, op.getAllocator(flags))
micropc += 1
if env.useStackSize:
useStackSize = "true"

19
src/arch/x86/isa/microops/base.isa
View file

@ -78,25 +78,14 @@ let {{
def __init__(self, name):
self.name = name
# This converts a python bool into a C++ bool
def cppBool(self, val):
if val:
return "true"
else:
return "false"
# This converts a list of python bools into
# a comma seperated list of C++ bools.
def microFlagsText(self, vals):
text = ""
for val in vals:
text += ", %s" % self.cppBool(val)
return text
def microFlagsText(self, flags):
wrapped = ("(1ULL << StaticInst::%s)" % flag for flag in flags)
return " | ".join(wrapped)
def getGeneratorDef(self, micropc):
return self.generatorTemplate % \
(self.className, micropc, \
self.getAllocator(True, True, False, False))
self.getAllocator(["IsMicroop", "IsDelayedCommit"]))
def getGenerator(self, micropc):
return self.generatorNameTemplate % (self.className, micropc)

23
src/arch/x86/isa/microops/debug.isa
View file

@ -50,8 +50,7 @@ output header {{
public:
MicroDebugBase(ExtMachInst _machInst, const char * mnem,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
std::string _message, uint8_t _cc);
MicroDebugBase(ExtMachInst _machInst, const char * mnem,
@ -69,8 +68,7 @@ def template MicroDebugDeclare {{
void buildMe();
public:
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
std::string _message, uint8_t _cc);
uint64_t setFlags, std::string _message, uint8_t _cc);
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
std::string _message, uint8_t _cc);
@ -96,18 +94,16 @@ output decoder {{
inline MicroDebugBase::MicroDebugBase(
ExtMachInst machInst, const char * mnem, const char * instMnem,
std::string _message, uint8_t _cc) :
X86MicroopBase(machInst, mnem, instMnem,
false, false, false, false, No_OpClass),
X86MicroopBase(machInst, mnem, instMnem, 0, No_OpClass),
message(_message), cc(_cc)
{
}
inline MicroDebugBase::MicroDebugBase(
ExtMachInst machInst, const char * mnem, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
std::string _message, uint8_t _cc) :
uint64_t setFlags, std::string _message, uint8_t _cc) :
X86MicroopBase(machInst, mnem, instMnem,
isMicro, isDelayed, isFirst, isLast, No_OpClass),
setFlags, No_OpClass),
message(_message), cc(_cc)
{
}
@ -129,11 +125,10 @@ def template MicroDebugConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
std::string _message, uint8_t _cc) :
%(base_class)s(machInst, "%(func)s", instMnem,
isMicro, isDelayed, isFirst, isLast, _message, _cc)
setFlags, _message, _cc)
{
buildMe();
}
@ -164,8 +159,8 @@ let {{
else:
self.cond = "0"
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock
def getAllocator(self, microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, "%(message)s", %(cc)s)''' % {
"class_name" : self.className,
"flags" : self.microFlagsText(microFlags),

16
src/arch/x86/isa/microops/fpop.isa
View file

@ -79,8 +79,7 @@ def template MicroFpOpDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, int8_t _spm);
@ -104,8 +103,7 @@ def template MicroFpOpConstructor {{
ExtMachInst machInst, const char * instMnem,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, int8_t _spm) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, 0,
_src1, _src2, _dest, _dataSize, _spm,
%(op_class)s)
{
@ -113,12 +111,10 @@ def template MicroFpOpConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, int8_t _spm) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_src1, _src2, _dest, _dataSize, _spm,
%(op_class)s)
{
@ -226,8 +222,8 @@ let {{
if spm:
self.className += "Top"
def getAllocator(self, *microFlags):
return '''new %(class_name)s(machInst, macrocodeBlock
def getAllocator(self, microFlags):
return '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(src1)s, %(src2)s, %(dest)s,
%(dataSize)s, %(spm)d)''' % {
"class_name" : self.className,

19
src/arch/x86/isa/microops/ldstop.isa
View file

@ -76,8 +76,7 @@ def template MicroLeaDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
uint64_t _disp, InstRegIndex _segment,
InstRegIndex _data,
@ -252,8 +251,7 @@ def template MicroLdStOpDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
uint64_t _disp, InstRegIndex _segment,
InstRegIndex _data,
@ -290,8 +288,7 @@ def template MicroLdStOpConstructor {{
InstRegIndex _data,
uint8_t _dataSize, uint8_t _addressSize,
Request::FlagsType _memFlags) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, 0,
_scale, _index, _base,
_disp, _segment, _data,
_dataSize, _addressSize, _memFlags, %(op_class)s)
@ -300,15 +297,13 @@ def template MicroLdStOpConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
uint64_t _disp, InstRegIndex _segment,
InstRegIndex _data,
uint8_t _dataSize, uint8_t _addressSize,
Request::FlagsType _memFlags) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_scale, _index, _base,
_disp, _segment, _data,
_dataSize, _addressSize, _memFlags, %(op_class)s)
@ -335,8 +330,8 @@ let {{
self.memFlags += " | (machInst.legacy.addr ? " + \
"(AddrSizeFlagBit << FlagShift) : 0)"
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock
def getAllocator(self, microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(scale)s, %(index)s, %(base)s,
%(disp)s, %(segment)s, %(data)s,
%(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {

20
src/arch/x86/isa/microops/limmop.isa
View file

@ -69,8 +69,8 @@ def template MicroLimmOpDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize);
uint64_t setFlags, InstRegIndex _dest,
uint64_t _imm, uint8_t _dataSize);
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
@ -105,19 +105,17 @@ def template MicroLimmOpConstructor {{
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false, %(op_class)s),
%(base_class)s(machInst, "%(mnemonic)s", instMnem, 0, %(op_class)s),
dest(_dest.idx), imm(_imm), dataSize(_dataSize)
{
buildMe();
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast, %(op_class)s),
setFlags, %(op_class)s),
dest(_dest.idx), imm(_imm), dataSize(_dataSize)
{
buildMe();
@ -135,8 +133,8 @@ let {{
self.imm = imm
self.dataSize = dataSize
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock
def getAllocator(self, microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(dest)s, %(imm)s, %(dataSize)s)''' % {
"class_name" : self.className,
"mnemonic" : self.mnemonic,
@ -159,8 +157,8 @@ let {{
self.imm = imm
self.dataSize = dataSize
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock
def getAllocator(self, microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(dest)s, %(imm)s, %(dataSize)s)''' % {
"class_name" : self.className,
"mnemonic" : self.mnemonic,

28
src/arch/x86/isa/microops/mediaop.isa
View file

@ -54,8 +54,7 @@ def template MediaOpRegDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext);
@ -77,8 +76,7 @@ def template MediaOpImmDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext);
@ -102,8 +100,7 @@ def template MediaOpRegConstructor {{
ExtMachInst machInst, const char * instMnem,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, 0,
_src1, _src2, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
@ -111,12 +108,10 @@ def template MediaOpRegConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_src1, _src2, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
@ -135,8 +130,7 @@ def template MediaOpImmConstructor {{
ExtMachInst machInst, const char * instMnem,
InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, 0,
_src1, _imm8, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
@ -144,12 +138,10 @@ def template MediaOpImmConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_src1, _imm8, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
@ -272,11 +264,11 @@ let {{
else:
self.ext = ext
def getAllocator(self, *microFlags):
def getAllocator(self, microFlags):
className = self.className
if self.mnemonic == self.base_mnemonic + 'i':
className += "Imm"
allocator = '''new %(class_name)s(machInst, macrocodeBlock
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(src1)s, %(op2)s, %(dest)s,
%(srcSize)s, %(destSize)s, %(ext)s)''' % {
"class_name" : className,

28
src/arch/x86/isa/microops/regop.isa
View file

@ -106,8 +106,7 @@ def template MicroRegOpDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext);
@ -129,8 +128,7 @@ def template MicroRegOpImmDeclare {{
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext);
@ -154,8 +152,7 @@ def template MicroRegOpConstructor {{
ExtMachInst machInst, const char * instMnem,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, 0,
_src1, _src2, _dest, _dataSize, _ext,
%(op_class)s)
{
@ -163,12 +160,10 @@ def template MicroRegOpConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_src1, _src2, _dest, _dataSize, _ext,
%(op_class)s)
{
@ -187,8 +182,7 @@ def template MicroRegOpImmConstructor {{
ExtMachInst machInst, const char * instMnem,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
false, false, false, false,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, 0,
_src1, _imm8, _dest, _dataSize, _ext,
%(op_class)s)
{
@ -196,12 +190,10 @@ def template MicroRegOpImmConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
uint8_t _dataSize, uint16_t _ext) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast,
%(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
_src1, _imm8, _dest, _dataSize, _ext,
%(op_class)s)
{
@ -421,11 +413,11 @@ let {{
self.ext = " | ".join(flags)
self.className += "Flags"
def getAllocator(self, *microFlags):
def getAllocator(self, microFlags):
className = self.className
if self.mnemonic == self.base_mnemonic + 'i':
className += "Imm"
allocator = '''new %(class_name)s(machInst, macrocodeBlock
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(src1)s, %(op2)s, %(dest)s,
%(dataSize)s, %(ext)s)''' % {
"class_name" : className,

48
src/arch/x86/isa/microops/seqop.isa
View file

@ -44,8 +44,7 @@ output header {{
public:
SeqOpBase(ExtMachInst _machInst, const char * instMnem,
const char * mnemonic,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
const char * mnemonic, uint64_t setFlags,
uint16_t _target, uint8_t _cc);
SeqOpBase(ExtMachInst _machInst, const char * instMnem,
@ -64,8 +63,7 @@ def template SeqOpDeclare {{
void buildMe();
public:
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
uint16_t _target, uint8_t _cc);
uint64_t setFlags, uint16_t _target, uint8_t _cc);
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
uint16_t _target, uint8_t _cc);
@ -94,18 +92,15 @@ output decoder {{
inline SeqOpBase::SeqOpBase(
ExtMachInst machInst, const char * mnemonic, const char * instMnem,
uint16_t _target, uint8_t _cc) :
X86MicroopBase(machInst, mnemonic, instMnem,
false, false, false, false, No_OpClass),
X86MicroopBase(machInst, mnemonic, instMnem, 0, No_OpClass),
target(_target), cc(_cc)
{
}
inline SeqOpBase::SeqOpBase(
ExtMachInst machInst, const char * mnemonic, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
uint16_t _target, uint8_t _cc) :
X86MicroopBase(machInst, mnemonic, instMnem,
isMicro, isDelayed, isFirst, isLast, No_OpClass),
uint64_t setFlags, uint16_t _target, uint8_t _cc) :
X86MicroopBase(machInst, mnemonic, instMnem, setFlags, No_OpClass),
target(_target), cc(_cc)
{
}
@ -128,10 +123,9 @@ def template SeqOpConstructor {{
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
uint16_t _target, uint8_t _cc) :
uint64_t setFlags, uint16_t _target, uint8_t _cc) :
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
isMicro, isDelayed, isFirst, isLast, _target, _cc)
setFlags, _target, _cc)
{
buildMe();
}
@ -162,8 +156,8 @@ let {{
else:
self.cond = "0"
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock
def getAllocator(self, microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(target)s, %(cc)s)''' % {
"class_name" : self.className,
"flags" : self.microFlagsText(microFlags),
@ -174,12 +168,12 @@ let {{
class Br(SeqOp):
className = "MicroBranch"
def getAllocator(self, *microFlags):
(is_micro, is_delayed, is_first, is_last) = microFlags
is_last = False
is_delayed = True
microFlags = (is_micro, is_delayed, is_first, is_last)
return super(Br, self).getAllocator(*microFlags)
def getAllocator(self, microFlags):
if "IsLastMicroop" in microFlags:
microFlags.remove("IsLastMicroop")
if not "IsDelayedCommit" in microFlags:
microFlags.append("IsDelayedCommit")
return super(Br, self).getAllocator(microFlags)
class Eret(SeqOp):
target = "normalMicroPC(0)"
@ -194,12 +188,12 @@ let {{
else:
self.cond = "0"
def getAllocator(self, *microFlags):
(is_micro, is_delayed, is_first, is_last) = microFlags
is_last = True
is_delayed = False
microFlags = (is_micro, is_delayed, is_first, is_last)
return super(Eret, self).getAllocator(*microFlags)
def getAllocator(self, microFlags):
if not "IsLastMicroop" in microFlags:
microFlags.append("IsLastMicroop")
if "IsDelayedCommit" in microFlags:
microFlags.remove("IsDelayedCommit")
return super(Eret, self).getAllocator(microFlags)
iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
{"code": "nuIP = target",

37
src/arch/x86/isa/microops/specop.isa
View file

@ -50,8 +50,7 @@ output header {{
public:
MicroFaultBase(ExtMachInst _machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
Fault _fault, uint8_t _cc);
uint64_t setFlags, Fault _fault, uint8_t _cc);
MicroFaultBase(ExtMachInst _machInst, const char * instMnem,
Fault _fault, uint8_t _cc);
@ -64,15 +63,13 @@ output header {{
{
public:
MicroHalt(ExtMachInst _machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast) :
X86MicroopBase(_machInst, "halt", instMnem,
isMicro, isDelayed, isFirst, isLast, No_OpClass)
uint64_t setFlags) :
X86MicroopBase(_machInst, "halt", instMnem, setFlags, No_OpClass)
{
}
MicroHalt(ExtMachInst _machInst, const char * instMnem) :
X86MicroopBase(_machInst, "halt", instMnem,
false, false, false, false, No_OpClass)
X86MicroopBase(_machInst, "halt", instMnem, 0, No_OpClass)
{
}
@ -90,8 +87,7 @@ def template MicroFaultDeclare {{
void buildMe();
public:
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
Fault _fault, uint8_t _cc);
uint64_t setFlags, Fault _fault, uint8_t _cc);
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
Fault _fault, uint8_t _cc);
@ -129,18 +125,15 @@ output decoder {{
inline MicroFaultBase::MicroFaultBase(
ExtMachInst machInst, const char * instMnem,
Fault _fault, uint8_t _cc) :
X86MicroopBase(machInst, "fault", instMnem,
false, false, false, false, No_OpClass),
X86MicroopBase(machInst, "fault", instMnem, 0, No_OpClass),
fault(_fault), cc(_cc)
{
}
inline MicroFaultBase::MicroFaultBase(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
Fault _fault, uint8_t _cc) :
X86MicroopBase(machInst, "fault", instMnem,
isMicro, isDelayed, isFirst, isLast, No_OpClass),
uint64_t setFlags, Fault _fault, uint8_t _cc) :
X86MicroopBase(machInst, "fault", instMnem, setFlags, No_OpClass),
fault(_fault), cc(_cc)
{
}
@ -162,11 +155,9 @@ def template MicroFaultConstructor {{
}
inline %(class_name)s::%(class_name)s(
ExtMachInst machInst, const char * instMnem,
bool isMicro, bool isDelayed, bool isFirst, bool isLast,
ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
Fault _fault, uint8_t _cc) :
%(base_class)s(machInst, instMnem,
isMicro, isDelayed, isFirst, isLast, _fault, _cc)
%(base_class)s(machInst, instMnem, setFlags, _fault, _cc)
{
buildMe();
}
@ -211,8 +202,8 @@ let {{
else:
self.cond = "0"
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock
def getAllocator(self, microFlags):
allocator = '''new %(class_name)s(machInst, macrocodeBlock,
%(flags)s, %(fault)s, %(cc)s)''' % {
"class_name" : self.className,
"flags" : self.microFlagsText(microFlags),
@ -239,8 +230,8 @@ let {{
def __init__(self):
pass
def getAllocator(self, *microFlags):
return "new MicroHalt(machInst, macrocodeBlock %s)" % \
def getAllocator(self, microFlags):
return "new MicroHalt(machInst, macrocodeBlock, %s)" % \
self.microFlagsText(microFlags)
microopClasses["halt"] = Halt