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ARM: Clean up flattening for SPSR adding

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This commit is contained in:
Min Kyu Jeong 2010-08-23 11:18:41 -05:00
parent a02d82f9f8
commit d2fac84b95
2 changed files with 63 additions and 54 deletions
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77
src/arch/arm/isa.cc
View file

@ -157,28 +157,17 @@ MiscReg
ISA::readMiscRegNoEffect(int misc_reg)
{
assert(misc_reg < NumMiscRegs);
if (misc_reg == MISCREG_SPSR) {
CPSR cpsr = miscRegs[MISCREG_CPSR];
switch (cpsr.mode) {
case MODE_USER:
return miscRegs[MISCREG_SPSR];
case MODE_FIQ:
return miscRegs[MISCREG_SPSR_FIQ];
case MODE_IRQ:
return miscRegs[MISCREG_SPSR_IRQ];
case MODE_SVC:
return miscRegs[MISCREG_SPSR_SVC];
case MODE_MON:
return miscRegs[MISCREG_SPSR_MON];
case MODE_ABORT:
return miscRegs[MISCREG_SPSR_ABT];
case MODE_UNDEFINED:
return miscRegs[MISCREG_SPSR_UND];
default:
return miscRegs[MISCREG_SPSR];
}
}
return miscRegs[misc_reg];
int flat_idx;
if (misc_reg == MISCREG_SPSR)
flat_idx = flattenMiscIndex(misc_reg);
else
flat_idx = misc_reg;
MiscReg val = miscRegs[flat_idx];
DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n",
misc_reg, flat_idx, val);
return val;
}
@ -237,36 +226,16 @@ void
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
assert(misc_reg < NumMiscRegs);
if (misc_reg == MISCREG_SPSR) {
CPSR cpsr = miscRegs[MISCREG_CPSR];
switch (cpsr.mode) {
case MODE_USER:
miscRegs[MISCREG_SPSR] = val;
return;
case MODE_FIQ:
miscRegs[MISCREG_SPSR_FIQ] = val;
return;
case MODE_IRQ:
miscRegs[MISCREG_SPSR_IRQ] = val;
return;
case MODE_SVC:
miscRegs[MISCREG_SPSR_SVC] = val;
return;
case MODE_MON:
miscRegs[MISCREG_SPSR_MON] = val;
return;
case MODE_ABORT:
miscRegs[MISCREG_SPSR_ABT] = val;
return;
case MODE_UNDEFINED:
miscRegs[MISCREG_SPSR_UND] = val;
return;
default:
miscRegs[MISCREG_SPSR] = val;
return;
}
}
miscRegs[misc_reg] = val;
int flat_idx;
if (misc_reg == MISCREG_SPSR)
flat_idx = flattenMiscIndex(misc_reg);
else
flat_idx = misc_reg;
miscRegs[flat_idx] = val;
DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg,
flat_idx, val);
}
void
@ -276,8 +245,8 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
if (misc_reg == MISCREG_CPSR) {
updateRegMap(val);
CPSR cpsr = val;
DPRINTF(Arm, "Updating CPSR to %#x f:%d i:%d a:%d mode:%#x\n",
cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
Addr npc = tc->readNextPC() & ~PcModeMask;
if (cpsr.j)
npc = npc | (ULL(1) << PcJBitShift);

40
src/arch/arm/isa.hh
View file

@ -137,6 +137,46 @@ namespace ArmISA
return reg;
}
int
flattenMiscIndex(int reg)
{
if (reg == MISCREG_SPSR) {
int spsr_idx = NUM_MISCREGS;
CPSR cpsr = miscRegs[MISCREG_CPSR];
switch (cpsr.mode) {
case MODE_USER:
warn("User mode does not have SPSR\n");
spsr_idx = MISCREG_SPSR;
break;
case MODE_FIQ:
spsr_idx = MISCREG_SPSR_FIQ;
break;
case MODE_IRQ:
spsr_idx = MISCREG_SPSR_IRQ;
break;
case MODE_SVC:
spsr_idx = MISCREG_SPSR_SVC;
break;
case MODE_MON:
spsr_idx = MISCREG_SPSR_MON;
break;
case MODE_ABORT:
spsr_idx = MISCREG_SPSR_ABT;
break;
case MODE_UNDEFINED:
spsr_idx = MISCREG_SPSR_UND;
break;
default:
warn("Trying to access SPSR in an invalid mode: %d\n",
cpsr.mode);
spsr_idx = MISCREG_SPSR;
break;
}
return spsr_idx;
}
return reg;
}
void serialize(EventManager *em, std::ostream &os)
{}
void unserialize(EventManager *em, Checkpoint *cp,