Andreas Hansson
b006ad26d4
stats: Update stats to reflect cache changes
...
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
2016-04-21 04:48:24 -04:00
Andreas Hansson
d9193d1b20
stats: Match current behaviour
...
Small changes to the branch predictor and BTB caused stats changes
throughout.
2016-04-09 12:13:40 -04:00
Andreas Hansson
28289e5995
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 04:16:59 -05:00
Andreas Hansson
c6cede244b
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 04:08:27 -05:00
Andreas Sandberg
bbcbe028fe
stats: Update to reflect changes to PCI handling
2015-12-05 00:11:25 +00:00
Andreas Sandberg
5a249e03a4
stats: Update to reflect changes to RealView platform code
2015-12-04 00:19:05 +00:00
Nilay Vaish
e1385784f2
stats: remove wb_penalized and wb_penalized_rate
2015-11-16 04:58:29 -06:00
Andreas Hansson
324bc9771d
stats: Update stats to match cache changes
2015-11-06 03:26:50 -05:00
Joel Hestness
735c4a8766
stats: Update for UDelayEvent quiesce change
2015-10-10 16:45:41 -05:00
Andreas Hansson
806e1fbf0f
stats: Update stats to reflect snoop-filter changes
2015-09-25 07:27:03 -04:00
Nilay Vaish
0d6a6dfd7b
stats: updates due to recent changesets including d0934b57735a
2015-09-15 08:14:09 -05:00
Andreas Sandberg
023f6eb0f2
stats: Update ARM stats to include programmable oscillators
2015-08-07 15:39:17 +01:00
Andreas Hansson
25e1b1c1f5
stats: Update stats for cache, crossbar and DRAM changes
...
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00
Andreas Hansson
a22c29b263
arm, stats: Update stats to reflect reduction in misc reg reads
2015-05-26 03:21:44 -04:00
Andreas Hansson
80cd107e51
stats: Update stats to reflect cache changes
2015-05-05 03:22:39 -04:00
Steve Reinhardt
0cf36d9409
stats: update for previous changeset
...
Very small differences in IQ-specific O3 stats.
2015-04-22 20:22:29 -07:00
Nilay Vaish
99fb8f8140
stats: changes to due to recent set of patches
2015-03-09 09:39:09 -05:00
Andreas Hansson
8909843a76
stats: Update stats to reflect cache and interconnect changes
...
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 05:04:20 -05:00
Andreas Hansson
df8df4fd0a
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
...
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00
Andreas Hansson
6489598fb4
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 06:08:25 -05:00
Ali Saidi
29cd50e14e
arm, tests: Add 64-bit ARM regression tests
2014-10-29 23:50:15 -05:00
