I steped on while doing it
console/console.c:
Allocate more HWRPB pages so we have room for 64 percpu_rpbs
Fix writing of Console Relocation Block virtual addresses so that
if they are outside of the first page, which they will be with more
than 8 processors, the correct adress is written
palcode/Makefile:
Update makefile for tsunami with 64 processors
palcode/platform_m5.S:
Add support for tsunami with 64 processors
console/console.c:
Remove Printed SimOS references and replace with M5
Rework the SMP stuff, so we don't trash any stacks, or what we
thought were stacks, but are actually other ppls memory.
console/dbmentry.s:
add a carefully crafted piece of assembly that doesn't use the stack,
so we don't clobber anthing in the time between when we are spinning
and when the OS tells us to go.
palcode/platform_m5.s:
add/fix code for IPI, multiprocessor interrupts (DIR), and initial
bootstrapping of the cpu
addresses so the uncachable bit is set for tsunami.
console/Makefile:
console/console.c:
changed to generate tlaser and tsunami console code at different addresses
measure. The rest of the registers I used are touched by the tlaser
platform code so I would guess their are fair game.
Random memory troubles hopefully over.
console/Makefile:
palcode/Makefile:
moved header files to /h so updated make file for that
console/dbmentry.s:
console/paljtokern.s:
console/paljtoslave.s:
upadated to use osf file that the palcode uses, one less file
console/Makefile:
Updated to build on linux and removed
lots of crud that compiled, disassembled, and then reassembled
console/dbmentry.s:
the assembler didn't like they comments, so I removed them
console/printf.c:
Gcc was very unhappy, so I fixed this line
h/lib.h:
time_t is defined in a std header, and this was causing some problems
deleted and then upon realizing we needed them undeleted a bunch of
header files in the palcode dir
console/Makefile:
fixed so it will work with tru64... still haven't got the console to build under linux
palcode/platform_m5.s:
fixed code to "fake" srm console interrupt handling correctly
include serial interrupts
console/console.c:
0 the system type, let m5 overwrite
palcode/platform_m5.s:
add some comments and make the timer interrupt actually care what CPU it happened on
makefile to that end. Additionally made a change in console to
preserve t7 on call back because linux uses it for the "current"
pointer.
console/Makefile:
Changed makefile back to using gcc and gas rather then trying to
cross-compile for now
console/console.c:
Put code in to save t7 on CallBackFixup() call and changed the
system type to Tsunami
palcode/Makefile:
updated palcode makefile to have targets for tlaser and tsunami
Most of the changes were to fix broken macros in platfrom_tlaser.s
palcode/Makefile:
Completly new makefile to build palcode
palcode/ev5_alpha_defs.h:
fixed a broken define
palcode/ev5_impure.h:
macro fixes
palcode/platform_srcmax.s:
manual macro expansion of broken macros... this file isn't needed to
build tlaser palcode
palcode/platform_tlaser.s:
lots of fixups to make the code assemble
Add support for some thigns that M5 needs
Make this better support Tru64 v5.1
console/Makefile:
I couldn't figure out the old build system since I was missing
a bunch of tools at the time, so I kinda rewrote it.
console/console.c:
Get the includes right, and make things compile
little bit of cleanup along the way
console/paljtokern.s:
formatting junk
console/printf.c:
Formatting
get const right
h/lib.h:
fiddle with the includes that we need
console/console.c:
Get the BOOTDEVICE_NAME right
Add a bit of support for grabbing console environment variables
The TBE pointer in the MESI CMP implementation was not being set to NULL
when the TBE is deallocated. This resulted in segmentation fault on testing
the protocol when the ProtocolTrace was switched on.
JMP_FAR_I was unpacking its far pointer operand using sll instead of srl like
it should, and also putting the components in the wrong registers for use by
other microcode.
During iret access LDT/GDT at CPL0 rather than after transition to user mode
(if I'm reading the Intel IA-64 architecture spec correctly, the contents of
the descriptor table are read before the CPL is updated).
The code for Orion 2.0 makes use of printf() at several places where there as
an error in configuration of the model. These have been replaced with fatal().
This way things that don't care about work count options and/or aren't called
by something that has those command line options set up doesn't have to build
a fake object to carry in inert values.
By stalling and waiting the mandatory queue instead of recycling it, one can
ensure that no incoming messages are starved when the mandatory queue puts
signficant of pressure on the L1 cache controller (i.e. the ruby memtester).
--HG--
rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
