Makefile cleanup, no seperate middle preprocessing steps anymore
This commit is contained in:
Ali Saidi
parent
8d148125f2
commit
66b80038ed
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@ -1,9 +1,5 @@
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DBMENTRY = fffffc0000010000
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INCLUDES = -I$(PALCODE) -I$(INCLUDEH) -I$(M5)/dev
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SOURDIR = ./
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PALCODE = ../palcode
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INCLUDEH = ../h
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CFLAGS=-I . -I ../h -I$(M5)/dev -nostdinc++ -Wa,-m21164
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ARCHNAME=$(shell uname -m)
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@ -11,10 +7,13 @@ ARCHNAME=$(shell uname -m)
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ifneq ($(ARCHNAME), alpha)
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CC=alpha-unknown-linux-gnu-gcc
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AS=alpha-unknown-linux-gnu-as
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CXX=alpha-unknown-linux-gnu-g++
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LD=alpha-unknown-linux-gnu-ld
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endif
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OBJS=dbmentry.o printf.o paljtokern.o paljtoslave.o
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TLOBJS+=$(OBJS) console_tl.o
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TSOBJS+=$(OBJS) console_ts.o
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### Make sure that the M5 variable is set ###
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ifndef M5
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$(error The M5 variable must be set)
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@ -22,37 +21,26 @@ endif
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all: console_tl console_ts
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dbmentry.o: dbmentry.s
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g++ -I ../h -I ../palcode -E -P -nostdinc -nostdinc++ -x c++ dbmentry.s | \
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$(AS) -m 21164 -o dbmentry.s.o
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%.o: %.S
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$(CC) $(CFLAGS) -nostdinc -o $@ -c $<
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console_ts.o: console.c
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$(CC) -g3 $(INCLUDES) -D _TIME_T -D TSUNAMI -nostdinc++ -o console_ts.o -c console.c
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$(CC) -g3 $(CFLAGS) -D _TIME_T -D TSUNAMI -o $@ -c $<
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console_tl.o: console.c
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$(CC) -g3 $(INCLUDES) -D _TIME_T -D TLASER -nostdinc++ -o console_tl.o -c console.c
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$(CC) -g3 $(CFLAGS) -D _TIME_T -D TLASER -o $@ -c $<
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printf.o: printf.c
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$(CC) -g3 $(INCLUDES) -nostdinc++ -o $*.o -c $*.c
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$(CC) -g3 $(CFLAGS) -o $@ -c $<
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paljtokern.s.o: paljtokern.s
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g++ -I ../h -E -P -nostdinc -nostdinc++ -x c++ paljtokern.s | \
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$(AS) -m 21164 -o paljtokern.s.o
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console_ts: $(TSOBJS)
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$(LD) -o console_ts -N -Ttext $(DBMENTRY) -non_shared $(TSOBJS) -lc
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paljtoslave.s.o: paljtoslave.s
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g++ -I ../h -E -P -nostdinc -nostdinc++ -x c++ paljtoslave.s | \
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$(AS) -m 21164 -o paljtoslave.s.o
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console_ts: console_ts.o dbmentry.o printf.o paljtokern.s.o paljtoslave.s.o
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$(LD) -o console_ts -N -Ttext $(DBMENTRY) -non_shared \
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dbmentry.s.o console_ts.o printf.o paljtokern.s.o paljtoslave.s.o -lc
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console_tl: console_tl.o dbmentry.o printf.o paljtokern.s.o paljtoslave.s.o
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$(LD) -o console_tl -N -Ttext $(DBMENTRY) -non_shared \
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dbmentry.s.o console_tl.o printf.o paljtokern.s.o paljtoslave.s.o -lc
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console_tl: $(TLOBJS)
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$(LD) -o console_tl -N -Ttext $(DBMENTRY) -non_shared $(TLOBJS) -lc
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install: console
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scp console zizzer.eecs.umich.edu:/z/m5/system/testing/binaries/console
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clean:
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rm -f *.o console *.strip paljtokern.c paljtoslave.c
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rm -f *.o console_t?
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242
system/alpha/console/dbmentry.S
Normal file
242
system/alpha/console/dbmentry.S
Normal file
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@ -0,0 +1,242 @@
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/* taken from ebfw/rom/dbmentry.s */
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#define EB164
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/*#ifndef LINT
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.data
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.asciiz "$Id: dbmentry.s,v 1.1.1.1 1997/10/30 23:27:12 verghese Exp $"
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.text
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#endif
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*/
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/*
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* Debug Monitor Entry code
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*/
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#ifndef MAKEDEPEND
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#include "ev5_impure.h"
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#include "cserve.h"
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#include "fromHudsonOsf.h"
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#endif
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//#include "paldefs.h"
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#include "regdefs.h"
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#include "eb164.h"
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//#include "ledcodes.h"
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.text
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/* return address and padding to octaword align */
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#define STARTFRM 16
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.globl __start
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.ent __start, 0
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__start:
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_entry:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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#ifdef original_xxm
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lda a2, CSERVE_K_RD_IMPURE
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call_pal PAL_CSERVE_ENTRY
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lda v0, CNS_Q_BASE(v0)
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# Add KSEG offset to the impure area
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subq zero, 1, t0
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sll t0, 42, t0
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addq t0, v0, v0
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lda t0, CNS_Q_SIGNATURE(v0)
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bic t0, 0x07, t0 # Clear bottom 3 bits to avoid
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# allignment errors if the
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# impure area is total rubbish
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ldq t0, 0x00(t0)
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srl t0, 16, t0 # Shift signature into bottom 16 bits.
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lda t6, 0xDECB(zero) # Load the expected valid signature.
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zap t6, 0xFC, t6 # Clear the upper bits.
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cmpeq t0, t6, t0 # Is this a valid signature?
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beq t0, 1f # Not valid, don't trust input params.
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/*
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* Init the stack at the first 8K boundary
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* below the top of memory.
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*/
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lda t0, CNS_Q_MEM_SIZE(v0)
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ldq t0, 0x00(t0) # Load memory size.
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subq t0, 1, t0 # Last address in memory
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srl t0, 13, t0 # Align to first 8KB boundary
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sll t0, 13, sp # below the top of memory.
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br zero, 2f
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/*
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* If memory size was not passed in via the
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* PALcode impure data use the system specific
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* MINIMUM_SYSTEM_MEMORY definition.
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*/
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1:
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lda sp, (MINIMUM_SYSTEM_MEMORY&0xffff)(zero)
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ldah sp, ((MINIMUM_SYSTEM_MEMORY+0x8000)>>16)(sp)
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lda t0, (8*1024)(zero) # Allow for 8KB guard page.
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subq sp, t0, sp
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2:
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#endif /* original_xxm */
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/*
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* SimOS. Stack pointer is start of a valid phys or KSEG page
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*/
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bis sp,sp,s0 /* save sp */
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slave: lda v0,(8*1024)(sp) /* end of page */
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subq zero, 1, t0
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sll t0, 42, t0
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bis t0, v0, sp
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#ifdef original_xxm
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# Add KSEG offset to the stack pointer
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subq zero, 1, t0
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sll t0, 42, t0
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addq t0, sp, sp
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#endif
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lda sp, -STARTFRM(sp) # Create a stack frame
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stq ra, 0(sp) # Place return address on the stack
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.mask 0x84000000, -8
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.frame sp, STARTFRM, ra
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/*
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* Enable the Floating Point Unit
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*/
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lda a0, 1(zero)
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call_pal PAL_WRFEN_ENTRY
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/*
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* Every good C program has a main()
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*/
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beq s0,master
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call_pal PAL_WHAMI_ENTRY
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bis v0,v0,a0
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jsr ra, SlaveLoop
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master:
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jsr ra, main
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/*
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* The Debug Monitor should never return.
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* However, just incase...
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*/
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ldgp gp, 0(ra)
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bsr zero, _exit
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.end __start
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.globl _exit
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.ent _exit, 0
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_exit:
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ldq ra, 0(sp) # restore return address
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lda sp, STARTFRM(sp) # prune back the stack
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ret zero, (ra) # Back from whence we came
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.end _exit
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.globl cServe
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.ent cServe 2
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cServe:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_CSERVE_ENTRY
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ret zero, (ra)
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.end cServe
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.globl wrfen
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.ent wrfen 2
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wrfen:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_WRFEN_ENTRY
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ret zero, (ra)
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.end wrfen
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.globl consoleCallback
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.ent consoleCallback 2
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consoleCallback:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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lda sp,-64(sp)
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stq ra,0(sp)
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jsr CallBackDispatcher
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ldq ra,0(sp)
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lda sp,64(sp)
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ret zero,(ra)
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.end consoleCallback
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.globl consoleFixup
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.ent consoleFixup 2
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consoleFixup:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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lda sp,-64(sp)
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stq ra,0(sp)
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jsr CallBackFixup
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ldq ra,0(sp)
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lda sp,64(sp)
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ret zero,(ra)
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.end consoleFixup
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.globl SpinLock
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.ent SpinLock 2
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SpinLock:
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1:
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ldq_l a1,0(a0) # interlock complete lock state
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subl ra,3,v0 # get calling addr[31:0] + 1
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blbs a1,2f # branch if lock is busy
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stq_c v0,0(a0) # attempt to acquire lock
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beq v0,2f # branch if lost atomicity
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mb # ensure memory coherence
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ret zero,(ra) # return to caller (v0 is 1)
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2:
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br zero,1b
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.end SpinLock
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.globl loadContext
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.ent loadContext 2
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loadContext:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_SWPCTX_ENTRY
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ret zero, (ra)
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.end loadContext
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.globl SlaveSpin # Very carefully spin wait
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.ent SlaveSpin 2 # and swap context without
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SlaveSpin: # using any stack space
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.option O1
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.frame sp, 0, ra
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mov a0, t0 # cpu number
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mov a1, t1 # cpu rpb pointer (virtual)
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mov a2, t2 # what to spin on
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test: ldl t3, 0(t2)
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beq t3, test
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zapnot t1,0x1f,a0 # make rpb physical
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call_pal PAL_SWPCTX_ENTRY # switch to pcb
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mov t0, a0 # setup args for SlaveCmd
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mov t1, a1
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jsr SlaveCmd # call SlaveCmd
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ret zero, (ra) # Should never be reached
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.end SlaveSpin
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@ -1,242 +0,0 @@
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/* taken from ebfw/rom/dbmentry.s */
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#define EB164
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/*#ifndef LINT
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.data
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.asciiz "$Id: dbmentry.s,v 1.1.1.1 1997/10/30 23:27:12 verghese Exp $"
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.text
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#endif
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*/
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/*
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* Debug Monitor Entry code
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*/
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#ifndef MAKEDEPEND
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#include "ev5_impure.h"
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#include "cserve.h"
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#include "fromHudsonOsf.h"
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#endif
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//#include "paldefs.h"
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#include "regdefs.h"
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#include "eb164.h"
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//#include "ledcodes.h"
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.text
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/* return address and padding to octaword align */
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#define STARTFRM 16
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.globl __start
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.ent __start, 0
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__start:
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_entry:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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#ifdef original_xxm
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lda a2, CSERVE_K_RD_IMPURE
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call_pal PAL_CSERVE_ENTRY
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lda v0, CNS_Q_BASE(v0)
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# Add KSEG offset to the impure area
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subq zero, 1, t0
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sll t0, 42, t0
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addq t0, v0, v0
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lda t0, CNS_Q_SIGNATURE(v0)
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bic t0, 0x07, t0 # Clear bottom 3 bits to avoid
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# allignment errors if the
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# impure area is total rubbish
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ldq t0, 0x00(t0)
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srl t0, 16, t0 # Shift signature into bottom 16 bits.
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lda t6, 0xDECB(zero) # Load the expected valid signature.
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zap t6, 0xFC, t6 # Clear the upper bits.
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cmpeq t0, t6, t0 # Is this a valid signature?
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beq t0, 1f # Not valid, don't trust input params.
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/*
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* Init the stack at the first 8K boundary
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* below the top of memory.
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*/
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lda t0, CNS_Q_MEM_SIZE(v0)
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ldq t0, 0x00(t0) # Load memory size.
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subq t0, 1, t0 # Last address in memory
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srl t0, 13, t0 # Align to first 8KB boundary
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sll t0, 13, sp # below the top of memory.
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br zero, 2f
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/*
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* If memory size was not passed in via the
|
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* PALcode impure data use the system specific
|
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* MINIMUM_SYSTEM_MEMORY definition.
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*/
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1:
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lda sp, (MINIMUM_SYSTEM_MEMORY&0xffff)(zero)
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ldah sp, ((MINIMUM_SYSTEM_MEMORY+0x8000)>>16)(sp)
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lda t0, (8*1024)(zero) # Allow for 8KB guard page.
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subq sp, t0, sp
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2:
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#endif /* original_xxm */
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/*
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* SimOS. Stack pointer is start of a valid phys or KSEG page
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*/
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bis sp,sp,s0 /* save sp */
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slave: lda v0,(8*1024)(sp) /* end of page */
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subq zero, 1, t0
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sll t0, 42, t0
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bis t0, v0, sp
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#ifdef original_xxm
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# Add KSEG offset to the stack pointer
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subq zero, 1, t0
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sll t0, 42, t0
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addq t0, sp, sp
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#endif
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lda sp, -STARTFRM(sp) # Create a stack frame
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stq ra, 0(sp) # Place return address on the stack
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.mask 0x84000000, -8
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.frame sp, STARTFRM, ra
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/*
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* Enable the Floating Point Unit
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*/
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lda a0, 1(zero)
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call_pal PAL_WRFEN_ENTRY
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/*
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* Every good C program has a main()
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*/
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beq s0,master
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call_pal PAL_WHAMI_ENTRY
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bis v0,v0,a0
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jsr ra, SlaveLoop
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master:
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jsr ra, main
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/*
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* The Debug Monitor should never return.
|
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* However, just incase...
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*/
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ldgp gp, 0(ra)
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bsr zero, _exit
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.end __start
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.globl _exit
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.ent _exit, 0
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_exit:
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ldq ra, 0(sp) # restore return address
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lda sp, STARTFRM(sp) # prune back the stack
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ret zero, (ra) # Back from whence we came
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.end _exit
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.globl cServe
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.ent cServe 2
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cServe:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_CSERVE_ENTRY
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ret zero, (ra)
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.end cServe
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.globl wrfen
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.ent wrfen 2
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wrfen:
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.option O1
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.frame sp, 0, ra
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call_pal PAL_WRFEN_ENTRY
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ret zero, (ra)
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.end wrfen
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.globl consoleCallback
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.ent consoleCallback 2
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consoleCallback:
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br t0, 2f # get the current PC
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2: ldgp gp, 0(t0) # init gp
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lda sp,-64(sp)
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stq ra,0(sp)
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jsr CallBackDispatcher
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ldq ra,0(sp)
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lda sp,64(sp)
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||||
ret zero,(ra)
|
||||
.end consoleCallback
|
||||
|
||||
|
||||
.globl consoleFixup
|
||||
.ent consoleFixup 2
|
||||
consoleFixup:
|
||||
br t0, 2f # get the current PC
|
||||
2: ldgp gp, 0(t0) # init gp
|
||||
lda sp,-64(sp)
|
||||
stq ra,0(sp)
|
||||
jsr CallBackFixup
|
||||
ldq ra,0(sp)
|
||||
lda sp,64(sp)
|
||||
ret zero,(ra)
|
||||
.end consoleFixup
|
||||
|
||||
|
||||
|
||||
.globl SpinLock
|
||||
.ent SpinLock 2
|
||||
SpinLock:
|
||||
1:
|
||||
ldq_l a1,0(a0) # interlock complete lock state
|
||||
subl ra,3,v0 # get calling addr[31:0] + 1
|
||||
blbs a1,2f # branch if lock is busy
|
||||
stq_c v0,0(a0) # attempt to acquire lock
|
||||
beq v0,2f # branch if lost atomicity
|
||||
mb # ensure memory coherence
|
||||
ret zero,(ra) # return to caller (v0 is 1)
|
||||
2:
|
||||
br zero,1b
|
||||
.end SpinLock
|
||||
|
||||
.globl loadContext
|
||||
.ent loadContext 2
|
||||
loadContext:
|
||||
.option O1
|
||||
.frame sp, 0, ra
|
||||
call_pal PAL_SWPCTX_ENTRY
|
||||
ret zero, (ra)
|
||||
.end loadContext
|
||||
|
||||
|
||||
.globl SlaveSpin # Very carefully spin wait
|
||||
.ent SlaveSpin 2 # and swap context without
|
||||
SlaveSpin: # using any stack space
|
||||
.option O1
|
||||
.frame sp, 0, ra
|
||||
mov a0, t0 # cpu number
|
||||
mov a1, t1 # cpu rpb pointer (virtual)
|
||||
mov a2, t2 # what to spin on
|
||||
|
||||
test: ldl t3, 0(t2)
|
||||
beq t3, test
|
||||
zapnot t1,0x1f,a0 # make rpb physical
|
||||
call_pal PAL_SWPCTX_ENTRY # switch to pcb
|
||||
mov t0, a0 # setup args for SlaveCmd
|
||||
mov t1, a1
|
||||
jsr SlaveCmd # call SlaveCmd
|
||||
ret zero, (ra) # Should never be reached
|
||||
.end SlaveSpin
|
||||
|
||||
|
||||
156
system/alpha/console/paljtokern.S
Normal file
156
system/alpha/console/paljtokern.S
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
|
||||
#include "ev5_defs.h"
|
||||
#include "fromHudsonOsf.h" // OSF/1 specific definitions
|
||||
#include "fromHudsonMacros.h" // Global macro definitions
|
||||
#include "ev5_impure.h" // Scratch & logout area data structures
|
||||
#include "platform.h" // Platform specific definitions
|
||||
|
||||
.global palJToKern
|
||||
.text 3
|
||||
palJToKern:
|
||||
/* Jump to kernel
|
||||
args:
|
||||
Kernel address - a0
|
||||
PCBB - a1
|
||||
First free PFN - a3?
|
||||
|
||||
Enable kseg addressing in ICSR
|
||||
Enable kseg addressing in MCSR
|
||||
Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
|
||||
Set PCBB -- pass pointer in arg
|
||||
Set PTBR -- get it out of PCB
|
||||
Set KSP -- get it out of PCB
|
||||
|
||||
Jump to kernel address
|
||||
|
||||
Kernel args-
|
||||
s0 first free PFN
|
||||
s1 ptbr
|
||||
s2 argc 0
|
||||
s3 argv NULL
|
||||
s5 osf_param (sysconfigtab) NULL
|
||||
*/
|
||||
|
||||
ALIGN_BRANCH
|
||||
|
||||
ldq_p a0, 0(zero)
|
||||
ldq_p a1, 8(zero)
|
||||
ldq_p a3, 16(zero)
|
||||
|
||||
#ifdef undef
|
||||
LDLI(t0,0x200000000) // 8GB, like the Mikasa
|
||||
LDLI(t0,0x40000000) // 1GB, like the SRM
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
#endif
|
||||
/* Point the Vptbr at 8GB */
|
||||
lda t0, 0x1(zero)
|
||||
sll t0, 33, t0
|
||||
|
||||
mtpr t0, mVptBr // Load Mbox copy
|
||||
mtpr t0, iVptBr // Load Ibox copy
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
/* Turn on superpage mapping in the mbox and icsr */
|
||||
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr t0, mcsr // Set the super page mode enable bit
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
lda t0, 0(zero)
|
||||
mtpr t0, dtbAsn
|
||||
mtpr t0, itbAsn
|
||||
|
||||
LDLI (t1,0x20000000)
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mfpr t0, icsr // Enable superpage mapping
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
bis t0, t1, t0
|
||||
mtpr t0, icsr
|
||||
|
||||
STALL // Required stall to update chip ...
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
|
||||
ldq_p s0, PCB_Q_PTBR(a1)
|
||||
sll s0, VA_S_OFF, s0 // Shift PTBR into position
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
ldq_p sp, PCB_Q_KSP(a1)
|
||||
|
||||
mtpr a0, excAddr // Load the dispatch address.
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
bis a3, zero, a0 // first free PFN
|
||||
ldq_p a1, PCB_Q_PTBR(a1) // ptbr
|
||||
ldq_p a2, 24(zero) // argc
|
||||
ldq_p a3, 32(zero) // argv
|
||||
ldq_p a4, 40(zero) // environ
|
||||
lda a5, 0(zero) // osf_param
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr zero, dtbIa // Flush all D-stream TB entries
|
||||
mtpr zero, itbIa // Flush all I-stream TB entries
|
||||
br zero, 2f
|
||||
|
||||
ALIGN_BLOCK
|
||||
|
||||
2: NOP
|
||||
mtpr zero, icFlush // Flush the icache.
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 1-10
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 11-20
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 21-30
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 31-40
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
|
||||
|
||||
NOP // Required NOPs ... 41-44
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
hw_rei_stall // Dispatch to kernel
|
||||
|
||||
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
|
||||
#include "ev5_defs.h"
|
||||
#include "fromHudsonOsf.h" // OSF/1 specific definitions
|
||||
#include "fromHudsonMacros.h" // Global macro definitions
|
||||
#include "ev5_impure.h" // Scratch & logout area data structures
|
||||
#include "platform.h" // Platform specific definitions
|
||||
|
||||
.global palJToKern
|
||||
.text 3
|
||||
palJToKern:
|
||||
/* Jump to kernel
|
||||
args:
|
||||
Kernel address - a0
|
||||
PCBB - a1
|
||||
First free PFN - a3?
|
||||
|
||||
Enable kseg addressing in ICSR
|
||||
Enable kseg addressing in MCSR
|
||||
Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
|
||||
Set PCBB -- pass pointer in arg
|
||||
Set PTBR -- get it out of PCB
|
||||
Set KSP -- get it out of PCB
|
||||
|
||||
Jump to kernel address
|
||||
|
||||
Kernel args-
|
||||
s0 first free PFN
|
||||
s1 ptbr
|
||||
s2 argc 0
|
||||
s3 argv NULL
|
||||
s5 osf_param (sysconfigtab) NULL
|
||||
*/
|
||||
|
||||
ALIGN_BRANCH
|
||||
|
||||
ldq_p a0, 0(zero)
|
||||
ldq_p a1, 8(zero)
|
||||
ldq_p a3, 16(zero)
|
||||
|
||||
#ifdef undef
|
||||
LDLI(t0,0x200000000) // 8GB, like the Mikasa
|
||||
LDLI(t0,0x40000000) // 1GB, like the SRM
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
#endif
|
||||
/* Point the Vptbr at 8GB */
|
||||
lda t0, 0x1(zero)
|
||||
sll t0, 33, t0
|
||||
|
||||
mtpr t0, mVptBr // Load Mbox copy
|
||||
mtpr t0, iVptBr // Load Ibox copy
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
/* Turn on superpage mapping in the mbox and icsr */
|
||||
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr t0, mcsr // Set the super page mode enable bit
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
lda t0, 0(zero)
|
||||
mtpr t0, dtbAsn
|
||||
mtpr t0, itbAsn
|
||||
|
||||
LDLI (t1,0x20000000)
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mfpr t0, icsr // Enable superpage mapping
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
bis t0, t1, t0
|
||||
mtpr t0, icsr
|
||||
|
||||
STALL // Required stall to update chip ...
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
|
||||
ldq_p s0, PCB_Q_PTBR(a1)
|
||||
sll s0, VA_S_OFF, s0 // Shift PTBR into position
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
ldq_p sp, PCB_Q_KSP(a1)
|
||||
|
||||
mtpr a0, excAddr // Load the dispatch address.
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
bis a3, zero, a0 // first free PFN
|
||||
ldq_p a1, PCB_Q_PTBR(a1) // ptbr
|
||||
ldq_p a2, 24(zero) // argc
|
||||
ldq_p a3, 32(zero) // argv
|
||||
ldq_p a4, 40(zero) // environ
|
||||
lda a5, 0(zero) // osf_param
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr zero, dtbIa // Flush all D-stream TB entries
|
||||
mtpr zero, itbIa // Flush all I-stream TB entries
|
||||
br zero, 2f
|
||||
|
||||
ALIGN_BLOCK
|
||||
|
||||
2: NOP
|
||||
mtpr zero, icFlush // Flush the icache.
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 1-10
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 11-20
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 21-30
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 31-40
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
|
||||
|
||||
NOP // Required NOPs ... 41-44
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
hw_rei_stall // Dispatch to kernel
|
||||
|
||||
|
||||
151
system/alpha/console/paljtoslave.S
Normal file
151
system/alpha/console/paljtoslave.S
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
|
||||
#include "ev5_defs.h"
|
||||
#include "fromHudsonOsf.h" // OSF/1 specific definitions
|
||||
#include "fromHudsonMacros.h" // Global macro definitions
|
||||
#include "ev5_impure.h" // Scratch & logout area data structures
|
||||
#include "platform.h" // Platform specific definitions
|
||||
|
||||
|
||||
.global palJToSlave
|
||||
.text 3
|
||||
|
||||
/*
|
||||
* args:
|
||||
a0: here
|
||||
a1: boot location
|
||||
a2: CSERVE_J_KTOPAL
|
||||
a3: restrart_pv
|
||||
a4: vptb
|
||||
a5: my_rpb
|
||||
|
||||
*/
|
||||
palJToSlave:
|
||||
|
||||
/*
|
||||
* SRM Console Architecture III 3-26
|
||||
*/
|
||||
|
||||
ALIGN_BRANCH
|
||||
|
||||
bis a3, zero, pv
|
||||
bis zero, zero, t11
|
||||
bis zero, zero, ra
|
||||
|
||||
/* Point the Vptbr to a2 */
|
||||
|
||||
mtpr a4, mVptBr // Load Mbox copy
|
||||
mtpr a4, iVptBr // Load Ibox copy
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
/* Turn on superpage mapping in the mbox and icsr */
|
||||
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr t0, mcsr // Set the super page mode enable bit
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
lda t0, 0(zero)
|
||||
mtpr t0, dtbAsn
|
||||
mtpr t0, itbAsn
|
||||
|
||||
LDLI (t1,0x20000000)
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mfpr t0, icsr // Enable superpage mapping
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
bis t0, t1, t0
|
||||
mtpr t0, icsr
|
||||
|
||||
STALL // Required stall to update chip ...
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
|
||||
ldq_p s0, PCB_Q_PTBR(a5)
|
||||
sll s0, VA_S_OFF, s0 // Shift PTBR into position
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
ldq_p sp, PCB_Q_KSP(a5)
|
||||
|
||||
//mtpr a0, excAddr // Load the dispatch address.
|
||||
//STALL // don't dual issue the load with mtpr -pb
|
||||
//bis a3, zero, a0 // first free PFN
|
||||
// ldq_p a1, PCB_Q_PTBR(a5) // ptbr
|
||||
|
||||
//ldq_p a2, 24(zero) // argc
|
||||
//ldq_p a3, 32(zero) // argv
|
||||
//ldq_p a4, 40(zero) // environ
|
||||
//lda a5, 0(zero) // osf_param
|
||||
//STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr zero, dtbIa // Flush all D-stream TB entries
|
||||
mtpr zero, itbIa // Flush all I-stream TB entries
|
||||
|
||||
|
||||
mtpr a1, excAddr // Load the dispatch address.
|
||||
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr zero, dtbIa // Flush all D-stream TB entries
|
||||
mtpr zero, itbIa // Flush all I-stream TB entries
|
||||
br zero, 2f
|
||||
|
||||
ALIGN_BLOCK
|
||||
|
||||
2: NOP
|
||||
mtpr zero, icFlush // Flush the icache.
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 1-10
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 11-20
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 21-30
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 31-40
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
|
||||
|
||||
NOP // Required NOPs ... 41-44
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
hw_rei_stall // Dispatch to kernel
|
||||
|
||||
|
|
@ -1,151 +0,0 @@
|
|||
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
|
||||
#include "ev5_defs.h"
|
||||
#include "fromHudsonOsf.h" // OSF/1 specific definitions
|
||||
#include "fromHudsonMacros.h" // Global macro definitions
|
||||
#include "ev5_impure.h" // Scratch & logout area data structures
|
||||
#include "platform.h" // Platform specific definitions
|
||||
|
||||
|
||||
.global palJToSlave
|
||||
.text 3
|
||||
|
||||
/*
|
||||
* args:
|
||||
a0: here
|
||||
a1: boot location
|
||||
a2: CSERVE_J_KTOPAL
|
||||
a3: restrart_pv
|
||||
a4: vptb
|
||||
a5: my_rpb
|
||||
|
||||
*/
|
||||
palJToSlave:
|
||||
|
||||
/*
|
||||
* SRM Console Architecture III 3-26
|
||||
*/
|
||||
|
||||
ALIGN_BRANCH
|
||||
|
||||
bis a3, zero, pv
|
||||
bis zero, zero, t11
|
||||
bis zero, zero, ra
|
||||
|
||||
/* Point the Vptbr to a2 */
|
||||
|
||||
mtpr a4, mVptBr // Load Mbox copy
|
||||
mtpr a4, iVptBr // Load Ibox copy
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
/* Turn on superpage mapping in the mbox and icsr */
|
||||
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr t0, mcsr // Set the super page mode enable bit
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
|
||||
lda t0, 0(zero)
|
||||
mtpr t0, dtbAsn
|
||||
mtpr t0, itbAsn
|
||||
|
||||
LDLI (t1,0x20000000)
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mfpr t0, icsr // Enable superpage mapping
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
bis t0, t1, t0
|
||||
mtpr t0, icsr
|
||||
|
||||
STALL // Required stall to update chip ...
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
STALL
|
||||
|
||||
ldq_p s0, PCB_Q_PTBR(a5)
|
||||
sll s0, VA_S_OFF, s0 // Shift PTBR into position
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
ldq_p sp, PCB_Q_KSP(a5)
|
||||
|
||||
//mtpr a0, excAddr // Load the dispatch address.
|
||||
//STALL // don't dual issue the load with mtpr -pb
|
||||
//bis a3, zero, a0 // first free PFN
|
||||
// ldq_p a1, PCB_Q_PTBR(a5) // ptbr
|
||||
|
||||
//ldq_p a2, 24(zero) // argc
|
||||
//ldq_p a3, 32(zero) // argv
|
||||
//ldq_p a4, 40(zero) // environ
|
||||
//lda a5, 0(zero) // osf_param
|
||||
//STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr zero, dtbIa // Flush all D-stream TB entries
|
||||
mtpr zero, itbIa // Flush all I-stream TB entries
|
||||
|
||||
|
||||
mtpr a1, excAddr // Load the dispatch address.
|
||||
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
STALL // don't dual issue the load with mtpr -pb
|
||||
mtpr zero, dtbIa // Flush all D-stream TB entries
|
||||
mtpr zero, itbIa // Flush all I-stream TB entries
|
||||
br zero, 2f
|
||||
|
||||
ALIGN_BLOCK
|
||||
|
||||
2: NOP
|
||||
mtpr zero, icFlush // Flush the icache.
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 1-10
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 11-20
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 21-30
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
NOP // Required NOPs ... 31-40
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
|
||||
|
||||
NOP // Required NOPs ... 41-44
|
||||
NOP
|
||||
NOP
|
||||
NOP
|
||||
|
||||
hw_rei_stall // Dispatch to kernel
|
||||
|
||||
Loading…
Reference in a new issue