496c48d9b2
console/Makefile:
palcode/Makefile:
moved header files to /h so updated make file for that
console/dbmentry.s:
console/paljtokern.s:
console/paljtoslave.s:
upadated to use osf file that the palcode uses, one less file
156 lines
3.1 KiB
ArmAsm
156 lines
3.1 KiB
ArmAsm
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
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#include "ev5_defs.h"
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#include "fromHudsonOsf.h" // OSF/1 specific definitions
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#include "fromHudsonMacros.h" // Global macro definitions
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#include "ev5_impure.h" // Scratch & logout area data structures
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#include "platform.h" // Platform specific definitions
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.global palJToKern
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.text 3
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palJToKern:
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/* Jump to kernel
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args:
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Kernel address - a0
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PCBB - a1
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First free PFN - a3?
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Enable kseg addressing in ICSR
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Enable kseg addressing in MCSR
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Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
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Set PCBB -- pass pointer in arg
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Set PTBR -- get it out of PCB
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Set KSP -- get it out of PCB
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Jump to kernel address
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Kernel args-
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s0 first free PFN
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s1 ptbr
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s2 argc 0
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s3 argv NULL
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s5 osf_param (sysconfigtab) NULL
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*/
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ALIGN_BRANCH
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ldq_p a0, 0(zero)
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ldq_p a1, 8(zero)
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ldq_p a3, 16(zero)
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#ifdef undef
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LDLI(t0,0x200000000) // 8GB, like the Mikasa
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LDLI(t0,0x40000000) // 1GB, like the SRM
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STALL // don't dual issue the load with mtpr -pb
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#endif
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/* Point the Vptbr at 8GB */
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lda t0, 0x1(zero)
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sll t0, 33, t0
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mtpr t0, mVptBr // Load Mbox copy
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mtpr t0, iVptBr // Load Ibox copy
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STALL // don't dual issue the load with mtpr -pb
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/* Turn on superpage mapping in the mbox and icsr */
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lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
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STALL // don't dual issue the load with mtpr -pb
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mtpr t0, mcsr // Set the super page mode enable bit
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STALL // don't dual issue the load with mtpr -pb
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lda t0, 0(zero)
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mtpr t0, dtbAsn
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mtpr t0, itbAsn
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LDLI (t1,0x20000000)
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STALL // don't dual issue the load with mtpr -pb
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mfpr t0, icsr // Enable superpage mapping
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STALL // don't dual issue the load with mtpr -pb
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bis t0, t1, t0
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mtpr t0, icsr
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STALL // Required stall to update chip ...
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STALL
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STALL
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STALL
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STALL
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ldq_p s0, PCB_Q_PTBR(a1)
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sll s0, VA_S_OFF, s0 // Shift PTBR into position
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STALL // don't dual issue the load with mtpr -pb
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mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
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STALL // don't dual issue the load with mtpr -pb
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ldq_p sp, PCB_Q_KSP(a1)
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mtpr a0, excAddr // Load the dispatch address.
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STALL // don't dual issue the load with mtpr -pb
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bis a3, zero, a0 // first free PFN
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ldq_p a1, PCB_Q_PTBR(a1) // ptbr
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ldq_p a2, 24(zero) // argc
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ldq_p a3, 32(zero) // argv
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ldq_p a4, 40(zero) // environ
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lda a5, 0(zero) // osf_param
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STALL // don't dual issue the load with mtpr -pb
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mtpr zero, dtbIa // Flush all D-stream TB entries
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mtpr zero, itbIa // Flush all I-stream TB entries
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br zero, 2f
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ALIGN_BLOCK
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2: NOP
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mtpr zero, icFlush // Flush the icache.
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NOP
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NOP
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NOP // Required NOPs ... 1-10
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 11-20
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 21-30
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 31-40
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP // Required NOPs ... 41-44
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NOP
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NOP
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NOP
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hw_rei_stall // Dispatch to kernel
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