Add support for tsunami with 64 processors and fix some console bugs
I steped on while doing it
console/console.c:
Allocate more HWRPB pages so we have room for 64 percpu_rpbs
Fix writing of Console Relocation Block virtual addresses so that
if they are outside of the first page, which they will be with more
than 8 processors, the correct adress is written
palcode/Makefile:
Update makefile for tsunami with 64 processors
palcode/platform_m5.S:
Add support for tsunami with 64 processors
This commit is contained in:
Ali Saidi
parent
99a522fb8b
commit
5821f37cb6
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@ -58,7 +58,7 @@ typedef unsigned int uint32;
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/* Kernel write | kernel read | valid */
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#define KPTE(x) ((ul)((((ul)(x)) << 32) | 0x1101))
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#define HWRPB_PAGES 4
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#define HWRPB_PAGES 16
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#define MDT_BITMAP_PAGES 4
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#define CSERVE_K_JTOKERN 0x18
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@ -480,6 +480,7 @@ unixBoot(int go, int argc, char **argv)
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first[1] = KPTE(PFN(first)); /* Region 3 */
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second[SECOND(0x10000000)] = KPTE(PFN(third_rpb)); /* Region 0 */
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for (i=0;i<NUM_KERNEL_THIRD;i++) {
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second[SECOND(0x20000000)+i] = KPTE(PFN(third_kernel)+i); /* Region 1 */
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}
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@ -720,9 +721,10 @@ unixBoot(int go, int argc, char **argv)
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rpb_crb->rpb_map[0].rpb_pgcount = HWRPB_PAGES;
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printf_lock("Console Callback at 0x%x, fixup at 0x%x \n",
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printf_lock("Console Callback at 0x%x, fixup at 0x%x, crb offset: 0x%x\n",
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rpb_crb->rpb_va_disp,
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rpb_crb->rpb_va_fixup );
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rpb_crb->rpb_va_fixup,
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rpb->rpb_crb_off);
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rpb_mdt = (struct _xxm_rpb_mdt *) (((ul)rpb_crb) + sizeof(struct rpb_crb));
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rpb->rpb_mdt_off = (ul)rpb_mdt - (ul)rpb;
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@ -811,11 +813,7 @@ unixBoot(int go, int argc, char **argv)
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{
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ul *ptr = (ul*)((char*)rpb_dsr + sizeof(struct rpb_dsr ));
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rpb_crb->rpb_pa_disp = KSEG_TO_PHYS(ptr);
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#if 0
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rpb_crb->rpb_va_disp = 0x10000000 + ((ul)ptr&(0x2000*HWRPB_PAGES-1));
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#else
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rpb_crb->rpb_va_disp = 0x10000000 + ((ul)ptr & 0x1fff);
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#endif
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rpb_crb->rpb_va_disp = 0x10000000 + (((ul)ptr - (ul)rpb) & (0x2000*HWRPB_PAGES-1));
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printf_lock("ConsoleDispatch at virt %x phys %x val %x\n",
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rpb_crb->rpb_va_disp,
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rpb_crb->rpb_pa_disp,
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@ -823,12 +821,9 @@ unixBoot(int go, int argc, char **argv)
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*ptr++ = 0;
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*ptr++ = (ul) consoleCallback;
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rpb_crb->rpb_pa_fixup = KSEG_TO_PHYS(ptr);
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#if 0
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rpb_crb->rpb_va_fixup = 0x10000000 + ((ul)ptr& (0x2000*HWRPB_PAGES-1));
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#else
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rpb_crb->rpb_va_fixup = 0x10000000 + ((ul)ptr & 0x1fff);
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#endif
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rpb_crb->rpb_va_fixup = 0x10000000 + (((ul)ptr - (ul)rpb) & (0x2000*HWRPB_PAGES-1));
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*ptr++ = 0;
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*ptr++ = (ul) consoleFixup;
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}
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@ -1,21 +1,26 @@
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#Makefile for palcode
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#Works on alpha-linux and builds elf executable
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GAS = alpha-elf-as
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CC = alpha-elf-g++
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LD = alpha-elf-ld
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GAS = alpha-linux-as
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CC = alpha-linux-gcc
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LD = alpha-linux-ld
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CFLAGS=-I . -I ../h -D SIMOS -D BUILD_PALCODE -nostdinc -nostdinc++ -Wa,-m21164
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LDFLAGS=-Ttext 0x4000
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TLOBJS = osfpal.o platform_tlaser.o
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TLOBJS_COPY = osfpal_cache_copy.o osfpal_cache_copy_unaligned.o
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TSOBJS = osfpal.o platform_m5.o
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TSBOBJS = osfpal.o platform_m5b.o
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TSOBJS_COPY = osfpal_cache_copy.o osfpal_cache_copy_unaligned.o
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%.o: %.S
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$(CC) $(CFLAGS) -o $@ -c $<
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all: tlaser tsunami
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all: tsunami tsunami_b64
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platform_m5b.o: platform_m5.S
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$(CC) $(CFLAGS) -DBIG_TSUNAMI -o $@ -c $<
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tlaser: $(TLOBJS)
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$(LD) $(LDFLAGS) -o tl_osfpal osfpal.o platform_tlaser.o
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@ -27,10 +32,13 @@ tlaser_copy: $(TLOBJS_COPY) $(TLOBJS)
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tsunami: $(TSOBJS)
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$(LD) $(LDFLAGS) -o ts_osfpal osfpal.o platform_m5.o
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tsunami_b64: $(TSBOBJS)
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$(LD) $(LDFLAGS) -o tsb_osfpal osfpal.o platform_m5b.o
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tsunami_copy: $(TSOBJS) $(TSOBJS_COPY)
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$(LD) $(LDFLAGS) -o ts_osfpal_cache osfpal_cache_copy.o platform_m5.o
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$(LD) $(LDFLAGS) -o ts_osfpal_unalign osfpal_cache_copy_unaligned.o platform_m5.o
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clean:
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rm -f *.o tl_osfpal tl_osfpal_cache tl_osfpal_unalign ts_osfpal \
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ts_osfpal_cache ts_osfpal_unalign
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ts_osfpal_cache ts_osfpal_unalign tsb_osfpal
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@ -71,6 +71,26 @@
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#define osfpcb_q_Ksp pcb_q_ksp
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#define pal_impure_common_size ((0x200 + 7) & 0xfff8)
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#ifdef BIG_TSUNAMI
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#define MAXPROC 0x3f
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#define IPIQ_addr 0x800
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#define IPIQ_shift 0
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#define IPIR_addr 0x840
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#define IPIR_shift 0
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#define RTC_addr 0x880
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#define RTC_shift 0
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#define DIR_addr 0xa2
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#else
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#define MAXPROC 0x3
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#define IPIQ_addr 0x080
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#define IPIQ_shift 12
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#define IPIR_addr 0x080
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#define IPIR_shift 8
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#define RTC_addr 0x080
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#define RTC_shift 4
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#define DIR_addr 0xa0
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#endif
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#define ALIGN_BLOCK \
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.align 5
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@ -431,12 +451,10 @@ EXPORT(sys_wripir)
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//++
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// Convert the processor number to a CPU mask
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//--
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and r16,0x3, r14 // mask the top stuff (4 CPUs supported)
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and r16,MAXPROC, r14 // mask the top stuff (4 or 64 CPUs supported)
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bis r31,0x1,r16 // get a one
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sll r16,r14,r14 // shift the bit to the right place
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sll r14,12,r14
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sll r14,IPIQ_shift,r14
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//++
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// Build the Broadcast Space base address
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@ -446,7 +464,7 @@ EXPORT(sys_wripir)
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ldah r13,0xa0(r31)
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sll r13,8,r13
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bis r16,r13,r16
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lda r16,0x0080(r16)
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lda r16,IPIQ_addr(r16)
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//++
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// Send out the IP Intr
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@ -748,14 +766,14 @@ sys_int_23:
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sll r12,16,r12
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lda r12,0xa000(r12)
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sll r12,16,r12
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lda r12,0x080(r12)
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lda r12,IPIR_addr(r12)
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mfpr r10, pt_whami // get CPU ID
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extbl r10, 1, r10 // Isolate just whami bits
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or r31,0x1,r14 // load r14 with bit to clear
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sll r14,r10,r14 // left shift by CPU ID
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sll r14,8,r14
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stq_p r14, 0(r12) // clear the rtc interrupt
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sll r14,IPIR_shift,r14
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stq_p r14, 0(r12) // clear the ipi interrupt
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br r31, pal_post_interrupt // Notify the OS
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@ -767,12 +785,13 @@ sys_int_22:
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sll r12,16,r12
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lda r12,0xa000(r12)
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sll r12,16,r12
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lda r12,0x080(r12)
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lda r12,RTC_addr(r12)
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mfpr r10, pt_whami // get CPU ID
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extbl r10, 1, r10 // Isolate just whami bits
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or r31,0x10,r14 // load r14 with bit to clear
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or r31,0x1,r14 // load r14 with bit to clear
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sll r14,r10,r14 // left shift by CPU ID
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sll r14,RTC_shift,r14 // put the bits in the right position
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stq_p r14, 0(r12) // clear the rtc interrupt
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br r31, pal_post_interrupt // Tell the OS
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@ -810,15 +829,20 @@ sys_int_20:
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ALIGN_BRANCH
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sys_int_21:
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lda r12,0xf01(r31)
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lda r12,0xf01(r31) // calculate DIRn address
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sll r12,32,r12
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ldah r13,0xa0(r31)
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ldah r13,DIR_addr(r31)
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sll r13,8,r13
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bis r12,r13,r12
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lda r12,0x0080(r12)
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mfpr r13, pt_whami // get CPU ID
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extbl r13, 1, r13 // Isolate just whami bits
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#ifdef BIG_TSUNAMI
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sll r13,4,r13
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or r12,r13,r12
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#else
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lda r12,0x0080(r12)
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and r13,0x1,r14 // grab LSB and shift left 6
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sll r14,6,r14
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and r13,0x2,r10 // grabl LSB+1 and shift left 9
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@ -826,9 +850,11 @@ sys_int_21:
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mskbl r12,0,r12 // calculate DIRn address
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lda r13,0x280(r31)
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bis r12,r13,r12
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bis r12,r13,r12
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or r12,r14,r12
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or r12,r10,r12
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#endif
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ldqp r13, 0(r12) // read DIRn
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or r31,1,r14 // set bit 55 (ISA Interrupt)
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