Added ALPHA_ACCESS_BASE to get rid of machine_defs.h
This commit is contained in:
Ali Saidi
parent
0d184b3bc9
commit
120825c1e2
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@ -15,7 +15,6 @@ typedef unsigned int uint32;
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#define CONSOLE
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#include "alpha_access.h"
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#include "machine_defs.h"
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#if 0
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#include "new_aouthdr.h"
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@ -34,8 +33,7 @@ typedef unsigned int uint32;
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#define K1BASE 0xfffffc8000000000
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#define KSEG_TO_PHYS(x)(((ul)x) & ~KSEG)
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#define CDR ((volatile DevConsoleRegisters *) \
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(__MAGIC_ZONE(0, 0, MAGIC_ZONE_BDOOR_DEV) + __MAGIC_BDOOR_CNSLE_OFFS))
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#define ALPHA_ACCESS_BASE 0xfffffc8000a00000
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#define PHYS_TO_K1(_x) (K1BASE|(_x))
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@ -118,7 +116,7 @@ void InitConsole(void)
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char GetChar()
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{
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struct AlphaAccess *k1Conf = (struct AlphaAccess *)(__MAGIC_ZONE(0, 0, MAGIC_ZONE_EV5_ALIAS));
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struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
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return k1Conf->inputChar;
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}
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@ -130,7 +128,7 @@ void PutChar(char c)
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#if 0
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*(int*) PHYS_TO_K1(SLOT_D_COM1<<5) = c;
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#endif
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struct AlphaAccess *k1Conf = (struct AlphaAccess *)(__MAGIC_ZONE(0, 0, MAGIC_ZONE_EV5_ALIAS));
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struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
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k1Conf->outputChar = c;
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}
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@ -144,7 +142,7 @@ int
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main(int argc, char **argv)
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{
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int x,i;
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struct AlphaAccess *k1Conf = (struct AlphaAccess *)(__MAGIC_ZONE(0, 0, MAGIC_ZONE_EV5_ALIAS));
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struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
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ui *k1ptr,*ksegptr;
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@ -828,7 +826,7 @@ unixBoot(int go, int argc, char **argv)
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int i;
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for (i=1;i<simosConf.numCPUs;i++) {
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volatile struct AlphaAccess *k1Conf = (volatile struct AlphaAccess *)
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(__MAGIC_ZONE(0, 0, MAGIC_ZONE_EV5_ALIAS));
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(ALPHA_ACCESS_BASE);
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SpinLock(&theLock);
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printf("Bootstraping CPU %d with sp=0x%x \n",
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i,bootStrapImpure[i]);
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@ -970,7 +968,7 @@ void
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DeviceOperation(long op, long channel, long count, long address, long block)
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{
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struct AlphaAccess *k1Conf = (struct AlphaAccess *)
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(__MAGIC_ZONE(0, 0, MAGIC_ZONE_EV5_ALIAS));
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(ALPHA_ACCESS_BASE);
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long pAddr;
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@ -1,635 +0,0 @@
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/*
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* Copyright (C) 1998 by the Board of Trustees
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* of Leland Stanford Junior University.
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* Copyright (C) 1998 Digital Equipment Corporation
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*
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* This file is part of the SimOS distribution.
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* See LICENSE file for terms of the license.
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*
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*/
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/***********************************************************************
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machine_defs.h
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***********************************************************************/
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/*************************************************************************
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* *
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* Copyright (C) 1993-1996 Stanford University *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Stanford University, and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Stanford University. *
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* *
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*************************************************************************/
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#ifndef __DPGCC__
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#ifndef _HEADER_STACK_
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#define _HEADER_STACK_
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#endif
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#endif
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#ifndef _MACHINE_DEFS_H
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#define _MACHINE_DEFS_H
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/*
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* Created by: Dan Teodosiu, 07/96
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*
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* This header file defines the OS view of the MAGIC service address space
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* and of the device registers.
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*
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* The service address space addresses used by the OS are VIRTUAL addresses.
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* Depending on whether we simulate a 32 bit or a 64 bit processor,
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* the service address mappings will be different. MAGIC physical addresses
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* are 40 bits wide, so in 32 bit mode (current SimOS) we had to squeeze
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* the service address space into less address bits.
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*
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* There are two kinds of macros in this file:
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*
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* - MAGIC definitions, pertaining to the services offered by the
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* MAGIC node controller. All these macros start with MAGIC_...,
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* Those definitions are further subdivided into ones which do not
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* depend on the address mappings (such as MAGIC register numbers,
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* error codes, etc.), and ones which do (such as the macros that help
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* construct MAGIC PPR addresses).
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* The current simulated MAGIC only supports doubleword accesses.
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*
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* - devices register definitions, of the form DEV_... These defs
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* describe the various device registers. Devices are accessed by
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* performing uncached word (32bit) reads and writes to their registers.
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*
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* Notes:
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* The macro SIMOS64BIT selects the 64 bit version of those definitions;
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* by default, you get the 32 bit version. 64 bit is currently not
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* implemented.
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*
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* Related documents:
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* - FLASH: Physical Address Layout
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* - FLASH: PP Software Services
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* - SimOS to FLASH Physical Address Mapping
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*
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*/
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/***************************************************************************
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MAGIC defs which do not depend on the virtual -> physical address mapping
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***************************************************************************/
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/** zone numbering for service address space **/
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#define MAGIC_ZONE_FRAM_ALIAS 0
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#define MAGIC_ZONE_PPR_ALIAS 1
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#define MAGIC_ZONE_PPC_ALIAS 2
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#define MAGIC_ZONE_FIREWALL 3
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#define MAGIC_ZONE_DMAMAP 4
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#define MAGIC_ZONE_SWTLB 5
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#define MAGIC_ZONE_MISSCNT 6
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#define MAGIC_ZONE_NODEMAP 7
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#define MAGIC_ZONE_PPR 8
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#define MAGIC_ZONE_PPC 9
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#define MAGIC_ZONE_MILO_ALIAS 10
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#define MAGIC_ZONE_EV5_ALIAS 10
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#define MAGIC_ZONE_NODECOMM 11 /* node communication zone */
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/* do not def zone 12: see below why */
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#define MAGIC_ZONE_BDOOR_DEV 14 /* backdoor area for devices */
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#define MAGIC_ZONE_FPROM_ALIAS 15
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#ifndef SIMOS64BIT
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#undef MAGIC_ZONE_FPROM_ALIAS /* In 32bit Simos, 0xbfc00000 maps to... */
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#define MAGIC_ZONE_FPROM_ALIAS 12 /* ... zone 12 */
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#endif
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/** PPR numbering **/
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/* Individual MAGIC registers */
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#define MAGIC_PPR_IECHIGH 0x0000 /* r */
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#define MAGIC_PPR_ACKINTERNAL 0x0001 /* w */
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#define MAGIC_PPR_IECENABLE 0x0002 /* r/w */
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#define MAGIC_PPR_SENDIPI 0x0003 /* w */
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#define MAGIC_PPR_OPSPACE 0x0004 /* r/w */
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#define MAGIC_PPR_ASID 0x0005 /* r/w */
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#define MAGIC_PPR_TLBINVAL 0x0006 /* w */
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#define MAGIC_PPR_TLBINUSE 0x0007 /* r */
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#define MAGIC_PPR_MSGTAG 0x0008 /* r/w */
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#define MAGIC_PPR_STALLOSPC 0x0009 /* r/w */
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#define MAGIC_PPR_CYCLECOUNT 0x000a /* r */
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#define MAGIC_PPR_NETMSGTIME 0x000b /* r */
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#define MAGIC_PPR_RESERVED_C 0x000c /* */
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#define MAGIC_PPR_RESERVED_D 0x000d /* */
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#define MAGIC_PPR_RESERVED_E 0x000e /* */
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#define MAGIC_PPR_RESERVED_F 0x000f /* */
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#define MAGIC_PPR_UNUSED10 0x0010 /* r */
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#define MAGIC_PPR_PROTVERSION 0x0011 /* r */
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#define MAGIC_PPR_HWVERSION 0x0012 /* r */
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#define MAGIC_PPR_REMAPMASK 0x0013 /* r/w */
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#define MAGIC_PPR_PROTCONTROL 0x0014 /* r/w */
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#define MAGIC_PPR_RESERVED_15 0x0015 /* */
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#define MAGIC_PPR_RESERVED_16 0x0016 /* */
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#define MAGIC_PPR_RESERVED_17 0x0017 /* */
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#define MAGIC_PPR_OUTOFRANGE 0x0018 /* r */
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#define MAGIC_PPR_INTERVAL 0x0019 /* r/w */
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#define MAGIC_PPR_SLOTMAP 0x001a /* r/w */
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#define MAGIC_SLOTMAP_SLOT0_OFFS 0
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#define MAGIC_SLOTMAP_SLOT0_MASK 0x00000000000000FFLL
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#define MAGIC_SLOTMAP_SLOT1_OFFS 8
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#define MAGIC_SLOTMAP_SLOT1_MASK 0x000000000000FF00LL
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#define MAGIC_SLOTMAP_SLOT2_OFFS 16
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#define MAGIC_SLOTMAP_SLOT2_MASK 0x0000000000FF0000LL
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#define MAGIC_SLOTMAP_SLOT3_OFFS 24
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#define MAGIC_SLOTMAP_SLOT3_MASK 0x00000000FF000000LL
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#define MAGIC_PPR_FWSHIFT 0x001b /* r/w */
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#define MAGIC_PPR_RECOVERYSYNC 0x001c /* r */
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#define MAGIC_RECOVERYSYNC_PHASE_MASK 0xF000000000000000LL;
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#define MAGIC_RECOVERYSYNC_PHASE_SHIFT 60
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#define MAGIC_RECOVERYSYNC_PHASE_ZERO (0x0LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
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#define MAGIC_RECOVERYSYNC_PHASE_ONE (0x1LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
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#define MAGIC_RECOVERYSYNC_PHASE_TWO (0x2LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
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#define MAGIC_RECOVERYSYNC_PHASE_THREE (0x3LL << MAGIC_RECOVERYSYNC_PHASE_SHIFT)
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#define MAGIC_RECOVERYSYNC_TIMESTAMP_MASK 0x0FFFFFFFFFFFFFFFLL
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#define MAGIC_RECOVERYSYNC_TIMESTAMP_SHIFT 0
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#define MAGIC_PPR_REPORT_DIAG_RESULT 0x001d /* w */
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#define MAGIC_REPORT_PASS_DIAG 0 /* other values indicate fail */
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#define MAGIC_PPR_RESERVED_1E 0x001e /* w */
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#define MAGIC_PPR_DRAIN_POLL 0x001f /* r */
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#define MAGIC_PPR_NODECONFIG 0x0020 /* r */
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#define MAGIC_NODECONFIG_THISNODE_OFFS 0
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#define MAGIC_NODECONFIG_THISNODE_MASK 0x0000000000000fffLL
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#define MAGIC_NODECONFIG_FIRSTNODE_OFFS 12
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#define MAGIC_NODECONFIG_FIRSTNODE_MASK 0x0000000000fff000LL
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#define MAGIC_NODECONFIG_NODESINCELL_OFFS 24
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#define MAGIC_NODECONFIG_NODESINCELL_MASK 0x0000000fff000000LL
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#define MAGIC_NODECONFIG_THISCELL_OFFS 36
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#define MAGIC_NODECONFIG_THISCELL_MASK 0x0000fff000000000LL
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#define MAGIC_NODECONFIG_NCELLS_OFFS 48
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#define MAGIC_NODECONFIG_NCELLS_MASK 0x0fff000000000000LL
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#define MAGIC_NODECONFIG_THISNODE(val) \
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(((val)&MAGIC_NODECONFIG_THISNODE_MASK)>>MAGIC_NODECONFIG_THISNODE_OFFS)
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#define MAGIC_NODECONFIG_FIRSTNODE(val) \
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(((val)&MAGIC_NODECONFIG_FIRSTNODE_MASK)>>MAGIC_NODECONFIG_FIRSTNODE_OFFS)
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#define MAGIC_NODECONFIG_NODESINCELL(val) \
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(((val)&MAGIC_NODECONFIG_NODESINCELL_MASK)>>MAGIC_NODECONFIG_NODESINCELL_OFFS)
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#define MAGIC_NODECONFIG_THISCELL(val) \
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(((val)&MAGIC_NODECONFIG_THISCELL_MASK)>>MAGIC_NODECONFIG_THISCELL_OFFS)
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#define MAGIC_NODECONFIG_NCELLS(val) \
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(((val)&MAGIC_NODECONFIG_NCELLS_MASK)>>MAGIC_NODECONFIG_NCELLS_OFFS)
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#define MAGIC_PPR_ADDRCONFIG 0x0021 /* r */
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#define MAGIC_ADDRCONFIG_PAGES_OFFS 0
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#define MAGIC_ADDRCONFIG_PAGES_MASK 0x0000ffffffffLL
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#define MAGIC_ADDRCONFIG_NNBITS_OFFS 32
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#define MAGIC_ADDRCONFIG_NNBITS_MASK 0x00ff00000000LL
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#define MAGIC_ADDRCONFIG_MASBITS_OFFS 40
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#define MAGIC_ADDRCONFIG_MASBITS_MASK 0xff0000000000LL
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#define MAGIC_ADDRCONFIG_PAGES(val) \
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(((val)&MAGIC_ADDRCONFIG_PAGES_MASK)>>MAGIC_ADDRCONFIG_PAGES_OFFS)
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#define MAGIC_ADDRCONFIG_NNBITS(val) \
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(((val)&MAGIC_ADDRCONFIG_NNBITS_MASK)>>MAGIC_ADDRCONFIG_NNBITS_OFFS)
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#define MAGIC_ADDRCONFIG_MASBITS(val) \
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(((val)&MAGIC_ADDRCONFIG_MASBITS_MASK)>>MAGIC_ADDRCONFIG_MASBITS_OFFS)
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/* OSPC mirror in uncached space (used by FPROM) */
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#define MAGIC_PPR_OSPC 0x1000 /* r */
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/** PPC error codes **/
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#define MAGIC_PPC_NOT_SUCCESSFUL_BIT 0x8000000000000000LL /* set for error */
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/* these return values should be ORed with the "not successful" bit */
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#define MAGIC_PPC_RETRY_CODE 0x00 /* please retry request (default) */
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#define MAGIC_PPC_BADGROUP 0x01 /* PPC group was invalid */
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#define MAGIC_PPC_BADOPCODE 0x02 /* PPC opcode was invalid */
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#define MAGIC_PPC_ARGOUTOFRANGE 0x03 /* some arg to the PPC was bad */
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#define MAGIC_PPC_BUSY 0x04 /* operation needed some
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* resource that was unavail */
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/* these results indicate the request cannot be serviced, and it should
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not be retried. The interpretation of these is protocol-dependent
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One example is: the physical pages are remote. The application
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can't know this, but the sequence was otherwise valid. If a protocol
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can't handle remote pages, this is a possibility. So, e.g. fmemcpy
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uses PROT_FAIL1 to indicate it can't handle the pages. See the
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individual _interface files to describe the interpretation*/
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#define MAGIC_PPC_PROT_FAIL1 0x11
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#define MAGIC_PPC_PROT_FAIL2 0x12
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#define MAGIC_PPC_PROT_FAIL3 0x13
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#define MAGIC_PPC_RETRY (MAGIC_PPC_NOT_SUCCESSFUL_BIT|MAGIC_PPC_RETRY_CODE)
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/** PPC groups **/
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#define MAGIC_PPC_GROUP_KERNEL 0x000
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#define MAGIC_PPC_GROUP_MSG 0x001
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/** kernel group opcodes **/
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#define MAGIC_PPC_OP_SIPSLO 0x000
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#define MAGIC_PPC_OP_SIPSHI 0x001
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#define MAGIC_PPC_OP_MEMCPY 0x002
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#define MAGIC_PPC_OP_IBITWRITE 0x003
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#define MAGIC_PPC_OP_IBITREAD 0x004
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#define MAGIC_PPC_OP_DONATE 0x005
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#define MAGIC_PPC_OP_RESETPOOL 0x006
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#define MAGIC_PPC_OP_LOADSTATE 0x007
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#define MAGIC_PPC_OP_STORESTATE 0x008
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#define MAGIC_PPC_OP_MEMRESET 0x009
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#define MAGIC_PPC_OP_VECTORPKT 0x00A
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#define MAGIC_PPC_OP_BZERO 0x00B
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/* HLL/Diag opcodes within kernel region */
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#define MAGIC_PPC_OP_PRINTF1 0x00C
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/* config info opcodes within kernel region */
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/* note: result has same format as MAGIC_PPR_NODECONFIG and
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* MAGIC_PPR_ADDRCONFIG PPR's.
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*/
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#define MAGIC_PPC_OP_CELLNODECONFIG 0x010
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#define MAGIC_PPC_OP_NODEADDRCONFIG 0x011
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#define MAGIC_PPC_OP_STARTSLAVENODE 0x012
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/** msg group opcodes **/
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#define MAGIC_PPC_OP_MEMCPY_V 0x000
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#define MAGIC_PPC_OP_SIPS_V 0x001
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#define MAGIC_PPC_OP_BZERO_V 0x002
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/** OSPC defs **/
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/* OSPC opcodes.
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*
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* Note:
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* In the future we will probably add more structure to the header dword...
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* for example, in SIPS it would be nice to have the sender CPU from the
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* message header there, which authenticates the sender at a lower level
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* than the sender cell info in the SIPS header. Because this will happen
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* eventually, these opcodes are not defined as 0x01LL.
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*/
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#define MAGIC_OSPC_LO_NONE 0xff /* no OSPC pending */
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#define MAGIC_OSPC_LO_SIPSREQ 0x01 /* lopri SIPS pending */
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#define MAGIC_OSPC_LO_CACHECTR 0x02 /* ??? */
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#define MAGIC_OSPC_HI_NONE 0xff /* no OSPC pending */
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#define MAGIC_OSPC_HI_SIPSREPLY 0x81 /* hipri SIPS pending */
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#define MAGIC_OSPC_HI_TLBMISS 0x82 /* ??? */
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/* For vector packet payload retrieval... in the future we'll move to some
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method other than OSPCs for this. */
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#define MAGIC_OSPC_VEC_REQ_NONE 0xff
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#define MAGIC_OSPC_VEC_REQ 0xd1
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#define MAGIC_OSPC_VEC_REP_NONE 0xff
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#define MAGIC_OSPC_VEC_REP 0xe1
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/* OSPC offsets */
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#define MAGIC_OSPC_SIZE 128 /* OSPC size == 1 cache line */
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#define MAGIC_OSPC_LO_OFFS 0*MAGIC_OSPC_SIZE /* lopri SIPS */
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#define MAGIC_OSPC_HI_OFFS 1*MAGIC_OSPC_SIZE /* hipri SIPS */
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#define MAGIC_OSPC_VEC_REQ_OFFS 2*MAGIC_OSPC_SIZE /* VP request */
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#define MAGIC_OSPC_VEC_REP_OFFS 3*MAGIC_OSPC_SIZE /* VP reply */
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/***************************************************************************
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MAGIC defs which reflect the virtual -> physical address mapping
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***************************************************************************/
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/* auxiliary defs -- ONLY FOR INTERNAL USE IN THIS FILE */
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#ifndef SIMOS64BIT /* 32 bit address space (current SimOS version) */
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/* virtual addresses for start of FPROM and FRAM */
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#define FPROM_BASE _SEXT(0xbfc00000)
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#define FRAM_BASE _SEXT(0xa0000000)
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#ifdef _KERNEL
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#define __MAGIC_BASE COMPAT_K1BASE /* KSEG1 */
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#define __MAGIC_BASE_32 COMPAT_K1BASE_32 /* KSEG1 */
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#define __MAGIC_BASE_ACC COMPAT_K1BASE /* still KSEG1 */
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#else
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#define __MAGIC_BASE K1BASE /* KSEG1 */
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#define __MAGIC_BASE_32 K1BASE_32 /* KSEG1 */
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#define __MAGIC_BASE_ACC K1BASE /* still KSEG1 */
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#endif
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#define __MAGIC_OSPC_BASE (K0BASE+0x1000) /* OSPC right after remap */
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#define __MAGIC_OSPC_END (K0BASE+0x2000) /* 1 page-alias for each node */
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#define __MAGIC_NODE_BITS 5 /* max. 32 nodes */
|
||||
#define __MAGIC_NODE_OFFS 24
|
||||
|
||||
#define __MAGIC_ZONE_BITS 4 /* 16 zones / node */
|
||||
#define __MAGIC_ZONE_OFFS 20 /* 1MB / zone */
|
||||
|
||||
#define __MAGIC_REG_BITS 17
|
||||
#define __MAGIC_REG_OFFS 3 /* registers are 64bit */
|
||||
|
||||
#define __MAGIC_PPC_SEQ_BITS 7 /* one cache line */
|
||||
#define __MAGIC_PPC_SEQ_OFFS 0
|
||||
#define __MAGIC_PPC_OPC_BITS 5 /* group corresponds to a 4K page */
|
||||
#define __MAGIC_PPC_OPC_OFFS __MAGIC_PPC_SEQ_BITS
|
||||
#define __MAGIC_PPC_GRP_BITS 8
|
||||
#define __MAGIC_PPC_GRP_OFFS (__MAGIC_PPC_SEQ_BITS+__MAGIC_PPC_OPC_BITS)
|
||||
|
||||
#define __MAGIC_ZONE(node, nbits, zone) \
|
||||
( __MAGIC_BASE | ((node) << __MAGIC_NODE_OFFS) \
|
||||
| ((zone) << __MAGIC_ZONE_OFFS) )
|
||||
#define __MAGIC_ZONE_32(node, nbits, zone) \
|
||||
( __MAGIC_BASE_32 | ((node) << __MAGIC_NODE_OFFS) \
|
||||
| ((zone) << __MAGIC_ZONE_OFFS) )
|
||||
#define __MAGIC_ZONE_ACC(node, nbits, zone) \
|
||||
( __MAGIC_BASE_ACC | ((node) << __MAGIC_NODE_OFFS) \
|
||||
| ((zone) << __MAGIC_ZONE_OFFS) )
|
||||
#define __MAGIC_ZONE_ALIAS(zone) \
|
||||
( __MAGIC_BASE | ((zone) << __MAGIC_ZONE_OFFS) )
|
||||
#define __MAGIC_ZONE_ALIAS_ACC(zone) \
|
||||
( __MAGIC_BASE_ACC | ((zone) << __MAGIC_ZONE_OFFS) )
|
||||
#define __MAGIC_OSPC_RANGE(node, nbits) \
|
||||
( __MAGIC_OSPC_BASE )
|
||||
|
||||
#define MAGIC_MAX_REMAP_PAGES 1 /* max. sz of remap area (limited
|
||||
* by OSPC in following page) */
|
||||
|
||||
/* offsets in bdoor zone of simulated devices (64KB each) */
|
||||
#define __MAGIC_BDOOR_CLOCK_OFFS 0x00000000 /* CMOS rt clock */
|
||||
#define __MAGIC_BDOOR_CNSLE_OFFS 0x00001000 /* console interface */
|
||||
#define __MAGIC_BDOOR_ETHER_OFFS 0x00002000 /* ethernet controller */
|
||||
#define __MAGIC_BDOOR_DISKS_OFFS 0x00010000 /* scsi disk controller */
|
||||
|
||||
#ifdef TORNADO
|
||||
#define __MAGIC_BDOOR_GIZMO_OFFS \
|
||||
((__MAGIC_BDOOR_DISKS_OFFS + sizeof(DevDiskRegisters)*DEV_DISK_MAX_DISKS + \
|
||||
0x1000 - 1) & ~(0x1000-1)) /* gizmo interface */
|
||||
#endif
|
||||
|
||||
#else /* SIMOS64BIT */ /* 64 bit address space */
|
||||
not yet implemented, will not compile;
|
||||
#endif /* SIMOS64BIT */
|
||||
|
||||
#ifdef LANGUAGE_ASSEMBLY
|
||||
#define MagicRegister int
|
||||
#define MAGICREGP_CAST
|
||||
#else
|
||||
typedef uint64 MagicRegister;
|
||||
#define MAGICREGP_CAST (MagicRegister *)
|
||||
#endif
|
||||
|
||||
/* PPR access */
|
||||
#define MAGIC_PPR(node, nbits, reg) \
|
||||
((MagicRegister*) \
|
||||
(__MAGIC_ZONE(node,nbits,MAGIC_ZONE_PPR) | ((reg) << __MAGIC_REG_OFFS)))
|
||||
#define MAGIC_PPR_ALIAS(reg) \
|
||||
(MAGICREGP_CAST \
|
||||
(__MAGIC_ZONE_ALIAS(MAGIC_ZONE_PPR_ALIAS) | ((reg) << __MAGIC_REG_OFFS)))
|
||||
#define MAGIC_PPR_NODE(addr, nbits) \
|
||||
( ((addr) >> __MAGIC_NODE_OFFS) & ((1LL << (nbits)) - 1) )
|
||||
#define MAGIC_PPR_ZONE(addr) \
|
||||
( ((addr) >> __MAGIC_ZONE_OFFS) & ((1LL << __MAGIC_ZONE_BITS) - 1) )
|
||||
#define MAGIC_PPR_REG(addr) \
|
||||
( ((addr) >> __MAGIC_REG_OFFS) & ((1LL << __MAGIC_REG_BITS) - 1) )
|
||||
|
||||
/* PPC access */
|
||||
#define MAGIC_PPC(node, nbits, grp, opc) \
|
||||
((MagicRegister*) \
|
||||
( __MAGIC_ZONE(node,nbits,MAGIC_ZONE_PPC) | \
|
||||
((grp) << __MAGIC_PPC_GRP_OFFS) | \
|
||||
((opc) << __MAGIC_PPC_OPC_OFFS) ))
|
||||
#define MAGIC_PPC_ACC(node, nbits, grp, opc) \
|
||||
((MagicRegister*) \
|
||||
( __MAGIC_ZONE_ACC(node,nbits,MAGIC_ZONE_PPC) | \
|
||||
((grp) << __MAGIC_PPC_GRP_OFFS) | \
|
||||
((opc) << __MAGIC_PPC_OPC_OFFS) ))
|
||||
#define MAGIC_PPC_ALIAS(grp, opc) \
|
||||
(MAGICREGP_CAST \
|
||||
( __MAGIC_ZONE_ALIAS(MAGIC_ZONE_PPC_ALIAS) \
|
||||
| ((grp) << __MAGIC_PPC_GRP_OFFS) \
|
||||
| ((opc) << __MAGIC_PPC_OPC_OFFS) ))
|
||||
#define MAGIC_PPC_ALIAS_ACC(grp, opc) \
|
||||
((MagicRegister*) \
|
||||
( __MAGIC_ZONE_ALIAS_ACC(MAGIC_ZONE_PPC_ALIAS) \
|
||||
| ((grp) << __MAGIC_PPC_GRP_OFFS) \
|
||||
| ((opc) << __MAGIC_PPC_OPC_OFFS) ))
|
||||
|
||||
#define MAGIC_PPC_NODE(addr,nbits) \
|
||||
( ((addr) >> __MAGIC_NODE_OFFS) & ((1LL << (nbits)) - 1) )
|
||||
#define MAGIC_PPC_ZONE(addr) \
|
||||
( ((addr) >> __MAGIC_ZONE_OFFS) & ((1LL << __MAGIC_ZONE_BITS) - 1) )
|
||||
#define MAGIC_PPC_GRP(addr) \
|
||||
( ((addr) >> __MAGIC_PPC_GRP_OFFS) & ((1LL << __MAGIC_PPC_GRP_BITS) - 1) )
|
||||
#define MAGIC_PPC_OPC(addr) \
|
||||
( ((addr) >> __MAGIC_PPC_OPC_OFFS) & ((1LL << __MAGIC_PPC_OPC_BITS) - 1) )
|
||||
|
||||
/* Nodemap access */
|
||||
#define MAGIC_NODEMAP(node, nbits, reg) \
|
||||
((MagicRegister*) \
|
||||
(__MAGIC_ZONE(node,nbits,MAGIC_ZONE_NODEMAP) | ((reg) << __MAGIC_REG_OFFS)))
|
||||
|
||||
/* Nodecomm access */
|
||||
#define MAGIC_NODECOMM(node, nbits, n) \
|
||||
((MagicRegister*) \
|
||||
(__MAGIC_ZONE(node,nbits,MAGIC_ZONE_NODECOMM) | ((n) << __MAGIC_REG_OFFS)))
|
||||
|
||||
/* OSPC access */
|
||||
#define MAGIC_OSPC(node, nbits, ospc) \
|
||||
( (MagicRegister*)(__MAGIC_OSPC_RANGE(node, nbits) + (ospc)) )
|
||||
|
||||
#define MAGIC_UNCACHED_OSPC(node, nbits, offs) \
|
||||
MAGIC_PPR(node, nbits, MAGIC_PPR_OSPC + ((offs) >> __MAGIC_REG_OFFS))
|
||||
|
||||
#define MAGIC_UNCACHED_OSPC_ALIAS(offs) \
|
||||
MAGIC_PPR_ALIAS(MAGIC_PPR_OSPC + ((offs) >> __MAGIC_REG_OFFS))
|
||||
|
||||
#define MAGIC_OSPC_OPCODE(val) ((int)((val) & ((MagicRegister)0xff)))
|
||||
|
||||
/* firewall access */
|
||||
#define MAGIC_FW_RANGE(node, nbits) \
|
||||
((MagicRegister*) __MAGIC_ZONE(node,nbits,MAGIC_ZONE_FIREWALL))
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
definitions of the simulated devices and of various parameters
|
||||
which depend on the simulator.
|
||||
***************************************************************************/
|
||||
|
||||
#define MAGIC_MAX_CPUS 32 /* max no of nodes in a simulation */
|
||||
#define MAGIC_MAX_CELLS 32 /* max no of cells in a simulation */
|
||||
|
||||
|
||||
/* needed so assembly files can include machine_defs */
|
||||
#ifndef LANGUAGE_ASSEMBLY
|
||||
|
||||
|
||||
typedef unsigned int DevRegister;
|
||||
|
||||
/* disk device:
|
||||
* there is currently one controller per cell. The controller
|
||||
* can be accessed through the backdoor zone of the first node
|
||||
* in the cell.
|
||||
*/
|
||||
|
||||
#define DEV_DISK_CMD_SIZE 12
|
||||
#define DEV_DISK_MAX_DMA_LENGTH 1024 /* max no of pages for one request */
|
||||
#define DEV_DISK_MAX_DISKS 128 /* max disks per controller (cell) */
|
||||
|
||||
typedef struct DevDiskRegisters {
|
||||
DevRegister intr_pending; /* r:int posted for this disk / w:ack int */
|
||||
DevRegister errnoVal; /* status of last i/o */
|
||||
DevRegister bytesTransferred; /* bytes transferred during last i/o */
|
||||
|
||||
DevRegister interruptNode; /* node to interrupt upon completion */
|
||||
DevRegister k0Addr[DEV_DISK_MAX_DMA_LENGTH]; /* page addresses */
|
||||
DevRegister offset; /* page offset for first page */
|
||||
DevRegister command[DEV_DISK_CMD_SIZE]; /* i/o command */
|
||||
|
||||
DevRegister startIO; /* write here causes i/o initiation */
|
||||
DevRegister doneIO; /* tells when i/o complete */
|
||||
|
||||
DevRegister filler[16]; /* filler: resize when you add new regs */
|
||||
} DevDiskRegisters;
|
||||
|
||||
#define DEV_DISK_REGISTERS(node, nbits, disk) \
|
||||
( ((volatile DevDiskRegisters*) \
|
||||
(__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
|
||||
__MAGIC_BDOOR_DISKS_OFFS)) + \
|
||||
(disk) )
|
||||
|
||||
|
||||
/* console device:
|
||||
* there is currently one console per cell. The console registers
|
||||
* can be accessed through the backdoor zone of the first node
|
||||
* in the cell. The console always interrupts this node.
|
||||
*/
|
||||
|
||||
#define DEV_CNSLE_TX_INTR 0x01 /* intr enable / state bits */
|
||||
#define DEV_CNSLE_RX_INTR 0x02
|
||||
|
||||
typedef struct DevConsoleRegisters {
|
||||
DevRegister intr_status; /* r: intr state / w: intr enable */
|
||||
DevRegister data; /* r: current char / w: send char */
|
||||
} DevConsoleRegisters;
|
||||
|
||||
#define DEV_CONSOLE_REGISTERS(node, nbits) \
|
||||
( ((volatile DevConsoleRegisters*) \
|
||||
(__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
|
||||
__MAGIC_BDOOR_CNSLE_OFFS)) )
|
||||
|
||||
|
||||
/* ethernet device:
|
||||
* there is currently one ether interface per cell. The ether registers
|
||||
* can be accessed through the backdoor zone of the first node
|
||||
* in the cell. The ether interface always interrupts this node.
|
||||
*/
|
||||
|
||||
#define DEV_ETHER_MAX_RCV_ENTRIES 64
|
||||
#define DEV_ETHER_MAX_SND_ENTRIES 64
|
||||
#define DEV_ETHER_MAX_SND_CHUNKS 128
|
||||
|
||||
#define DEV_ETHER_MAX_TRANSFER_SIZE 1800
|
||||
|
||||
typedef struct DevEtherRegisters {
|
||||
DevRegister etheraddr[6]; /* controller tells OS its ethernet addr */
|
||||
DevRegister numRcvEntries; /* read by OS, indicates how many receive
|
||||
* ring buffer entries will be used. OS must
|
||||
* allocate a receive buffer for each of
|
||||
* these entries */
|
||||
DevRegister numSndEntries; /* read by OS, indicates how many send ring
|
||||
* buffer entries will be used so it knows
|
||||
* when to wrap its index pointer */
|
||||
DevRegister numSndChunks; /* same as numSndEntries */
|
||||
|
||||
struct {
|
||||
DevRegister pAddr;
|
||||
DevRegister maxLen;
|
||||
DevRegister len;
|
||||
DevRegister flag;
|
||||
} rcvEntries[ DEV_ETHER_MAX_RCV_ENTRIES ];
|
||||
|
||||
struct {
|
||||
DevRegister firstChunk;
|
||||
DevRegister lastChunk;
|
||||
DevRegister flag; /* triggers send */
|
||||
} sndEntries[ DEV_ETHER_MAX_SND_ENTRIES ];
|
||||
|
||||
struct {
|
||||
DevRegister pAddr;
|
||||
DevRegister len;
|
||||
} sndChunks[ DEV_ETHER_MAX_SND_CHUNKS ];
|
||||
|
||||
/* note: sndChunks is last because we might extend the number of
|
||||
* send chunks in the future and don't want to break OS compatibility when
|
||||
* we do it */
|
||||
} DevEtherRegisters;
|
||||
|
||||
/* values for flag field */
|
||||
#define DEV_ETHER_OS_OWNED (DevRegister)1
|
||||
#define DEV_ETHER_CONTROLLER_OWNED (DevRegister)2
|
||||
|
||||
#define DEV_ETHER_REGISTERS(node, nbits) \
|
||||
( ((volatile DevEtherRegisters*) \
|
||||
(__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
|
||||
__MAGIC_BDOOR_ETHER_OFFS)) )
|
||||
|
||||
|
||||
/* CMOS RT clock device:
|
||||
* This simulates a very primitive CMOS clock. This device only
|
||||
* has one register that contains the time since January 1, 1970
|
||||
* (same as the Unix gettimeofday() result).
|
||||
*/
|
||||
|
||||
typedef struct DevClockRegisters {
|
||||
DevRegister ctime; /* current time */
|
||||
} DevClockRegisters;
|
||||
|
||||
#define DEV_CLOCK_REGISTERS(node, nbits) \
|
||||
( ((volatile DevClockRegisters*) \
|
||||
(__MAGIC_ZONE(node, nbits, MAGIC_ZONE_BDOOR_DEV) + \
|
||||
__MAGIC_BDOOR_CLOCK_OFFS)) )
|
||||
|
||||
|
||||
#endif /* LANGUAGE_ASSEMBLY */
|
||||
|
||||
|
||||
/* Interrupt bit assignments:
|
||||
*
|
||||
* There are 64 external interrupt lines coming into MAGIC. The
|
||||
* following defines show to what interrupt line each device is
|
||||
* connected.
|
||||
*
|
||||
* NOTE: when MAGIC posts an interrupt, the IEChigh register will
|
||||
* contain the bit number of the highest level interrupt pending,
|
||||
* so the bit numbers are also IEC's (Interrupt Exception Codes).
|
||||
*/
|
||||
|
||||
#define DEV_IEC_SCSI 0x08 /* scsi disk controller */
|
||||
#define DEV_IEC_ETHER 0x09 /* ether controller */
|
||||
#define DEV_IEC_OSPC_LO 0x0a /* low-priority SIPS */
|
||||
#define DEV_IEC_VEC_REQ 0x0b /* vector packet request */
|
||||
#define DEV_IEC_KEYBDMOUSE 0x10 /* console */
|
||||
#define DEV_IEC_DUART 0x11 /* serial line on FLASH board */
|
||||
#define DEV_IEC_OSPC_HI 0x12 /* high-priority SIPS */
|
||||
#define DEV_IEC_RECOVERY 0x13 /* recov int (posted by MAGIC) */
|
||||
#define DEV_IEC_VEC_REPLY 0x14 /* vector packet reply */
|
||||
#define DEV_IEC_CLOCK 0x18 /* clock */
|
||||
#define DEV_IEC_IPI 0x20 /* inter-processor interrupt */
|
||||
#define DEV_IEC_DEBUG 0x21 /* ??? */
|
||||
#define DEV_IEC_PROFTIM 0x28 /* prof timer (currently unused) */
|
||||
#define DEV_IEC_MAGICWARN 0x29 /* ??? */
|
||||
#define DEV_IEC_MAGICERR 0x31 /* ??? */
|
||||
#define DEV_IEC_POWERFAIL 0x38 /* ??? */
|
||||
|
||||
#define DEV_IEC_MAX 0x3f /* 64 bits */
|
||||
|
||||
|
||||
/* PCI slot assignments:
|
||||
*
|
||||
* NOTE:
|
||||
* On the real system these slot assignments wouldn't be fixed (you
|
||||
* could plug a card into any slot on the I/O bus) but this isn't
|
||||
* particularly interesting to model.
|
||||
*/
|
||||
|
||||
#define DEV_PCI_DISK_SLOT 0
|
||||
#define DEV_PCI_ETHER_SLOT 1
|
||||
#define DEV_PCI_CONSOLE_SLOT 2
|
||||
|
||||
|
||||
#endif /* _MACHINE_DEFS_H */
|
||||
Loading…
Reference in a new issue