Commit graph

58 commits

Author SHA1 Message Date
Gabe Black
68d7382cf3 Eliminated TARGET_ALPHA, since THE_ISA provides the same function.
--HG--
extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a
2006-03-10 16:26:31 -05:00
Gabe Black
f102365bfe SimpleCPU compiles with merge.
arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
base/chunk_generator.hh:
base/loader/elf_object.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
kern/linux/linux.hh:
kern/tru64/tru64.hh:
mem/packet.hh:
mem/page_table.cc:
mem/page_table.hh:
mem/physical.cc:
mem/request.hh:
mem/translating_port.cc:
sim/process.hh:
sim/system.cc:
    Fixing merged changes.

--HG--
extra : convert_revision : 2e94f21009395db654880fcb94ec806b6f5772c3
2006-03-09 19:21:35 -05:00
Gabe Black
872bbdfc33 Hand merge. Stuff probably doesn't compile.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
2006-03-09 18:35:28 -05:00
Gabe Black
91545ac2bf Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into  zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch

cpu/simple/cpu.cc:
    Hand Merge

--HG--
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : bf664b092f993d0f4675ce8e7df13645a920c1f4
2006-03-09 15:15:55 -05:00
Kevin Lim
e30bce8f8e Use functions to access XC.
cpu/exec_context.hh:
    Include readNextNPC function.
cpu/simple/cpu.cc:
    Use functions to set and access nextPC, nextNPC.

--HG--
extra : convert_revision : 22622b9c110e1d99cc9106a2a27c479579d7e1ad
2006-03-09 15:10:55 -05:00
Korey Sewell
a3aae21d03 last changes before big merge
arch/alpha/isa_traits.hh:
arch/sparc/isa_traits.hh:
    add nnpc for compiling purposes in exec_context setNextNPC function
cpu/exec_context.hh:
    set NNPC function
cpu/simple/cpu.cc:
    use NNPC in determining what PC we are using

--HG--
extra : convert_revision : e810cfbc5dc31879b20d2cc40bf9871613203532
2006-03-09 03:27:51 -05:00
Kevin Lim
11aead894d Updates for the quiesceEvent that was added to the XC.
Also several files need to include system.hh or symtab.hh.  This is because exec_context.hh has less #includes than before, requiring some of the files that include it to include some other files as well.

arch/alpha/faults.cc:
    Avoid accessing XC directly.
arch/alpha/stacktrace.cc:
    StackTrace needs to include system.hh.
cpu/cpu_exec_context.cc:
    Update for change to CPUExecContext.
cpu/cpu_exec_context.hh:
    Make quiesce events use CPUExecContext instead of ExecContext.  Include functions to allow the quiesce event and last activate/suspend be accessed.
cpu/exec_context.hh:
    Include functions for quiesceEvent.
cpu/intr_control.cc:
    Needs to include cpu/exec_context.hh.
cpu/profile.cc:
    Needs to include symtab.hh for the symbol table.
cpu/profile.hh:
    Needs forward declare of ExecContext.
cpu/simple/cpu.cc:
    Rename xc to cpuXC.
dev/tsunami_cchip.cc:
    Needs to include exec_context.hh.
kern/kernel_stats.cc:
    Needs to include system.hh.
kern/linux/events.cc:
    Needs to include system.hh.

    Also avoid accessing objects directly from the XC.
kern/tru64/dump_mbuf.cc:
    Include symtab.hh for the SymbolTable and system.hh.
kern/tru64/tru64_events.cc:
    Include system.hh
sim/pseudo_inst.cc:
    Avoid accessing objects directly within the XC.

--HG--
extra : convert_revision : 78fe30d98cd20f7403fa216f772071458b675c84
2006-03-07 19:59:12 -05:00
Kevin Lim
20eced3ea0 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

Further changes still need to be made to the XC code.

arch/alpha/ev5.cc:
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
base/remote_gdb.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
kern/kernel_stats.cc:
sim/pseudo_inst.cc:
    Hand merge.

--HG--
rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc
rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc
rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : c1fe71fdd87d1fcd376f4feec69fc3fa29152e3e
2006-03-05 00:34:54 -05:00
Kevin Lim
f15e492375 Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode.
The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext).

Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC).  The CPU uses the CPUExecContext, or however else it stores its own state.  It then creates a ProxyExecContext, templated on the class used to hold its state.  This proxy is passed to any code outside of the CPU that needs to access the XC.  This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out.

Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers.

SConscript:
    Include new file, cpu_exec_context.cc.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
arch/alpha/isa/decoder.isa:
arch/alpha/stacktrace.cc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
cpu/intr_control.cc:
    Avoid directly accessing objects within the XC.
arch/alpha/ev5.cc:
    Avoid directly accessing objects within the XC.

    KernelStats have been moved to the BaseCPU instead of the XC.
arch/alpha/isa_traits.hh:
    Remove clearIprs().  It wasn't used very often and it did not work well with the proxy ExecContext.
cpu/base.cc:
    Place kernel stats within the BaseCPU instead of the ExecContext.

    For now comment out the profiling code sampling until its exact location is decided upon.
cpu/base.hh:
    Kernel stats are now in the BaseCPU instead of the ExecContext.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
    Changes to support rename of old ExecContext to CPUExecContext.  See changeset for more details.
cpu/exetrace.cc:
    Remove unneeded include of exec_context.hh.
cpu/intr_control.hh:
cpu/o3/alpha_cpu_builder.cc:
    Remove unneeded include of exec_context.hh
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Changes to support rename of old ExecContext to CPUExecContext.  See changeset for more details.

    Also avoid accessing anything directly from the XC.
cpu/pc_event.cc:
    Avoid accessing objects directly from the XC.
dev/tsunami_cchip.cc:
    Avoid accessing objects directly within the XC>
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/linux/linux_threadinfo.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Avoid accessing objects directly within the XC.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
    Kernel stats no longer exist within the XC.
kern/system_events.cc:
    Avoid accessing objects directly within the XC.  Also kernel stats are now in the BaseCPU.
sim/process.cc:
sim/process.hh:
    Avoid accessing regs directly within an ExecContext.  Instead use a CPUExecContext to initialize the registers and copy them over.
cpu/cpu_exec_context.cc:
    Rename old ExecContext to CPUExecContext.  This is used by the old CPU models to store any necessary architectural state.  Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.
cpu/cpu_exec_context.hh:
    Rename old ExecContext to CPUExecContext.  This is used by the old CPU models to store any necessary architectural state.  Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.

    Remove kernel stats from the ExecContext.
sim/pseudo_inst.cc:
    Kernel stats now live within the CPU.

    Avoid accessing objects directly within the XC.

--HG--
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85
2006-03-04 15:18:40 -05:00
Kevin Lim
5790e295a9 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

arch/alpha/ev5.cc:
    Remove intr_post, it is no longer used.
arch/alpha/isa_traits.hh:
    Hand merge.

--HG--
extra : convert_revision : 94f14539a9e5646f8c368b15b2dff18ab2f492cf
2006-03-04 13:06:24 -05:00
Kevin Lim
fc664f7ca6 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/m5-shadowregs

--HG--
extra : convert_revision : 979ab1fc4e1ea4d6a78ac9a2ec894f0be4feb01d
2006-03-03 16:04:34 -05:00
Kevin Lim
e7825aab59 Changes to support automatic renaming of the shadow registers at decode time. This requires using an ExtMachInst (uint64_t) instead of the normal MachInst; the ExtMachInst is packed with extra decode context information. In the case of Alpha, the PAL mode is included.
The shadow registers are folded into the normal integer registers to ease renaming indexing.

Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.

arch/alpha/ev5.cc:
    Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
    Changes for automatically using the shadow registers.  Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.

    The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode.  If it is, then it refers to the reg_redir table to determine the true index of the register it is using.

    Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
    Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.

    Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).

    Change the dependence tags to reflect the integer registers include the 8 shadow registers.

    Define function to make an ExtMachInst.  Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
    Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
    Support the automatic remapping of shadow registers.  Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
    Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
    Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
    Change from MachInst to ExtMachInst to support shadow register renaming.

--HG--
extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5
2006-03-03 15:28:25 -05:00
Gabe Black
dd0d8e6287 Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

--HG--
extra : convert_revision : f6db244a66431dd6b8c5ba251ed02d76cd509cff
2006-03-02 21:44:43 -05:00
Ali Saidi
0fed64a6a4 Fix fault handling, dereferincing a null pointer is bad.
--HG--
extra : convert_revision : a4f658bfd39b7f1d219ad8929b8f45457f49299f
2006-03-02 17:49:12 -05:00
Steve Reinhardt
e7f442d527 Simple program runs with sendAtomic!
Ignoring returned latency for now.
Refactored loadSections in ObjectFile hierarchy.

base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
    Have each section record a pointer to image data.
    This allows us to move common loadSections code into ObjectFile.
base/loader/object_file.cc:
    Have each section record a pointer to image data.
    This allows us to move common loadSections code into ObjectFile.
    Also explicitly load BSS now since we need to allocate the
    translations for it in syscall emulation.
cpu/base.hh:
    Don't need memPort (just pass port in to ExecContext constructor).
cpu/exec_context.cc:
cpu/exec_context.hh:
mem/port.cc:
mem/translating_port.cc:
mem/translating_port.hh:
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
cpu/simple/cpu.cc:
    Explicitly choose one of three timing models.
    Statically allocate request and packet objects when possible.
    Several more minor bug fixes.
    Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now.
    Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all).
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
cpu/simple/cpu.hh:
    Explicitly choose one of three timing models.
    Statically allocate request and packet objects when possible.
    Pass syscall emulation Port into constructor instead of
    getting it from BaseCPU.
mem/physical.cc:
    Set packet result field.

--HG--
extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
2006-03-02 10:31:48 -05:00
Steve Reinhardt
0c2c7171a8 More progress... run a few instructions now, but die on the second
memory access (I think because we're deallocating our one and only
CpuRequest object).

base/loader/aout_object.cc:
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
    Add flag to force allocation of new pages on data writes.
cpu/simple/cpu.cc:
    Several minor fixes.
    Switch to atomic mode for now.
mem/physical.hh:
    Don't copy the packet to the response event, just keep a reference
    to the original.
mem/translating_port.cc:
mem/translating_port.hh:
    Add parameter to writeBlobFunctional() to force allocation of
    unallocated pages on writes.

--HG--
extra : convert_revision : 05cb31c7b0047b492dcfa0d12ddee690ef762b44
2006-03-02 01:01:03 -05:00
Gabe Black
2eff368dd0 Cleaned up some of the Fault system.
arch/alpha/ev5.cc:
    Commented out the intr_post function since it's not used. If this really -is- needed, it should be moved into the fault class.
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Moved the fault invocation code into the fault class fully, and got rid of the need for isA.
cpu/exec_context.cc:
cpu/exec_context.hh:
    Removed the trap function from the ExecContext. The faults will execute normally in full system mode, but always panic in syscall emulation mode.
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Changed the execution context executing a fault to a fault executing on the execution context.
sim/faults.cc:
    If not in full system mode, trying to invoke a fault causes a panic.
sim/faults.hh:
    Removed the isA function.

--HG--
extra : convert_revision : 894dc8f0755c8efc4b7ef5a09fb2cf7373042395
2006-03-01 05:26:08 -05:00
Gabe Black
e08cf8fee0 Changed the name of the fault's invocation method from ev5_trap to invoke.
--HG--
extra : convert_revision : b7ab14ac644f6a38c69aaa5372b3002b21f34af0
2006-03-01 01:23:10 -05:00
Gabe Black
d6c0657116 Used the Fault constructor to create Interrupt faults. Using the pointer directly prevents reference counting from working correctly.
cpu/simple/cpu.cc:
    Used the Fault constructor to create an Interrupt fault.

--HG--
extra : convert_revision : ec2ef7e3cd04ee9a44628877dc6e770fb907104b
2006-03-01 00:14:09 -05:00
Kevin Lim
34da58a698 Merge ktlim@zizzer:/bk/m5
into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean

arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
    Hand merge.

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
2006-02-28 15:16:24 -05:00
Gabe Black
6165419d35 Changed ev5_trap from a function of the execution context to a function of the fault. The actual function still resides in the execution context.
--HG--
extra : convert_revision : 56e33536cdd9079ace03896b85ea3c84b6eb4e57
2006-02-27 23:26:13 -05:00
Kevin Lim
70b35bab57 Changes to put all the misc regs within the misc reg file. This includes the FPCR, Uniq, lock flag, lock addr, and IPRs.
They are now accessed by calling readMiscReg()/setMiscReg() on the XC.  Old IPR accesses are supported by using readMiscRegWithEffect() and setMiscRegWithEffect() (names may change in the future).

arch/alpha/alpha_memory.cc:
    Change accesses to IPR to go through the XC.
arch/alpha/ev5.cc:
    Change accesses for IPRs to go through the misc regs.
arch/alpha/isa/decoder.isa:
    Change accesses to IPRs to go through the misc regs.  readIpr() and setIpr() are now changed to calls to readMiscRegWithEffect() and setMiscRegWithEffect().
arch/alpha/isa/fp.isa:
    Change accesses to IPRs and Fpcr to go through the misc regs.
arch/alpha/isa/main.isa:
    Add support for all misc regs being accessed through readMiscReg() and setMiscReg().  Instead of readUniq and readFpcr, they are replaced by calls with Uniq_DepTag and Fpcr_DepTag passed in as the register index.
arch/alpha/isa_traits.hh:
    Change the MiscRegFile to a class that handles all accesses to MiscRegs, which in Alpha include the FPCR, Uniq, Lock Addr, Lock Flag, and IPRs.
    Two flavors of accesses are supported: normal register reads/writes, and reads/writes with effect.  The latter are basically the original read/write IPR functions, while the former are normal reads/writes.

    The lock flag and lock addr registers are added to the dependence tags in order to support being accessed through the misc regs.
arch/alpha/stacktrace.cc:
cpu/simple/cpu.cc:
dev/sinic.cc:
    Change accesses to the IPRs to go through the XC.
arch/alpha/vtophys.cc:
    Change access to the IPR to go through the XC.
arch/isa_parser.py:
    Change generation of code for control registers to use the readMiscReg and setMiscReg functions.
base/remote_gdb.cc:
    Change accesses to the IPR to go through the XC.
cpu/exec_context.hh:
    Use the miscRegs to access the lock addr, lock flag, and other misc registers.
cpu/o3/alpha_cpu.hh:
cpu/simple/cpu.hh:
    Support interface for reading and writing misc registers, which replaces readUniq, readFpcr, readIpr, and their set functions.
cpu/o3/alpha_cpu_impl.hh:
    Change accesses to the IPRs to go through the miscRegs.
    For now comment out some of the accesses to the misc regs until the proxy exec context is completed.
cpu/o3/alpha_dyn_inst.hh:
    Change accesses to misc regs to use readMiscReg and setMiscReg.
cpu/o3/alpha_dyn_inst_impl.hh:
    Remove old misc reg accessors.
cpu/o3/cpu.cc:
    Comment out old misc reg accesses until the proxy exec context is completed.
cpu/o3/cpu.hh:
    Change accesses to the misc regs.
cpu/o3/regfile.hh:
    Remove old access methods for the misc regs, replace them with readMiscReg and setMiscReg.  They are dummy functions for now until the proxy exec context is completed.
kern/kernel_stats.cc:
kern/system_events.cc:
    Have accesses to the IPRs go through the XC.
kern/tru64/tru64.hh:
    Have accesses to the misc regs use the new access methods.

--HG--
extra : convert_revision : e32e0a3fe99522e17294bbe106ff5591cb1a9d76
2006-02-27 11:44:35 -05:00
Gabe Black
f1ef4a8f06 Renamed arch files to remove alpha prefix, and changed alpha_memory.hh and cc to a more accurate tlb.hh and cc
--HG--
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux_process.hh
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/tlb.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64_process.hh
extra : convert_revision : 9fe6863cc37347d2a6bd716c529b0a4a50b36ea7
2006-02-27 06:05:10 -05:00
Gabe Black
c5dcd152f2 Changed targetarch to just arch.
SConscript:
    Changed all of the "targetarch" files to be "arch" files
arch/SConscript:
    Added all of the remaining targetarch files to isa_switch_hdrs

--HG--
extra : convert_revision : a37d18349e27cf92dce12814f21944daa7fe9480
2006-02-27 05:35:43 -05:00
Gabe Black
07cd7e966e Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class, and replaced the isA templated function with them where appropriate.
arch/alpha/ev5.cc:
cpu/simple/cpu.cc:
    Changed from the isA templated function to isMachineCheckFault and isAlignmentFault
sim/faults.hh:
    Added isMachineCheckFault and isAlignmentFault virtual functions to the fault base class.

--HG--
extra : convert_revision : 3bf3a4369bc24a039648ee4f2a9c1663362ff2e2
2006-02-27 04:02:45 -05:00
Gabe Black
e66f521d5b Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into  ewok.(none):/home/gblack/m5/multiarch

SConscript:
arch/alpha/ev5.cc:
dev/alpha_console.cc:
    Hand merged

--HG--
extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
2006-02-24 18:45:28 -05:00
Gabe Black
08637efadc Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type.
arch/alpha/alpha_memory.cc:
arch/alpha/isa/decoder.isa:
    Added news where faults are created.
arch/alpha/ev5.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==
arch/alpha/faults.cc:
arch/alpha/faults.hh:
    Changed Fault to be a RefCountingPtr
arch/alpha/isa/fp.isa:
    Added a new where a FloatEnableFault was created.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
    Added a new where an UnimplementedFault is created.
base/refcnt.hh:
    Added include of stddef.h for the NULL macro
cpu/base_dyn_inst.cc:
    Added a new where an UnimplementedOpcodeFault is created.
cpu/o3/alpha_cpu_impl.hh:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name()
cpu/o3/regfile.hh:
    Added new where UnimplementedOpcodeFaults are created.
cpu/simple/cpu.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created.
dev/alpha_console.cc:
    Added news where MachineCheckFaults are created.
dev/pcidev.hh:
    Added news where MachineCheckFaults are generated.
dev/sinic.cc:
    Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables.
kern/kernel_stats.cc:
    Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future.
kern/kernel_stats.hh:
    Commented out the declaration of _fault. when fault() is called, the fault increments its own stat.
sim/faults.cc:
sim/faults.hh:
    Changed Fault from a FaultBase * to a RefCountingPtr.

--HG--
extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
2006-02-24 01:51:45 -05:00
Ron Dreslinski
b6247c9ea7 Add support for multiple ports on the memory. Hook up simple cpu to memory.
Ready to start testing if I could fix the linking errors I can't ever seem to fix.

cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Add connecting of ports until builder can handle it.
mem/physical.cc:
    Add function to allocate a port in the object

    Remove some full_sys stuff untill needed
mem/physical.hh:
    Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
    Update the params
sim/process.cc:
    Make sure to use the right name (hopefully CPU constructor already called)

--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
2006-02-23 17:02:34 -05:00
Ali Saidi
e1c3acd91c Merge zizzer:/bk/m5
into  zeep.eecs.umich.edu:/z/saidi/work/m5.head

cpu/simple/cpu.cc:
    remove initCPU from constructor
dev/alpha_console.cc:
    we are panicing, so no need to return a fault

--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9
2006-02-23 15:06:06 -05:00
Ali Saidi
1166d4f0bf Get rid of the xc from the alphaAccess/alphaConsole backdoor device.
Now allocate an array of stacks indexed by cpu number which specify
cpu stacks and are initialized by cpu 0. Othe cpus spin waiting for
their stacks before continuing. This change *REQUIRES* a the new
console code to operate correctly.

arch/alpha/ev5.cc:
    Add cpuId to initCPU/initIPR functions
cpu/o3/cpu.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move the cpu initilization into an init() function since it now needs
    the CPU id which isn't known at construction
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
    instead of the bootstrap variables, add space for 64 cpu stacks in the
    alpha access structure.
sim/system.cc:
    start all cpus immediately rather than just the first one

--HG--
extra : convert_revision : 28c218af49d885a0f203ada419f16f25d5a3f37b
2006-02-23 14:50:16 -05:00
Ron Dreslinski
8fc06589cb Update functional memory to have a response event
Clean out old memory python files, move them into old_mem directory.  Maybe we should just delete them, they are under revision control.

Add new py files for new objects.

SConscript:
    Update because memory is just a header file now
base/chunk_generator.hh:
    Make Chunk Generator return the entire size if the chunk_size is set to zero.  Useful when trying to chunck on blocksize of memory, which can write large pieces of data.
cpu/simple/cpu.cc:
    Make sure to delete the pkt.
mem/physical.cc:
mem/physical.hh:
    Set up response event.
mem/port.cc:
    Rename rqst to req to conform to same standard naming convention.
python/m5/objects/PhysicalMemory.py:
    Update the params, inheritence

--HG--
extra : convert_revision : 857154ec256522baf423b715833930497999549b
2006-02-23 13:51:54 -05:00
Gabe Black
8d80fd1477 Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
2006-02-21 20:10:40 -05:00
Steve Reinhardt
8a753f6ae2 Move read/writeBlob functions to Port class;
clean up implementation a little.

SConscript:
    Add mem/port.cc
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move read/writeBlob functions to base Port class.
mem/port.hh:
    Implement read/writeBlob functions.
    No need for them to be virtual since the proxy
    object (now called TranslatingPort) is not a
    subclass of Port.
mem/port.cc:
    Implement read/writeBlob functions.

--HG--
extra : convert_revision : a3660eaa43a7c286aca962f17fa32fbd42bf1fa6
2006-02-21 11:27:53 -05:00
Ron Dreslinski
00be4e8510 Thanks to Ali, I was able to add chunk generation code in to handle a few cases. Still have some duplicated code we may want to revisit.
cpu/simple/cpu.cc:
    Thanks to Ali I found the chunk generator, although I still seem to be duplicating some code becuase the only difference between readBlob and writeBlob is the command in the packet.  Perhaps an access function with the command as a param would help with the duplication (sendBlob that takes a cmd (maybe).
mem/translating_port.cc:
    Using the chunck generator to break it up to be in page size chunks

--HG--
extra : convert_revision : cc2e4e60c76098655e469f81c89d2c7438350fdb
2006-02-21 03:32:42 -05:00
Ron Dreslinski
562efe214c Adding some definitons for read/write blob/string. I need to locate te code stever wrote to break up address ranges into blk/page size chunks.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Add read/write blob definitions, still need to break it up into blk size chunks (where was the code stever wrote for that?)
mem/physical.hh:
    Remove un-needed function (I think)
mem/port.hh:
    Default these virtual functions to panic unimplented
mem/translating_port.cc:
    Again handling read/write string properly.

    Need the stever code to break things into page size chunks yet
mem/translating_port.hh:
    Having trouble with the const declerator.  I will need to read how it works, for now it compiles if I remove it.

--HG--
extra : convert_revision : f174e06700daa9967958d18e01798270c90d6dac
2006-02-21 02:15:02 -05:00
Ron Dreslinski
75152fcaf7 Get simple cpu to compile.
Now I need to fix linking errors, probably due to missing function details in new memory objects.

cpu/exec_context.cc:
cpu/exec_context.hh:
    Fix constructor for SE mode
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Fix compilation errors

--HG--
extra : convert_revision : 6a58c0906340e10b654369c36f528fc17e3f19be
2006-02-21 01:01:16 -05:00
Gabe Black
463aa6d49d Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
2006-02-19 02:34:37 -05:00
Gabe Black
10c79efe55 Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d
2006-02-16 01:22:51 -05:00
Ron Dreslinski
d142788172 More compilation fixes.
Should we add a proxy_port that does the v->p address translation?
Should the proxy port return a fault on translation errors, if we add one?

arch/alpha/alpha_linux_process.cc:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
cpu/base.hh:
    Add a pointer to the memPort syscalls will use.  Should this be a proxy_port that does address translation?
cpu/exec_context.cc:
cpu/exec_context.hh:
    Remove functional memory from the exec context
cpu/simple/cpu.cc:
    Set the memPort to be used as the syscall port as the dcache port
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Syscalls use a memPort through the CPU now instead of a xc functional memory.
    Also, fix the fact that readStringFunctional doesn't return a fault... should proxy_port handle this because it is doing the translation?

--HG--
extra : convert_revision : 1f65318c6594301a75dc4dc0c99fdd436b094a7f
2006-02-15 22:05:23 -05:00
Steve Reinhardt
b8a2d1e5c7 More progress toward compiling... partly by
fixing things, partly by ignoring CPU models
that don't currently compile.

SConscript:
    Split sources for fast, simple, and o3 CPU models into
    separate source lists.  For now none of these are included
    in the base source list, so you won't get any CPU models
    at all... but we still can't compile the other stuff so
    it's not an issue.

    Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
    FunctionalMemory -> Memory
cpu/pc_event.hh:
    Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move Port functions into .cc file.
mem/port.hh:
    Make recvAddressRangesQuery panic by default instead
    of being abstract... do CPUs need to implement this?
mem/request.hh:
    Add prefetch flags.
sim/syscall_emul.hh:
    Start to fix...

--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
2006-02-15 17:52:49 -05:00
Kevin Lim
989292a0fa Update for new memory system. Uses the ports to access memory now. Also supports the response path of the new memory system, as well as retrying accesses.
cpu/simple/cpu.cc:
    Update for new memory system.  Supports using ports to access the memory system.  The IcacheMissStall/DcacheMissStall statuses have been changed to reflect the cache returning a response after a variable latency (due to hit/miss).  They are now DcacheWaitResponse/IcacheWaitResponse.  Also supports retrying accesses.

    For now the body of the copy functions are commented out.
cpu/simple/cpu.hh:
    Update for new memory system.

--HG--
extra : convert_revision : 5a80247537d98ed690f7b6119094d9f59b4c7d73
2006-02-03 15:21:06 -05:00
Gabe Black
2939a7089a byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
    Added the endianness namespace. This may change.
cpu/exec_context.hh:
    Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
    Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
    Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
    Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
    Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
    Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
    Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
    Forced LittleEndianness for lack of a better solution.

--HG--
extra : convert_revision : b95d3e1265a825e04bd77622a3ac09fbac6bd206
2006-02-03 00:16:44 -05:00
Ron Dreslinski
4c40848dcc Remove non-needed functions, fix return values of completion handler.
--HG--
extra : convert_revision : 7c0cb6b13ba68650d54cdc35779517e8c4b5e3ff
2006-01-31 15:03:04 -05:00
Ron Dreslinski
0d74f27313 More changes toward making simpleCpu use new port interface.
cpu/simple/cpu.cc:
    Initialize the ports, also add Request and Packet instead of MemReq.  Initial work at ICache read in place.
cpu/simple/cpu.hh:
    Need to call the completion handler when we see a recieve.

--HG--
extra : convert_revision : a52caee6f0ceb5d9ee1e5acca63a202f5ea71359
2006-01-31 15:00:09 -05:00
Ron Dreslinski
6c7fdb1be7 More include files, removing definition of SendResult whioch isn't needed anymore
cpu/simple/cpu.hh:
    Some needed includes
mem/port.hh:
    Now we removed the sendResult and replaced with void,tick,bool don't need it defined anymore

--HG--
extra : convert_revision : aea08ec299c41b9f9a5b0da7649cef0459315139
2006-01-31 14:42:42 -05:00
Ron Dreslinski
2f644efafa Fixed some void functions with returns, first stab at cpu ports.
cpu/simple/cpu.hh:
    Adding port definitions to simple cpu, still needs work.
mem/bus.hh:
    no return for void functions

--HG--
extra : convert_revision : 42e5bc16af187d3a46eb25a15b600a8a11b88cc5
2006-01-31 14:39:41 -05:00
Ron Dreslinski
ffc32970f6 Two small fixes for mem_req's and Probe path with MOSI/MOESI
cpu/simple/cpu.cc:
    Properly set the Instruction Read bit in the Memory Request

--HG--
extra : convert_revision : e1a4756f32718fd8ef3ac3db16625bd6d8f07cc5
2005-12-01 18:47:36 -05:00
Nathan Binkert
6e6422ab22 For SimpleCPU profiling code, only update the exec context's
profileNode if we got a new one

cpu/simple/cpu.cc:
    Only update the exec context's profileNode if we got a new one

--HG--
extra : convert_revision : a16a7410070b0d811032dc4b86b1368df913b2be
2005-11-20 17:55:11 -05:00
Nathan Binkert
0dcb288365 Cleanup the StackTrace interfaces and profile interfaces so they
are more efficient and reduce the number of new/delete calls

arch/alpha/stacktrace.cc:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
    - switch to using kernelSymtab instead of allSymtab which will be
    going away
    - if the stack adjustment doesn't make any sense, exit and push
    unknown so we don't get into an infinite loop or record garbage.
    - check to see if we've made too many iterations through the stack
    and panic to avoid an infinite loop
arch/alpha/stacktrace.hh:
    - Change the StackTrace code so that the class can more easily be
    cleaned out and reused to avoid extra allocations.
    - Allow trace() to accept a static instruction pointer so it can
    determine if the instruction is worth tracing.  This is moved from
    the CPU.
    - provide constants for special meaning PCs (user, console, unknown),
    instead of magic numbers
cpu/base.cc:
    only clear the profile if we have one
    include profile.hh here since base.hh doesn't do it anymore
cpu/base.hh:
    no need to include cpu/profile.hh here
cpu/profile.cc:
    use ProfileNode pointers instead of objects in the ChildList
    Consume a vector of addresses since that's really all we
    care about.
cpu/profile.hh:
    Keep pointers to ProfileNodes to reduce the size of these structures
    keep a StackTrace around so that we may reuse it.
    provide consume functions that use the new StackTrace trace interface
    one consume function is inline and tries to fastpath the no trace
    condition, it calls the outlined consume function if a trace is generated.
cpu/simple/cpu.cc:
    include cpu/profile.hh here since base.hh no longer does
    use the new FunctionProfile::consume interface
    (which contains the tracing functions)

--HG--
extra : convert_revision : 5a1d9265289a75f67a497b322926be1f8c2d8eb3
2005-11-20 17:44:58 -05:00
Nathan Binkert
a81c03737a Add new function profiling stuff, wrap the pc_sample stuff into it.
SConscript:
    Get rid of the pc_sample stuff and move to the new profiling stuff
base/traceflags.py:
    DPRINTF Stack stuff
cpu/base.cc:
cpu/base.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
    Add profiling stuff
kern/kernel_stats.hh:
    Use a smart pointer
sim/system.cc:
sim/system.hh:
    Create a new symbol table that has all of the symbols for a
    particular system
util/stats/categories.py:
    change around the categories, add categories for function
    profiling stuff
util/stats/profile.py:
    No profile parsing and display code to deal with function
    profiling stuff, graph, dot, and text outputs.

--HG--
extra : convert_revision : b3de0cdc8bd468e42647966e2640ae009bda9eb8
2005-10-18 19:07:42 -04:00