2006-05-16 23:36:50 +02:00
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Steve Reinhardt
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2006-05-16 23:36:50 +02:00
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*/
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#include "arch/utility.hh"
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2006-10-28 10:44:05 +02:00
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#include "arch/faults.hh"
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2006-05-16 23:36:50 +02:00
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/stats/events.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/profile.hh"
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#include "cpu/simple/base.hh"
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2006-06-07 21:29:53 +02:00
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#include "cpu/simple_thread.hh"
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2006-05-16 23:36:50 +02:00
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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2006-06-07 21:29:53 +02:00
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#include "cpu/thread_context.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet.hh"
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2006-06-07 21:29:53 +02:00
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#include "sim/byteswap.hh"
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2006-05-16 23:36:50 +02:00
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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2006-07-13 02:22:07 +02:00
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#include "sim/system.hh"
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2006-05-16 23:36:50 +02:00
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#if FULL_SYSTEM
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2006-11-08 04:34:34 +01:00
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#include "arch/kernel_stats.hh"
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2006-05-16 23:36:50 +02:00
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#include "arch/stacktrace.hh"
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2006-11-08 04:34:34 +01:00
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#include "arch/tlb.hh"
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2006-05-16 23:36:50 +02:00
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#include "arch/vtophys.hh"
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2006-11-08 02:26:45 +01:00
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#include "base/remote_gdb.hh"
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2006-05-16 23:36:50 +02:00
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#else // !FULL_SYSTEM
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#include "mem/mem_object.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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using namespace TheISA;
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BaseSimpleCPU::BaseSimpleCPU(Params *p)
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2007-05-31 22:01:41 +02:00
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: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
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2006-05-16 23:36:50 +02:00
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{
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#if FULL_SYSTEM
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2006-06-07 21:29:53 +02:00
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thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
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2006-05-16 23:36:50 +02:00
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#else
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2006-06-07 21:29:53 +02:00
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thread = new SimpleThread(this, /* thread_num */ 0, p->process,
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2007-08-27 05:24:18 +02:00
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p->itb, p->dtb, /* asid */ 0);
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2006-05-16 23:36:50 +02:00
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#endif // !FULL_SYSTEM
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2007-04-16 17:31:54 +02:00
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thread->setStatus(ThreadContext::Unallocated);
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2006-06-05 04:13:42 +02:00
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2006-06-07 21:29:53 +02:00
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tc = thread->getTC();
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2006-05-16 23:36:50 +02:00
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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2006-06-06 23:32:21 +02:00
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threadContexts.push_back(tc);
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2007-05-18 19:42:50 +02:00
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2007-10-18 19:15:08 +02:00
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cpuId = tc->readCpuId();
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2007-05-18 19:42:50 +02:00
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fetchOffset = 0;
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stayAtPC = false;
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2006-05-16 23:36:50 +02:00
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}
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BaseSimpleCPU::~BaseSimpleCPU()
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{
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}
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void
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BaseSimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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BaseSimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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icacheRetryCycles
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.name(name() + ".icache_retry_cycles")
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.desc("ICache total retry cycles")
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.prereq(icacheRetryCycles)
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;
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dcacheRetryCycles
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.name(name() + ".dcache_retry_cycles")
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.desc("DCache total retry cycles")
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.prereq(dcacheRetryCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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}
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void
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BaseSimpleCPU::resetStats()
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{
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2006-10-01 05:43:23 +02:00
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// startNumInst = numInst;
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2006-05-16 23:36:50 +02:00
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// notIdleFraction = (_status != Idle);
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}
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void
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BaseSimpleCPU::serialize(ostream &os)
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{
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BaseCPU::serialize(os);
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2006-07-12 23:11:57 +02:00
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// SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc.0", name()));
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2006-06-07 21:29:53 +02:00
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thread->serialize(os);
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2006-05-16 23:36:50 +02:00
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}
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void
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BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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BaseCPU::unserialize(cp, section);
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2006-07-12 23:11:57 +02:00
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// UNSERIALIZE_SCALAR(inst);
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thread->unserialize(cp, csprintf("%s.xc.0", section));
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2006-05-16 23:36:50 +02:00
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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Fault
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BaseSimpleCPU::copySrcTranslate(Addr src)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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int offset = src & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(src & PageMask) != ((src + blk_size) & PageMask) &&
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(src >> 40) != 0xfffffc) {
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warn("Copied block source spans pages %x.", src);
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no_warn = false;
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}
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address
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2006-06-07 21:29:53 +02:00
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Fault fault = thread->translateDataReadReq(req);
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2006-05-16 23:36:50 +02:00
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if (fault == NoFault) {
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2006-06-07 21:29:53 +02:00
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thread->copySrcAddr = src;
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thread->copySrcPhysAddr = memReq->paddr + offset;
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2006-05-16 23:36:50 +02:00
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} else {
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assert(!fault->isAlignmentFault());
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2006-06-07 21:29:53 +02:00
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thread->copySrcAddr = 0;
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thread->copySrcPhysAddr = 0;
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2006-05-16 23:36:50 +02:00
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}
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return fault;
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#else
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return NoFault;
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#endif
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}
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Fault
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BaseSimpleCPU::copy(Addr dest)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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uint8_t data[blk_size];
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2006-06-07 21:29:53 +02:00
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//assert(thread->copySrcAddr);
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2006-05-16 23:36:50 +02:00
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int offset = dest & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(dest & PageMask) != ((dest + blk_size) & PageMask) &&
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(dest >> 40) != 0xfffffc) {
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no_warn = false;
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warn("Copied block destination spans pages %x. ", dest);
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}
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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2006-06-07 21:29:53 +02:00
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Fault fault = thread->translateDataWriteReq(req);
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2006-05-16 23:36:50 +02:00
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if (fault == NoFault) {
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Addr dest_addr = memReq->paddr + offset;
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// Need to read straight from memory since we have more than 8 bytes.
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2006-06-07 21:29:53 +02:00
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memReq->paddr = thread->copySrcPhysAddr;
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thread->mem->read(memReq, data);
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2006-05-16 23:36:50 +02:00
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memReq->paddr = dest_addr;
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2006-06-07 21:29:53 +02:00
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thread->mem->write(memReq, data);
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2006-05-16 23:36:50 +02:00
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if (dcacheInterface) {
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memReq->cmd = Copy;
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memReq->completionEvent = NULL;
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2006-06-07 21:29:53 +02:00
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memReq->paddr = thread->copySrcPhysAddr;
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2006-05-16 23:36:50 +02:00
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memReq->dest = dest_addr;
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memReq->size = 64;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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dcacheInterface->access(memReq);
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}
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}
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else
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assert(!fault->isAlignmentFault());
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return fault;
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#else
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panic("copy not implemented");
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return NoFault;
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#endif
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}
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#if FULL_SYSTEM
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Addr
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BaseSimpleCPU::dbg_vtophys(Addr addr)
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{
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2006-06-06 23:32:21 +02:00
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return vtophys(tc, addr);
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2006-05-16 23:36:50 +02:00
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}
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#endif // FULL_SYSTEM
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#if FULL_SYSTEM
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void
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BaseSimpleCPU::post_interrupt(int int_num, int index)
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{
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BaseCPU::post_interrupt(int_num, index);
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2006-06-07 21:29:53 +02:00
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if (thread->status() == ThreadContext::Suspended) {
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2007-03-13 05:05:52 +01:00
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DPRINTF(Quiesce,"Suspended Processor awoke\n");
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2006-06-07 21:29:53 +02:00
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thread->activate();
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2006-05-16 23:36:50 +02:00
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}
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}
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#endif // FULL_SYSTEM
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void
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BaseSimpleCPU::checkForInterrupts()
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{
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#if FULL_SYSTEM
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2007-01-26 18:51:07 +01:00
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if (check_interrupts(tc)) {
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2006-11-03 08:25:39 +01:00
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Fault interrupt = interrupts.getInterrupt(tc);
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2006-05-16 23:36:50 +02:00
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2006-11-03 08:25:39 +01:00
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if (interrupt != NoFault) {
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2006-11-13 02:15:30 +01:00
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interrupts.updateIntrInfo(tc);
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2006-11-03 08:25:39 +01:00
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interrupt->invoke(tc);
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2006-05-16 23:36:50 +02:00
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}
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}
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#endif
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}
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Fault
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2006-05-31 04:30:42 +02:00
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BaseSimpleCPU::setupFetchRequest(Request *req)
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2006-05-16 23:36:50 +02:00
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{
|
2007-06-01 20:16:58 +02:00
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Addr threadPC = thread->readPC();
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2007-05-31 22:01:41 +02:00
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2006-05-16 23:36:50 +02:00
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// set up memory request for instruction fetch
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2006-09-01 02:51:30 +02:00
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#if ISA_HAS_DELAY_SLOT
|
2007-05-31 22:01:41 +02:00
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|
|
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
|
2006-06-07 21:29:53 +02:00
|
|
|
thread->readNextPC(),thread->readNextNPC());
|
2006-09-01 02:51:30 +02:00
|
|
|
#else
|
2007-06-13 22:09:03 +02:00
|
|
|
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
|
2006-09-01 02:51:30 +02:00
|
|
|
thread->readNextPC());
|
2006-06-11 20:38:14 +02:00
|
|
|
#endif
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-06-13 22:09:03 +02:00
|
|
|
Addr fetchPC = (threadPC & PCMask) + fetchOffset;
|
|
|
|
req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2006-06-07 21:29:53 +02:00
|
|
|
Fault fault = thread->translateInstReq(req);
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
BaseSimpleCPU::preExecute()
|
|
|
|
{
|
|
|
|
// maintain $r0 semantics
|
2006-06-07 21:29:53 +02:00
|
|
|
thread->setIntReg(ZeroReg, 0);
|
2006-05-16 23:36:50 +02:00
|
|
|
#if THE_ISA == ALPHA_ISA
|
2006-06-07 21:29:53 +02:00
|
|
|
thread->setFloatReg(ZeroReg, 0.0);
|
2006-05-16 23:36:50 +02:00
|
|
|
#endif // ALPHA_ISA
|
|
|
|
|
|
|
|
// check for instruction-count-based events
|
|
|
|
comInstEventQueue[0]->serviceEvents(numInst);
|
|
|
|
|
|
|
|
// decode the instruction
|
|
|
|
inst = gtoh(inst);
|
2007-05-18 19:42:50 +02:00
|
|
|
|
2006-10-16 03:04:14 +02:00
|
|
|
//If we're not in the middle of a macro instruction
|
|
|
|
if (!curMacroStaticInst) {
|
2007-05-18 19:42:50 +02:00
|
|
|
|
2007-03-13 17:13:21 +01:00
|
|
|
StaticInstPtr instPtr = NULL;
|
|
|
|
|
|
|
|
//Predecode, ie bundle up an ExtMachInst
|
2007-03-15 03:47:42 +01:00
|
|
|
//This should go away once the constructor can be set up properly
|
|
|
|
predecoder.setTC(thread->getTC());
|
|
|
|
//If more fetch data is needed, pass it in.
|
2007-06-19 20:17:34 +02:00
|
|
|
Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
|
|
|
|
//if(predecoder.needMoreBytes())
|
|
|
|
predecoder.moreBytes(thread->readPC(), fetchPC, inst);
|
|
|
|
//else
|
|
|
|
// predecoder.process();
|
2007-05-18 19:42:50 +02:00
|
|
|
|
|
|
|
//If an instruction is ready, decode it. Otherwise, we'll have to
|
|
|
|
//fetch beyond the MachInst at the current pc.
|
|
|
|
if (predecoder.extMachInstReady()) {
|
|
|
|
#if THE_ISA == X86_ISA
|
|
|
|
thread->setNextPC(thread->readPC() + predecoder.getInstSize());
|
|
|
|
#endif // X86_ISA
|
|
|
|
stayAtPC = false;
|
2007-06-14 22:52:19 +02:00
|
|
|
instPtr = StaticInst::decode(predecoder.getExtMachInst(),
|
|
|
|
thread->readPC());
|
2007-05-18 19:42:50 +02:00
|
|
|
} else {
|
|
|
|
stayAtPC = true;
|
|
|
|
fetchOffset += sizeof(MachInst);
|
|
|
|
}
|
2007-03-13 17:13:21 +01:00
|
|
|
|
|
|
|
//If we decoded an instruction and it's microcoded, start pulling
|
|
|
|
//out micro ops
|
2007-06-12 18:21:47 +02:00
|
|
|
if (instPtr && instPtr->isMacroop()) {
|
2006-10-16 03:04:14 +02:00
|
|
|
curMacroStaticInst = instPtr;
|
2006-10-29 10:04:50 +01:00
|
|
|
curStaticInst = curMacroStaticInst->
|
2007-06-12 18:21:47 +02:00
|
|
|
fetchMicroop(thread->readMicroPC());
|
2006-10-16 21:56:46 +02:00
|
|
|
} else {
|
|
|
|
curStaticInst = instPtr;
|
2006-10-16 03:04:14 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
//Read the next micro op from the macro op
|
2006-10-29 10:04:50 +01:00
|
|
|
curStaticInst = curMacroStaticInst->
|
2007-06-12 18:21:47 +02:00
|
|
|
fetchMicroop(thread->readMicroPC());
|
2006-10-16 03:04:14 +02:00
|
|
|
}
|
|
|
|
|
2007-03-13 17:13:21 +01:00
|
|
|
//If we decoded an instruction this "tick", record information about it.
|
|
|
|
if(curStaticInst)
|
|
|
|
{
|
2007-06-04 21:53:04 +02:00
|
|
|
#if TRACING_ON
|
2007-07-29 05:30:43 +02:00
|
|
|
traceData = tracer->getInstRecord(curTick, tc, curStaticInst,
|
2007-03-13 17:13:21 +01:00
|
|
|
thread->readPC());
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-03-13 17:13:21 +01:00
|
|
|
DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
|
|
|
|
curStaticInst->getName(), curStaticInst->machInst);
|
2007-06-04 21:53:04 +02:00
|
|
|
#endif // TRACING_ON
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
#if FULL_SYSTEM
|
2007-03-13 17:13:21 +01:00
|
|
|
thread->setInst(inst);
|
2006-05-16 23:36:50 +02:00
|
|
|
#endif // FULL_SYSTEM
|
2007-03-13 17:13:21 +01:00
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
BaseSimpleCPU::postExecute()
|
|
|
|
{
|
|
|
|
#if FULL_SYSTEM
|
2007-09-25 02:39:56 +02:00
|
|
|
if (thread->profile && curStaticInst) {
|
2006-11-08 19:55:48 +01:00
|
|
|
bool usermode = TheISA::inUserMode(tc);
|
2006-06-07 21:29:53 +02:00
|
|
|
thread->profilePC = usermode ? 1 : thread->readPC();
|
2007-09-25 02:39:56 +02:00
|
|
|
ProfileNode *node = thread->profile->consume(tc, curStaticInst);
|
2006-05-16 23:36:50 +02:00
|
|
|
if (node)
|
2006-06-07 21:29:53 +02:00
|
|
|
thread->profileNode = node;
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (curStaticInst->isMemRef()) {
|
|
|
|
numMemRefs++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (curStaticInst->isLoad()) {
|
|
|
|
++numLoad;
|
|
|
|
comLoadEventQueue[0]->serviceEvents(numLoad);
|
|
|
|
}
|
|
|
|
|
2006-06-07 21:29:53 +02:00
|
|
|
traceFunctions(thread->readPC());
|
2006-05-26 20:33:43 +02:00
|
|
|
|
|
|
|
if (traceData) {
|
2007-02-11 00:14:50 +01:00
|
|
|
traceData->dump();
|
|
|
|
delete traceData;
|
|
|
|
traceData = NULL;
|
2006-05-26 20:33:43 +02:00
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
BaseSimpleCPU::advancePC(Fault fault)
|
|
|
|
{
|
2007-05-18 19:42:50 +02:00
|
|
|
//Since we're moving to a new pc, zero out the offset
|
|
|
|
fetchOffset = 0;
|
2006-05-16 23:36:50 +02:00
|
|
|
if (fault != NoFault) {
|
2007-01-17 01:12:33 +01:00
|
|
|
curMacroStaticInst = StaticInst::nullStaticInstPtr;
|
2007-10-03 07:21:38 +02:00
|
|
|
predecoder.reset();
|
2006-06-06 23:32:21 +02:00
|
|
|
fault->invoke(tc);
|
2007-01-25 19:43:46 +01:00
|
|
|
thread->setMicroPC(0);
|
|
|
|
thread->setNextMicroPC(1);
|
2007-05-18 19:42:50 +02:00
|
|
|
} else {
|
2006-10-16 03:04:14 +02:00
|
|
|
//If we're at the last micro op for this instruction
|
2007-06-12 18:21:47 +02:00
|
|
|
if (curStaticInst && curStaticInst->isLastMicroop()) {
|
2006-10-16 03:04:14 +02:00
|
|
|
//We should be working with a macro op
|
|
|
|
assert(curMacroStaticInst);
|
|
|
|
//Close out this macro op, and clean up the
|
|
|
|
//microcode state
|
2006-10-16 21:56:46 +02:00
|
|
|
curMacroStaticInst = StaticInst::nullStaticInstPtr;
|
2006-10-16 03:04:14 +02:00
|
|
|
thread->setMicroPC(0);
|
2006-10-16 21:56:46 +02:00
|
|
|
thread->setNextMicroPC(1);
|
2006-10-16 03:04:14 +02:00
|
|
|
}
|
|
|
|
//If we're still in a macro op
|
|
|
|
if (curMacroStaticInst) {
|
|
|
|
//Advance the micro pc
|
2006-10-16 21:56:46 +02:00
|
|
|
thread->setMicroPC(thread->readNextMicroPC());
|
2006-10-16 03:04:14 +02:00
|
|
|
//Advance the "next" micro pc. Note that there are no delay
|
|
|
|
//slots, and micro ops are "word" addressed.
|
2006-10-16 21:56:46 +02:00
|
|
|
thread->setNextMicroPC(thread->readNextMicroPC() + 1);
|
2006-10-16 03:04:14 +02:00
|
|
|
} else {
|
|
|
|
// go to the next instruction
|
|
|
|
thread->setPC(thread->readNextPC());
|
|
|
|
thread->setNextPC(thread->readNextNPC());
|
|
|
|
thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
|
|
|
|
assert(thread->readNextPC() != thread->readNextNPC());
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
Addr oldpc;
|
|
|
|
do {
|
2006-06-07 21:29:53 +02:00
|
|
|
oldpc = thread->readPC();
|
2006-06-06 23:32:21 +02:00
|
|
|
system->pcEventQueue.service(tc);
|
2006-06-07 21:29:53 +02:00
|
|
|
} while (oldpc != thread->readPC());
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2007-11-15 09:10:41 +01:00
|
|
|
/*Fault
|
2007-11-13 22:58:16 +01:00
|
|
|
BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
|
|
|
|
{
|
|
|
|
// translate to physical address
|
|
|
|
Fault fault = NoFault;
|
|
|
|
int CacheID = Op & 0x3; // Lower 3 bits identify Cache
|
|
|
|
int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
|
|
|
|
if(CacheID > 1)
|
|
|
|
{
|
|
|
|
warn("CacheOps not implemented for secondary/tertiary caches\n");
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
switch(CacheOP)
|
|
|
|
{ // Fill Packet Type
|
|
|
|
case 0: warn("Invalidate Cache Op\n");
|
|
|
|
break;
|
|
|
|
case 1: warn("Index Load Tag Cache Op\n");
|
|
|
|
break;
|
|
|
|
case 2: warn("Index Store Tag Cache Op\n");
|
|
|
|
break;
|
|
|
|
case 4: warn("Hit Invalidate Cache Op\n");
|
|
|
|
break;
|
|
|
|
case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
|
|
|
|
break;
|
|
|
|
case 6: warn("Hit Writeback\n");
|
|
|
|
break;
|
|
|
|
case 7: warn("Fetch & Lock Cache Op\n");
|
|
|
|
break;
|
|
|
|
default: warn("Unimplemented Cache Op\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return fault;
|
2007-11-15 09:10:41 +01:00
|
|
|
}*/
|