2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-10-14 00:21:40 +02:00
sim_seconds 51.821889 # Number of seconds simulated
sim_ticks 51821888787500 # Number of ticks simulated
final_tick 51821888787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-10-19 12:20:04 +02:00
host_inst_rate 1225071 # Simulator instruction rate (inst/s)
host_op_rate 1439562 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 73854998542 # Simulator tick rate (ticks/s)
host_mem_usage 679352 # Number of bytes of host memory used
host_seconds 701.67 # Real time elapsed on the host
2016-10-14 00:21:40 +02:00
sim_insts 859596485 # Number of instructions simulated
sim_ops 1010098639 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 216448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 219200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5035380 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 42867656 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 394432 # Number of bytes read from this memory
system.physmem.bytes_read::total 48733116 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5035380 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5035380 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 69868992 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
2016-10-14 00:21:40 +02:00
system.physmem.bytes_written::total 69889572 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 3382 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3425 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 119085 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 669820 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6163 # Number of read requests responded to by this memory
system.physmem.num_reads::total 801875 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1091703 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
2016-10-14 00:21:40 +02:00
system.physmem.num_writes::total 1094276 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 4177 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 4230 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 97167 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 827211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 7611 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 940396 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 97167 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 97167 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1348253 # Write bandwidth from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.physmem.bw_write::total 1348650 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1348253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 4177 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 4230 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 97167 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 827609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 7611 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2289046 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 801875 # Number of read requests accepted
system.physmem.writeReqs 1094276 # Number of write requests accepted
system.physmem.readBursts 801875 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1094276 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 51277952 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 42048 # Total number of bytes read from write queue
system.physmem.bytesWritten 69886912 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 48733116 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 69889572 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 657 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2265 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-10-14 00:21:40 +02:00
system.physmem.perBankRdBursts::0 50164 # Per bank write bursts
system.physmem.perBankRdBursts::1 52640 # Per bank write bursts
system.physmem.perBankRdBursts::2 46199 # Per bank write bursts
system.physmem.perBankRdBursts::3 47700 # Per bank write bursts
system.physmem.perBankRdBursts::4 47678 # Per bank write bursts
system.physmem.perBankRdBursts::5 54947 # Per bank write bursts
system.physmem.perBankRdBursts::6 45482 # Per bank write bursts
system.physmem.perBankRdBursts::7 44174 # Per bank write bursts
system.physmem.perBankRdBursts::8 47146 # Per bank write bursts
system.physmem.perBankRdBursts::9 89983 # Per bank write bursts
system.physmem.perBankRdBursts::10 47048 # Per bank write bursts
system.physmem.perBankRdBursts::11 49101 # Per bank write bursts
system.physmem.perBankRdBursts::12 43837 # Per bank write bursts
system.physmem.perBankRdBursts::13 45399 # Per bank write bursts
system.physmem.perBankRdBursts::14 43891 # Per bank write bursts
system.physmem.perBankRdBursts::15 45829 # Per bank write bursts
system.physmem.perBankWrBursts::0 68109 # Per bank write bursts
system.physmem.perBankWrBursts::1 72083 # Per bank write bursts
system.physmem.perBankWrBursts::2 69263 # Per bank write bursts
system.physmem.perBankWrBursts::3 69948 # Per bank write bursts
system.physmem.perBankWrBursts::4 67942 # Per bank write bursts
system.physmem.perBankWrBursts::5 73995 # Per bank write bursts
system.physmem.perBankWrBursts::6 66206 # Per bank write bursts
system.physmem.perBankWrBursts::7 65273 # Per bank write bursts
system.physmem.perBankWrBursts::8 68509 # Per bank write bursts
system.physmem.perBankWrBursts::9 70672 # Per bank write bursts
system.physmem.perBankWrBursts::10 68078 # Per bank write bursts
system.physmem.perBankWrBursts::11 68626 # Per bank write bursts
system.physmem.perBankWrBursts::12 64922 # Per bank write bursts
system.physmem.perBankWrBursts::13 66812 # Per bank write bursts
system.physmem.perBankWrBursts::14 65438 # Per bank write bursts
system.physmem.perBankWrBursts::15 66107 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-10-14 00:21:40 +02:00
system.physmem.numWrRetry 528 # Number of times write queue was full causing retry
system.physmem.totGap 51821885925500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.readPktSize::6 758759 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-10-14 00:21:40 +02:00
system.physmem.writePktSize::6 1091703 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 767795 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 27710 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 516 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 322 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 453 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 438 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 573 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 470 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 924 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 568 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 268 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 279 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 120 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 101 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 79 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-10-14 00:21:40 +02:00
system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 34869 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 57710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 61714 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 64549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 61650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 60651 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 63213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 64819 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 63587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 67440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 65819 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 62330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 60766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 60977 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 60110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 59233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 58775 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1663 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1421 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1205 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 853 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 815 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 823 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 783 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 742 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 685 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 732 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 715 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 977 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 1097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1188 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 1099 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 664 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 1235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 2021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 1432 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 593 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 1157 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 494449 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 245.049629 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 147.402723 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 288.016754 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 219085 44.31% 44.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 131738 26.64% 70.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 43693 8.84% 79.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 22796 4.61% 84.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 15362 3.11% 87.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 9595 1.94% 89.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7428 1.50% 90.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 5929 1.20% 92.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 38823 7.85% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 494449 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 57195 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 14.008130 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 134.294281 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 57192 99.99% 99.99% # Reads before turning the bus around for writes
2016-07-21 18:19:18 +02:00
system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
2016-02-24 10:16:59 +01:00
system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
2016-10-14 00:21:40 +02:00
system.physmem.rdPerTurnAround::total 57195 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 57195 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.092281 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.359425 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 8.356307 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 44576 77.94% 77.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 9441 16.51% 94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 730 1.28% 95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 284 0.50% 96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 871 1.52% 97.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 293 0.51% 98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 48 0.08% 98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 36 0.06% 98.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 15 0.03% 98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 17 0.03% 98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 14 0.02% 98.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 33 0.06% 98.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 518 0.91% 99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 69 0.12% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 50 0.09% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 58 0.10% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 36 0.06% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.01% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 3 0.01% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.00% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 5 0.01% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.00% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 17 0.03% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 4 0.01% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.00% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 5 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 20 0.03% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 6 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 3 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 5 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 57195 # Writes before turning the bus around for reads
system.physmem.totQLat 29399013585 # Total ticks spent queuing
system.physmem.totMemAccLat 44421851085 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4006090000 # Total ticks spent in databus transfers
system.physmem.avgQLat 36692.90 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-10-14 00:21:40 +02:00
system.physmem.avgMemAccLat 55442.90 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
2014-10-30 05:50:15 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2014-10-30 05:50:15 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2016-10-14 00:21:40 +02:00
system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing
system.physmem.readRowHits 600273 # Number of row buffer hits during reads
system.physmem.writeRowHits 798478 # Number of row buffer hits during writes
system.physmem.readRowHitRate 74.92 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes
system.physmem.avgGap 27330041.71 # Average gap between requests
system.physmem.pageHitRate 73.88 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1812881700 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 963565680 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2777345760 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 2885715180 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 48801801360.000008 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 38319920670 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 3025839840 # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy 94040362440 # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy 72590911200 # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy 12330316288695 # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy 12595556394525 # Total energy per rank (pJ)
system.physmem_0.averagePower 243.054753 # Core power per rank (mW)
system.physmem_0.totalIdleTime 51729925726993 # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE 5744734750 # Time in different power states
system.physmem_0.memoryStateTime::REF 20754236000 # Time in different power states
system.physmem_0.memoryStateTime::SREF 51334657894500 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 189038733198 # Time in different power states
system.physmem_0.memoryStateTime::ACT 65464048007 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 206229141045 # Time in different power states
system.physmem_1.actEnergy 1717491300 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 912868275 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2943350760 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 2814436080 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 46544843280.000008 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 38176673400 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2758502400 # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy 87988375470 # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy 69794301120 # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy 12334956932460 # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy 12588629106345 # Total energy per rank (pJ)
system.physmem_1.averagePower 242.921078 # Core power per rank (mW)
system.physmem_1.totalIdleTime 51730316233255 # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE 5091528742 # Time in different power states
system.physmem_1.memoryStateTime::REF 19793960000 # Time in different power states
system.physmem_1.memoryStateTime::SREF 51356223942250 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 181755962683 # Time in different power states
system.physmem_1.memoryStateTime::ACT 66066776003 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 192956617822 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
2016-10-14 00:21:40 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 195978 # Table walker walks requested
system.cpu.dtb.walker.walksLong 195978 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13491 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152311 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 195958 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 0.153094 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 48.869782 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047 195956 100.00% 100.00% # Table walker wait (enqueue to first request) latency
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.walkWaitTime::total 195958 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 165822 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23748.733582 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 19720.854851 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 19654.042010 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 164137 98.98% 98.98% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 1390 0.84% 99.82% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 75 0.05% 99.87% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 54 0.03% 99.90% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 79 0.05% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 19 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 53 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 165822 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples -2782551036 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.846086 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.360866 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 -428273296 15.39% 15.39% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1 -2354277740 84.61% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total -2782551036 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 152312 91.86% 91.86% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 13491 8.14% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 165803 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 195978 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 195978 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 165803 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 165803 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 361781 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.read_hits 161602593 # DTB read hits
system.cpu.dtb.read_misses 145506 # DTB read misses
system.cpu.dtb.write_hits 146806893 # DTB write hits
system.cpu.dtb.write_misses 50472 # DTB write misses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-10-14 00:21:40 +02:00
system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 72949 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2016-10-14 00:21:40 +02:00
system.cpu.dtb.prefetch_faults 7287 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-10-14 00:21:40 +02:00
system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 161748099 # DTB read accesses
system.cpu.dtb.write_accesses 146857365 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-10-14 00:21:40 +02:00
system.cpu.dtb.hits 308409486 # DTB hits
system.cpu.dtb.misses 195978 # DTB misses
system.cpu.dtb.accesses 308605464 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 120718 # Table walker walks requested
system.cpu.itb.walker.walksLong 120718 # Table walker walks initiated with long descriptors
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.walksLongTerminationLevel::Level3 108838 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples 120718 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0 120718 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 120718 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 109957 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 27485.576180 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 23297.926209 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 24382.701456 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 107960 98.18% 98.18% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 1664 1.51% 99.70% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 68 0.06% 99.76% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 86 0.08% 99.84% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 74 0.07% 99.90% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 23 0.02% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 5 0.00% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 76 0.07% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 109957 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 108838 98.98% 98.98% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 109957 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120718 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 120718 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-10-14 00:21:40 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109957 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 109957 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 230675 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 860126625 # ITB inst hits
system.cpu.itb.inst_misses 120718 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-10-14 00:21:40 +02:00
system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 52157 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-10-14 00:21:40 +02:00
system.cpu.itb.inst_accesses 860247343 # ITB inst accesses
system.cpu.itb.hits 860126625 # DTB hits
system.cpu.itb.misses 120718 # DTB misses
system.cpu.itb.accesses 860247343 # DTB accesses
system.cpu.numPwrStateTransitions 32322 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 16161 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean 3111677574.020791 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 60407510991.245888 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows 6870 42.51% 42.51% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-10-14 00:21:40 +02:00
system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total 16161 # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON 1534067513750 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50287821273750 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 103643777575 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-10-14 00:21:40 +02:00
system.cpu.kern.inst.quiesce 16161 # number of quiesce instructions executed
system.cpu.committedInsts 859596485 # Number of instructions committed
system.cpu.committedOps 1010098639 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 927989339 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 896850 # Number of float alu accesses
system.cpu.num_func_calls 51273640 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 130821573 # number of instructions that are conditional controls
system.cpu.num_int_insts 927989339 # number of integer instructions
system.cpu.num_fp_insts 896850 # number of float instructions
system.cpu.num_int_register_reads 1348541336 # number of times the integer registers were read
system.cpu.num_int_register_writes 735865236 # number of times the integer registers were written
system.cpu.num_fp_register_reads 1446705 # number of times the floating registers were read
system.cpu.num_fp_register_writes 758956 # number of times the floating registers were written
system.cpu.num_cc_register_reads 224361660 # number of times the CC registers were read
system.cpu.num_cc_register_writes 223761478 # number of times the CC registers were written
system.cpu.num_mem_refs 308390268 # number of memory refs
system.cpu.num_load_insts 161593947 # Number of load instructions
system.cpu.num_store_insts 146796321 # Number of store instructions
system.cpu.num_idle_cycles 100575642547.498062 # Number of idle cycles
system.cpu.num_busy_cycles 3068135027.501941 # Number of busy cycles
system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.970397 # Percentage of idle cycles
system.cpu.Branches 191892206 # Number of branches fetched
2014-10-30 05:50:15 +01:00
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::IntAlu 699904687 69.25% 69.25% # Class of executed instruction
system.cpu.op_class::IntMult 2167959 0.21% 69.47% # Class of executed instruction
system.cpu.op_class::IntDiv 97409 0.01% 69.48% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::FloatAdd 8 0.00% 69.48% # Class of executed instruction
system.cpu.op_class::FloatCmp 13 0.00% 69.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 21 0.00% 69.48% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::FloatMultAcc 0 0.00% 69.48% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::FloatMisc 111537 0.01% 69.49% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 69.49% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction
2016-10-19 12:20:04 +02:00
system.cpu.op_class::MemRead 161481542 15.98% 85.46% # Class of executed instruction
system.cpu.op_class::MemWrite 146123455 14.46% 99.92% # Class of executed instruction
system.cpu.op_class::FloatMemRead 112405 0.01% 99.93% # Class of executed instruction
system.cpu.op_class::FloatMemWrite 672866 0.07% 100.00% # Class of executed instruction
2014-10-30 05:50:15 +01:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2016-10-14 00:21:40 +02:00
system.cpu.op_class::total 1010671903 # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 9712865 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 298498000 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9713377 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 30.730610 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu.dcache.tags.tag_accesses 1243014374 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1243014374 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 151150245 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 151150245 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 139360023 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 139360023 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 383359 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 383359 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 333234 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 333234 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475622 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3475622 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3766718 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3766718 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 290843502 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 290843502 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 291226861 # number of overall hits
system.cpu.dcache.overall_hits::total 291226861 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 5063029 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 5063029 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2070213 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2070213 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1203887 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1203887 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1226147 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1226147 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 292765 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 292765 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 8359389 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 8359389 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9563276 # number of overall misses
system.cpu.dcache.overall_misses::total 9563276 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 86479051000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 86479051000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 64029512000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 64029512000 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24965286000 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 24965286000 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4461300000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 4461300000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 175473849000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 175473849000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 175473849000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 175473849000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 156213274 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 156213274 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 141430236 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 141430236 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587246 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1587246 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559381 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1559381 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768387 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3768387 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766720 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3766720 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 299202891 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 299202891 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 300790137 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 300790137 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032411 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032411 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014638 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.014638 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758475 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.758475 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786304 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.786304 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077690 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077690 # miss rate for LoadLockedReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.027939 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.027939 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.031794 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.031794 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17080.496873 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17080.496873 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30928.948857 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30928.948857 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20360.760985 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20360.760985 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15238.501870 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15238.501870 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20991.229024 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20991.229024 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18348.717427 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18348.717427 # average overall miss latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.dcache.writebacks::writebacks 7498102 # number of writebacks
system.cpu.dcache.writebacks::total 7498102 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21612 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 21612 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21289 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 21289 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70591 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 70591 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 42901 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 42901 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 42901 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 42901 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5041417 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5041417 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2048924 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2048924 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203533 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1203533 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1226147 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1226147 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222174 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 222174 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 8316488 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 8316488 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9520021 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9520021 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80551413000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 80551413000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61232027000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61232027000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21569596000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21569596000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23739139000 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23739139000 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3061958500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3061958500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165522579000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 165522579000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187092175000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 187092175000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032273 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032273 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014487 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014487 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758252 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758252 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786304 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786304 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058957 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058957 # mshr miss rate for LoadLockedReq accesses
2016-07-21 18:19:18 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
2016-10-14 00:21:40 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027795 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.027795 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031650 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.031650 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15977.931006 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15977.931006 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29884.967427 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29884.967427 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17921.898278 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17921.898278 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19360.760985 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19360.760985 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13781.803901 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13781.803901 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.942083 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.942083 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.496040 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.496040 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.352816 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.352816 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.690519 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.690519 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 13489644 # number of replacements
system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 846636464 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 13490156 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 62.759576 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 32464202500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.cpu.icache.tags.tag_accesses 873616786 # Number of tag accesses
system.cpu.icache.tags.data_accesses 873616786 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 846636464 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 846636464 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 846636464 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 846636464 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 846636464 # number of overall hits
system.cpu.icache.overall_hits::total 846636464 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 13490161 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 13490161 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 13490161 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 13490161 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 13490161 # number of overall misses
system.cpu.icache.overall_misses::total 13490161 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 183617881000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 183617881000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 183617881000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 183617881000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 183617881000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 183617881000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 860126625 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 860126625 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 860126625 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 860126625 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 860126625 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 860126625 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015684 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.015684 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.015684 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.015684 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.015684 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.015684 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13611.244595 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13611.244595 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13611.244595 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13611.244595 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13611.244595 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
system.cpu.icache.writebacks::writebacks 13489644 # number of writebacks
system.cpu.icache.writebacks::total 13489644 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13490161 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 13490161 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 13490161 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 13490161 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 13490161 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 13490161 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
2016-10-14 00:21:40 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170127720000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 170127720000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170127720000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 170127720000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170127720000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 170127720000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015684 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.015684 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015684 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.015684 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12611.244595 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12611.244595 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12611.244595 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12611.244595 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 1158676 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65394.159072 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 44435371 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1220446 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 36.409125 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 10890.998401 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 465.362855 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 539.855564 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6670.163394 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 46827.778856 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.166183 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007101 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008238 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101779 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.714535 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.997836 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61492 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5790 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54645 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938293 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 377782006 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 377782006 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307317 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 227975 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 535292 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 7498102 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 7498102 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 13488047 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 13488047 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 24835 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 24835 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1605264 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1605264 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13414164 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 13414164 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6210983 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6210983 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 729246 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 729246 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 307317 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 227975 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 13414164 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7816247 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 21765703 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 307317 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 227975 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 13414164 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7816247 # number of overall hits
system.cpu.l2cache.overall_hits::total 21765703 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3382 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3425 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 6807 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3962 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 3962 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 414863 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 414863 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75997 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 75997 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 256141 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 256141 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 496901 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 496901 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 3382 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3425 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 75997 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 671004 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 753808 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 3382 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3425 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 75997 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 671004 # number of overall misses
system.cpu.l2cache.overall_misses::total 753808 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 458444500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 422573500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 881018000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69853000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 69853000 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40877442000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 40877442000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8773195000 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.WritebackDirty_accesses::total 7498102 # number of WritebackDirty accesses(hits+misses)
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2014-10-30 05:50:15 +01:00
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2016-10-14 00:21:40 +02:00
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2014-10-30 05:50:15 +01:00
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-10-14 00:21:40 +02:00
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2015-05-05 09:22:39 +02:00
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2016-08-12 15:12:59 +02:00
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2015-05-05 09:22:39 +02:00
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2016-08-12 15:12:59 +02:00
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2016-10-14 00:21:40 +02:00
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010885 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012557 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.137584 # mshr miss rate for UpgradeReq accesses
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2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
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2016-10-14 00:21:40 +02:00
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system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.405254 # mshr miss rate for InvalidateReq accesses
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19040.005048 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 105441.333211 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.380822 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.687184 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.076065 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.215576 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 46934872 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 23731321 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_filter.tot_snoops 1965 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1965 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 1010835 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 20969000 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 8483175 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 13489644 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2388366 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 28800 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 28802 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2020127 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2020127 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 13490161 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6470086 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1256693 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1226147 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40556216 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332974 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592159 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 883944 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 71365293 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726880020 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023309382 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1851200 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2485592 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2754526194 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1584975 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 66236232 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 25469090 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.019778 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.139236 # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::0 24965367 98.02% 98.02% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 503723 1.98% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoop_fanout::total 25469090 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 44744307000 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1625890 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 20278366500 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 13408934951 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 360759000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 573245000 # Layer occupancy (ticks)
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231050 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231050 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334632 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334632 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.iobus.pkt_size::total 7492552 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer23.occupancy 25714500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.reqLayer25.occupancy 569287162 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iobus.respLayer3.occupancy 147810000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115506 # number of replacements
system.iocache.tags.tagsinuse 10.457104 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-10-14 00:21:40 +02:00
system.iocache.tags.warmup_cycle 13154766855000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.510739 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.946366 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.434148 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-10-14 00:21:40 +02:00
system.iocache.tags.tag_accesses 1040082 # Number of tag accesses
system.iocache.tags.data_accesses 1040082 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_misses::realview.ide 8861 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8898 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-10-14 00:21:40 +02:00
system.iocache.demand_misses::realview.ide 115525 # number of demand (read+write) misses
system.iocache.demand_misses::total 115565 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-10-14 00:21:40 +02:00
system.iocache.overall_misses::realview.ide 115525 # number of overall misses
system.iocache.overall_misses::total 115565 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 2019214145 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 2024300645 # number of ReadReq miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
2016-10-14 00:21:40 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13409527517 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13409527517 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 15428741662 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 15434179162 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 15428741662 # number of overall miss cycles
system.iocache.overall_miss_latency::total 15434179162 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_accesses::realview.ide 8861 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8898 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-10-14 00:21:40 +02:00
system.iocache.demand_accesses::realview.ide 115525 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115565 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-10-14 00:21:40 +02:00
system.iocache.overall_accesses::realview.ide 115525 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115565 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 227876.554001 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 227500.634412 # average ReadReq miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
2016-10-14 00:21:40 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.463408 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125717.463408 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 133554.096500 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 133553.271257 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 133554.096500 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 51750 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.iocache.blocked::no_mshrs 3356 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-10-14 00:21:40 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 15.420143 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8861 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8898 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-10-14 00:21:40 +02:00
system.iocache.demand_mshr_misses::realview.ide 115525 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115565 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-10-14 00:21:40 +02:00
system.iocache.overall_mshr_misses::realview.ide 115525 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115565 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1576164145 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1579400645 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2016-10-14 00:21:40 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8069228353 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8069228353 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 9645392498 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9648829998 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 9645392498 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9648829998 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-10-14 00:21:40 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177876.554001 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 177500.634412 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2016-10-14 00:21:40 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75650.907082 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75650.907082 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 83491.819935 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 83492.666447 # average overall mshr miss latency
system.membus.snoop_filter.tot_requests 2643885 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 1308749 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3600 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-10-14 00:21:40 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadReq 76831 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadResp 424674 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::WriteReq 33710 # Transaction distribution
system.membus.trans_dist::WriteResp 33710 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::WritebackDirty 1091703 # Transaction distribution
system.membus.trans_dist::CleanEvict 181416 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
2016-10-14 00:21:40 +02:00
system.membus.trans_dist::ReadExReq 414305 # Transaction distribution
system.membus.trans_dist::ReadExResp 414305 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 347843 # Transaction distribution
system.membus.trans_dist::InvalidateReq 603558 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256260 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385964 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237234 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237234 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 3623198 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
2016-10-14 00:21:40 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111403936 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111573786 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 118792538 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3397 # Total snoops (count)
system.membus.snoopTraffic 216896 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1480779 # Request fanout histogram
system.membus.snoop_fanout::mean 0.023089 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.150185 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::0 1446590 97.69% 97.69% # Request fanout histogram
system.membus.snoop_fanout::1 34189 2.31% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-10-14 00:21:40 +02:00
system.membus.snoop_fanout::total 1480779 # Request fanout histogram
system.membus.reqLayer0.occupancy 106893000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.reqLayer2.occupancy 5820500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.reqLayer5.occupancy 7180364209 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.respLayer2.occupancy 4203282304 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.respLayer3.occupancy 44877398 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-10-14 00:21:40 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-10-14 00:21:40 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-10-14 00:21:40 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821888787500 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
