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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
sim_seconds 51.821204 # Number of seconds simulated
sim_ticks 51821203872000 # Number of ticks simulated
final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
host_inst_rate 797175 # Simulator instruction rate (inst/s)
host_op_rate 936716 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 46008450754 # Simulator tick rate (ticks/s)
host_mem_usage 656028 # Number of bytes of host memory used
host_seconds 1126.34 # Real time elapsed on the host
sim_insts 897890420 # Number of instructions simulated
sim_ops 1055061464 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory
system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory
system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 959683 # Number of read requests accepted
system.physmem.writeReqs 1860672 # Number of write requests accepted
system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue
system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 56975 # Per bank write bursts
system.physmem.perBankRdBursts::1 58359 # Per bank write bursts
system.physmem.perBankRdBursts::2 58716 # Per bank write bursts
system.physmem.perBankRdBursts::3 57264 # Per bank write bursts
system.physmem.perBankRdBursts::4 61545 # Per bank write bursts
system.physmem.perBankRdBursts::5 66145 # Per bank write bursts
system.physmem.perBankRdBursts::6 57228 # Per bank write bursts
system.physmem.perBankRdBursts::7 52937 # Per bank write bursts
system.physmem.perBankRdBursts::8 52189 # Per bank write bursts
system.physmem.perBankRdBursts::9 99547 # Per bank write bursts
system.physmem.perBankRdBursts::10 57680 # Per bank write bursts
system.physmem.perBankRdBursts::11 61393 # Per bank write bursts
system.physmem.perBankRdBursts::12 54506 # Per bank write bursts
system.physmem.perBankRdBursts::13 60286 # Per bank write bursts
system.physmem.perBankRdBursts::14 51564 # Per bank write bursts
system.physmem.perBankRdBursts::15 52667 # Per bank write bursts
system.physmem.perBankWrBursts::0 114739 # Per bank write bursts
system.physmem.perBankWrBursts::1 115397 # Per bank write bursts
system.physmem.perBankWrBursts::2 117633 # Per bank write bursts
system.physmem.perBankWrBursts::3 119136 # Per bank write bursts
system.physmem.perBankWrBursts::4 120318 # Per bank write bursts
system.physmem.perBankWrBursts::5 121968 # Per bank write bursts
system.physmem.perBankWrBursts::6 116613 # Per bank write bursts
system.physmem.perBankWrBursts::7 113695 # Per bank write bursts
system.physmem.perBankWrBursts::8 109286 # Per bank write bursts
system.physmem.perBankWrBursts::9 116370 # Per bank write bursts
system.physmem.perBankWrBursts::10 115629 # Per bank write bursts
system.physmem.perBankWrBursts::11 118249 # Per bank write bursts
system.physmem.perBankWrBursts::12 111968 # Per bank write bursts
system.physmem.perBankWrBursts::13 117797 # Per bank write bursts
system.physmem.perBankWrBursts::14 110347 # Per bank write bursts
system.physmem.perBankWrBursts::15 113912 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
system.physmem.totGap 51821201316000 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.readPktSize::6 916567 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.writePktSize::6 1858099 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 925038 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 28111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 593 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 706 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 405 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 375 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 306 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 221 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 147 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 137 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 124 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::15 58079 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 70983 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 101652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 104342 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 108305 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 122410 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 126456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 111805 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 113098 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 110863 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 108761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 105735 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 102887 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 101533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 96838 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 95973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 95806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 94380 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3424 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 2906 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1880 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1660 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1358 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1022 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 916 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 412 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 308 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 295 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 181 # What write queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::54 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 617611 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 291.399266 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 166.446996 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads
system.physmem.totQLat 12714966775 # Total ticks spent queuing
system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing
system.physmem.readRowHits 722338 # Number of row buffer hits during reads
system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes
system.physmem.avgGap 18373999.48 # Average gap between requests
system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states
system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ)
system.physmem.averagePower::0 668.686370 # Core power per rank (mW)
system.physmem.averagePower::1 668.663363 # Core power per rank (mW)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.read_hits 168646043 # DTB read hits
system.cpu.dtb.read_misses 158497 # DTB read misses
system.cpu.dtb.write_hits 153371607 # DTB write hits
system.cpu.dtb.write_misses 56347 # DTB write misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 168804540 # DTB read accesses
system.cpu.dtb.write_accesses 153427954 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dtb.hits 322017650 # DTB hits
system.cpu.dtb.misses 214844 # DTB misses
system.cpu.dtb.accesses 322232494 # DTB accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.inst_hits 898442559 # ITB inst hits
system.cpu.itb.inst_misses 123457 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.itb.inst_accesses 898566016 # ITB inst accesses
system.cpu.itb.hits 898442559 # DTB hits
system.cpu.itb.misses 123457 # DTB misses
system.cpu.itb.accesses 898566016 # DTB accesses
system.cpu.numCycles 103642407744 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.committedInsts 897890420 # Number of instructions committed
system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses
system.cpu.num_func_calls 53165114 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls
system.cpu.num_int_insts 968615704 # number of integer instructions
system.cpu.num_fp_insts 900077 # number of float instructions
system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read
system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written
system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read
system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written
system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read
system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written
system.cpu.num_mem_refs 322001322 # number of memory refs
system.cpu.num_load_insts 168639088 # Number of load instructions
system.cpu.num_store_insts 153362234 # Number of store instructions
system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles
system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles
system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.969412 # Percentage of idle cycles
system.cpu.Branches 200577010 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction
system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction
system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction
system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.op_class::total 1055656727 # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed
system.cpu.dcache.tags.replacements 10282368 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits
system.cpu.dcache.overall_hits::total 303464910 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses
system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses
system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 7580753 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7580753 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 8890915 # number of overall misses
system.cpu.dcache.overall_misses::total 8890915 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 83712196260 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 83712196260 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 64378240535 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 64378240535 # number of WriteReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27514486506 # number of WriteInvalidateReq miss cycles
system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27514486506 # number of WriteInvalidateReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4474608500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 4474608500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251501 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 251501 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 148090436795 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 148090436795 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 148090436795 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 148090436795 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 162900280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 162900280 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 147748389 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 147748389 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707156 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1707156 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568634 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total 1568634 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004840 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 4004840 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4003153 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 4003153 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 310648669 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 310648669 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 312355825 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 312355825 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032806 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032806 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015138 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015138 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767453 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.767453 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.785363 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.785363 # miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076531 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076531 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.024403 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.024403 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.028464 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.028464 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15664.452368 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15664.452368 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28783.126553 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28783.126553 # average WriteReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22334.147902 # average WriteInvalidateReq miss latency
system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902 # average WriteInvalidateReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14599.287101 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 62875.250000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 62875.250000 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19535.056319 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 19535.056319 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16656.377526 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16656.377526 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 7918344 # number of writebacks
system.cpu.dcache.writebacks::total 7918344 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7198 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 7198 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21104 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 21104 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70788 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 70788 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 28302 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 28302 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 28302 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 28302 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5336889 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5336889 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2215562 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2215562 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1308413 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1308413 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1231947 # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1231947 # number of WriteInvalidateReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 235707 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 235707 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 7552451 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 7552451 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8860864 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8860864 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72465482990 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 72465482990 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59129774715 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 59129774715 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19473134500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19473134500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25050592494 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25050592494 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2902318500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2902318500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 243499 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 243499 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131595257705 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 131595257705 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151068392205 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 151068392205 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727938750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727938750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573388000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573388000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301326750 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301326750 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032762 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032762 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014996 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014996 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766428 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766428 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.785363 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.785363 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058856 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058856 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.024312 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028368 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.028368 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13578.225627 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13578.225627 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26688.386385 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26688.386385 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14883.018206 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14883.018206 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20334.147893 # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20334.147893 # average WriteInvalidateReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12313.246955 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12313.246955 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 60874.750000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 60874.750000 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17424.178946 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17424.178946 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17048.946040 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17048.946040 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13856298 # number of replacements
system.cpu.icache.tags.tagsinuse 511.892935 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 884585744 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 13856810 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 63.837618 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 31832974250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.892935 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999791 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999791 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.tag_accesses 912299374 # Number of tag accesses
system.cpu.icache.tags.data_accesses 912299374 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 884585744 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 884585744 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 884585744 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 884585744 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 884585744 # number of overall hits
system.cpu.icache.overall_hits::total 884585744 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 13856815 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 13856815 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 13856815 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 13856815 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 13856815 # number of overall misses
system.cpu.icache.overall_misses::total 13856815 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 185267091485 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 185267091485 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 185267091485 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 185267091485 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 185267091485 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 185267091485 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 898442559 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 898442559 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 898442559 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 898442559 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 898442559 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 898442559 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015423 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.015423 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.015423 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.015423 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.015423 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.015423 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13370.106441 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13370.106441 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13370.106441 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13370.106441 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13370.106441 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13856815 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 13856815 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 13856815 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 13856815 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 13856815 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 13856815 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 157525292015 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 157525292015 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 157525292015 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 157525292015 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 157525292015 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 157525292015 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2831639000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2831639000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2831639000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 2831639000 # number of overall MSHR uncacheable cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015423 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.015423 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015423 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.015423 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11368.073545 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11368.073545 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11368.073545 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11368.073545 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.replacements 1326931 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65218.833700 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 27835482 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1389841 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 20.027818 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 6373825000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 38602.265871 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 305.289253 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 445.157205 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6377.971996 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19488.149376 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.589024 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004658 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006793 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.097320 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.297366 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.995160 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62664 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2454 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5481 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54290 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956177 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 266276553 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 266276553 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 378716 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250963 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 13777936 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6592157 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 20999772 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 7918344 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 7918344 # number of Writeback hits
system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 722474 # number of WriteInvalidateReq hits
system.cpu.l2cache.WriteInvalidateReq_hits::total 722474 # number of WriteInvalidateReq hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9882 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 9882 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1634882 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1634882 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 378716 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 250963 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 13777936 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 8227039 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 22634654 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 378716 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 250963 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 13777936 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 8227039 # number of overall hits
system.cpu.l2cache.overall_hits::total 22634654 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4296 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4389 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 78879 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 288852 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 376416 # number of ReadReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509473 # number of WriteInvalidateReq misses
system.cpu.l2cache.WriteInvalidateReq_misses::total 509473 # number of WriteInvalidateReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 35727 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 35727 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 535071 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 535071 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 4296 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 4389 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 78879 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 823923 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 911487 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 4296 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 4389 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 78879 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 823923 # number of overall misses
system.cpu.l2cache.overall_misses::total 911487 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 336423500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345754750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5888588734 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22037305240 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 28608072224 # number of ReadReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 117495 # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 117495 # number of WriteInvalidateReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 416260719 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 416260719 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 239499 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 239499 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 39649987439 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 39649987439 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 336423500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345754750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 5888588734 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 61687292679 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 68258059663 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 336423500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345754750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 5888588734 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 61687292679 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 68258059663 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 383012 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 255352 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 13856815 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 6881009 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 21376188 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 7918344 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 7918344 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1231947 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.WriteInvalidateReq_accesses::total 1231947 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45609 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 45609 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2169953 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2169953 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 383012 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 255352 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 13856815 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9050962 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 23546141 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 383012 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 255352 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 13856815 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9050962 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 23546141 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011216 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017188 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005692 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.041978 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.017609 # miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413551 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413551 # miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783332 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783332 # miss rate for UpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.246582 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.246582 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011216 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017188 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005692 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.091032 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.038711 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011216 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017188 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005692 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.091032 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.038711 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78310.870577 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78777.568922 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74653.440510 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76292.721671 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76001.212021 # average ReadReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.230621 # average WriteInvalidateReq miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.230621 # average WriteInvalidateReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11651.152322 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11651.152322 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 59874.750000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 59874.750000 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74102.291918 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74102.291918 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78310.870577 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78777.568922 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74653.440510 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74870.215638 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74886.487315 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78310.870577 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78777.568922 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74653.440510 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74870.215638 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74886.487315 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.writebacks::writebacks 1135338 # number of writebacks
system.cpu.l2cache.writebacks::total 1135338 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4296 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4389 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 78879 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 288852 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 376416 # number of ReadReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509473 # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 509473 # number of WriteInvalidateReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35727 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 35727 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 535071 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 535071 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4296 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4389 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 78879 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 823923 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 911487 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4296 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4389 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 78879 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 823923 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 911487 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 282739500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 290818750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 4901275766 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18418526760 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23893360776 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 10988649006 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 10988649006 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 357469724 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 357469724 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 190001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 190001 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32969610561 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32969610561 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 282739500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 290818750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 4901275766 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51388137321 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 56862971337 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 282739500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 290818750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 4901275766 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51388137321 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 56862971337 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2248902500 # number of ReadReq MSHR uncacheable cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5287986500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7536889000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5166017500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5166017500 # number of WriteReq MSHR uncacheable cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2248902500 # number of overall MSHR uncacheable cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454004000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12702906500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.041978 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017609 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413551 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413551 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783332 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783332 # mshr miss rate for UpgradeReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246582 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246582 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.038711 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.038711 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62136.636697 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63764.581031 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63475.943573 # average ReadReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21568.658213 # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21568.658213 # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.590282 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.590282 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 474114 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.trans_dist::ReadReq 40402 # Transaction distribution
system.iobus.trans_dist::ReadResp 40402 # Transaction distribution
system.iobus.trans_dist::WriteReq 136733 # Transaction distribution
system.iobus.trans_dist::WriteResp 30069 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115480 # number of replacements
system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.tag_accesses 1039857 # Number of tag accesses
system.iocache.tags.data_accesses 1039857 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses
system.iocache.demand_misses::total 8876 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_misses::realview.ide 8836 # number of overall misses
system.iocache.overall_misses::total 8876 # number of overall misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.writebacks::writebacks 106629 # number of writebacks
system.iocache.writebacks::total 106629 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.trans_dist::ReadReq 462201 # Transaction distribution
system.membus.trans_dist::ReadResp 462201 # Transaction distribution
system.membus.trans_dist::WriteReq 33872 # Transaction distribution
system.membus.trans_dist::WriteResp 33872 # Transaction distribution
system.membus.trans_dist::Writeback 1241967 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution
system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution
system.membus.trans_dist::ReadExReq 534513 # Transaction distribution
system.membus.trans_dist::ReadExResp 534513 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3244 # Total snoops (count)
system.membus.snoop_fanout::samples 2814199 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2814199 # Request fanout histogram
system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink