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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
sim_seconds 51.278323 # Number of seconds simulated
sim_ticks 51278322908000 # Number of ticks simulated
final_tick 51278322908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
host_inst_rate 391318 # Simulator instruction rate (inst/s)
host_op_rate 459835 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 23610419083 # Simulator tick rate (ticks/s)
host_mem_usage 689044 # Number of bytes of host memory used
host_seconds 2171.85 # Real time elapsed on the host
sim_insts 849885052 # Number of instructions simulated
sim_ops 998692344 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.bytes_read::cpu0.dtb.walker 79744 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 81088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2584308 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 18551240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 21056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 18624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 450240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4979392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 31808 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 29568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 1509568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 6342336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 66432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker 61184 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 1749760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 11675328 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 416192 # Number of bytes read from this memory
system.physmem.bytes_read::total 48647868 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2584308 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 450240 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 1509568 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 1749760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6293876 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 68210816 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.bytes_written::total 68231396 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1246 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1267 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 80787 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 289876 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 329 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 291 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 7035 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 77803 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 462 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 23587 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 99099 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 1038 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker 956 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 27340 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 182427 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6503 # Number of read requests responded to by this memory
system.physmem.num_reads::total 800543 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1065794 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.num_writes::total 1068367 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1555 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1581 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 50398 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 361775 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 411 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 363 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 8780 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 97105 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 620 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 577 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 29439 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 123685 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1296 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker 1193 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 34123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 227685 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8116 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 948702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 50398 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 8780 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 29439 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 34123 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 122740 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1330208 # Write bandwidth from this memory (bytes/s)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.bw_write::total 1330609 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1330208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1555 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1581 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 50398 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 362177 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 363 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 8780 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 97105 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 620 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 577 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 29439 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 123685 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker 1193 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 34123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 227685 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8116 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2279311 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 425112 # Number of read requests accepted
system.physmem.writeReqs 454625 # Number of write requests accepted
system.physmem.readBursts 425112 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 454625 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 27178752 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 28416 # Total number of bytes read from write queue
system.physmem.bytesWritten 29094208 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 27207168 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 29096000 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 444 # Number of DRAM read bursts serviced by the write queue
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.perBankRdBursts::0 27658 # Per bank write bursts
system.physmem.perBankRdBursts::1 29828 # Per bank write bursts
system.physmem.perBankRdBursts::2 28706 # Per bank write bursts
system.physmem.perBankRdBursts::3 26688 # Per bank write bursts
system.physmem.perBankRdBursts::4 26134 # Per bank write bursts
system.physmem.perBankRdBursts::5 30288 # Per bank write bursts
system.physmem.perBankRdBursts::6 24980 # Per bank write bursts
system.physmem.perBankRdBursts::7 26114 # Per bank write bursts
system.physmem.perBankRdBursts::8 23639 # Per bank write bursts
system.physmem.perBankRdBursts::9 28679 # Per bank write bursts
system.physmem.perBankRdBursts::10 26865 # Per bank write bursts
system.physmem.perBankRdBursts::11 27723 # Per bank write bursts
system.physmem.perBankRdBursts::12 26411 # Per bank write bursts
system.physmem.perBankRdBursts::13 25648 # Per bank write bursts
system.physmem.perBankRdBursts::14 22535 # Per bank write bursts
system.physmem.perBankRdBursts::15 22772 # Per bank write bursts
system.physmem.perBankWrBursts::0 28961 # Per bank write bursts
system.physmem.perBankWrBursts::1 29340 # Per bank write bursts
system.physmem.perBankWrBursts::2 30073 # Per bank write bursts
system.physmem.perBankWrBursts::3 30333 # Per bank write bursts
system.physmem.perBankWrBursts::4 28091 # Per bank write bursts
system.physmem.perBankWrBursts::5 30746 # Per bank write bursts
system.physmem.perBankWrBursts::6 26981 # Per bank write bursts
system.physmem.perBankWrBursts::7 28675 # Per bank write bursts
system.physmem.perBankWrBursts::8 26142 # Per bank write bursts
system.physmem.perBankWrBursts::9 29950 # Per bank write bursts
system.physmem.perBankWrBursts::10 27880 # Per bank write bursts
system.physmem.perBankWrBursts::11 29356 # Per bank write bursts
system.physmem.perBankWrBursts::12 28075 # Per bank write bursts
system.physmem.perBankWrBursts::13 28226 # Per bank write bursts
system.physmem.perBankWrBursts::14 25398 # Per bank write bursts
system.physmem.perBankWrBursts::15 26370 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.numWrRetry 27 # Number of times write queue was full causing retry
system.physmem.totGap 51277322578500 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.readPktSize::6 425112 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.writePktSize::6 454625 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 320658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 71523 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 20097 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8919 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 382 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 348 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 332 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 736 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 254 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 253 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 107 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 78 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 75 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 65 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 53 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.wrQLenPdf::0 596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 571 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 571 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 572 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 567 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 565 # What write queue length does an incoming req see
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.physmem.wrQLenPdf::9 564 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 559 # What write queue length does an incoming req see
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.wrQLenPdf::11 560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 561 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 556 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 555 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 10142 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 11914 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 20808 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 22265 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 25126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 25463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 25664 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 25947 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 26600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 26580 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 27124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 28654 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 27815 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 28161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 29398 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 26416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 26013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 25235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 442 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 264549 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 212.710628 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 133.311116 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 253.186946 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 128347 48.52% 48.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 68595 25.93% 74.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 23489 8.88% 83.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 11716 4.43% 87.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 8015 3.03% 90.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 4779 1.81% 92.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 3761 1.42% 94.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2799 1.06% 95.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 13048 4.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 264549 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 24602 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 17.259532 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 12.570080 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-31 22973 93.38% 93.38% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-63 1501 6.10% 99.48% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-95 103 0.42% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-127 9 0.04% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-159 2 0.01% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-191 2 0.01% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::192-223 4 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::224-255 3 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-287 1 0.00% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::352-383 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::416-447 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::480-511 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::608-639 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 24602 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 24602 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.478051 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.651979 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 9.004636 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 26 0.11% 0.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 15 0.06% 0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 5 0.02% 0.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 55 0.22% 0.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 22328 90.76% 91.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 965 3.92% 95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 224 0.91% 96.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 206 0.84% 96.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 77 0.31% 97.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 56 0.23% 97.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 71 0.29% 97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 24 0.10% 97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 154 0.63% 98.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 44 0.18% 98.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 15 0.06% 98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 22 0.09% 98.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 116 0.47% 99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 24 0.10% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 8 0.03% 99.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 50 0.20% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 75 0.30% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.01% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.01% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.01% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 7 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 11 0.04% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 3 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-235 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 24602 # Writes before turning the bus around for reads
system.physmem.totQLat 8333966979 # Total ticks spent queuing
system.physmem.totMemAccLat 16296491979 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2123340000 # Total ticks spent in databus transfers
system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.53 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.57 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.busUtil 0.01 # Data bus utilization in percentage
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.avgWrQLen 6.41 # Average write queue length when enqueuing
system.physmem.readRowHits 310449 # Number of row buffer hits during reads
system.physmem.writeRowHits 304265 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.10 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.93 # Row buffer hit rate for writes
system.physmem.avgGap 58287104.64 # Average gap between requests
system.physmem.pageHitRate 69.91 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1040339160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 565834500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1719073200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1511136000 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3310423515360 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1181162631510 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 30835777461750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 35332199991480 # Total energy per rank (pJ)
system.physmem_0.averagePower 665.141706 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 48866215203670 # Time in different power states
system.physmem_0.memoryStateTime::REF 1692445560000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem_0.memoryStateTime::ACT 125694518580 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem_1.actEnergy 959651280 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 522080625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1593267000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1434652560 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3310423515360 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1174137422265 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29654012520750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34143083109840 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.640404 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 48876586216946 # Time in different power states
system.physmem_1.memoryStateTime::REF 1692445560000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem_1.memoryStateTime::ACT 115306042554 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walks 90589 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 90589 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 90589 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 90589 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 90589 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 384648913196 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.541506 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -208289583554 -54.15% -54.15% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 592938496750 154.15% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 384648913196 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 66121 84.68% 84.68% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 11962 15.32% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 78083 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90589 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90589 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78083 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78083 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 168672 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.read_hits 64905943 # DTB read hits
system.cpu0.dtb.read_misses 68632 # DTB read misses
system.cpu0.dtb.write_hits 59387283 # DTB write hits
system.cpu0.dtb.write_misses 21957 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.dtb.flush_tlb 1195 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 16181 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 404 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 41245 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.prefetch_faults 2795 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.perms_faults 7554 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 64974575 # DTB read accesses
system.cpu0.dtb.write_accesses 59409240 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dtb.hits 124293226 # DTB hits
system.cpu0.dtb.misses 90589 # DTB misses
system.cpu0.dtb.accesses 124383815 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walks 53629 # Table walker walks requested
system.cpu0.itb.walker.walksLong 53629 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 53629 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 53629 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 53629 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 384648913196 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.541605 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -208327943554 -54.16% -54.16% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 592976856750 154.16% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 384648913196 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 46675 94.93% 94.93% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2493 5.07% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 49168 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53629 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53629 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49168 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49168 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 102797 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 346758065 # ITB inst hits
system.cpu0.itb.inst_misses 53629 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.itb.flush_tlb 1195 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.flush_tlb_mva_asid 16181 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 404 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 28950 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.itb.inst_accesses 346811694 # ITB inst accesses
system.cpu0.itb.hits 346758065 # DTB hits
system.cpu0.itb.misses 53629 # DTB misses
system.cpu0.itb.accesses 346811694 # DTB accesses
system.cpu0.numCycles 418356627 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.kern.inst.quiesce 16523 # number of quiesce instructions executed
system.cpu0.committedInsts 346615446 # Number of instructions committed
system.cpu0.committedOps 407794224 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 374692963 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 359996 # Number of float alu accesses
system.cpu0.num_func_calls 21015198 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 52493274 # number of instructions that are conditional controls
system.cpu0.num_int_insts 374692963 # number of integer instructions
system.cpu0.num_fp_insts 359996 # number of float instructions
system.cpu0.num_int_register_reads 546961774 # number of times the integer registers were read
system.cpu0.num_int_register_writes 297330498 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 576159 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 315016 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 89964300 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 89735253 # number of times the CC registers were written
system.cpu0.num_mem_refs 124366560 # number of memory refs
system.cpu0.num_load_insts 64963335 # Number of load instructions
system.cpu0.num_store_insts 59403225 # Number of store instructions
system.cpu0.num_idle_cycles 408478241.491071 # Number of idle cycles
system.cpu0.num_busy_cycles 9878385.508929 # Number of busy cycles
system.cpu0.not_idle_fraction 0.023612 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.976388 # Percentage of idle cycles
system.cpu0.Branches 77357953 # Number of branches fetched
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.op_class::IntAlu 282690768 69.28% 69.28% # Class of executed instruction
system.cpu0.op_class::IntMult 882754 0.22% 69.50% # Class of executed instruction
system.cpu0.op_class::IntDiv 40502 0.01% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 48552 0.01% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
system.cpu0.op_class::MemRead 64963335 15.92% 85.44% # Class of executed instruction
system.cpu0.op_class::MemWrite 59403225 14.56% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.op_class::total 408029136 # Class of executed instruction
system.cpu0.dcache.tags.replacements 9683863 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999715 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 293338565 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 9684375 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 30.289881 # Average number of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.042783 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.501939 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.121621 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 4.333371 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968834 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.012699 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010003 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.008464 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.tags.tag_accesses 1243130988 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1243130988 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 60751672 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 18984916 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 26046764 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 45054878 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 150838230 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56188931 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 17455574 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 23041710 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 37927921 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 134614136 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 159339 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 46933 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 75224 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113852 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 395348 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 127860 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 45150 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data 58313 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97655 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 328978 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1451290 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 446318 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 563586 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 939310 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3400504 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1544040 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 483834 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 609806 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1079891 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3717571 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 116940603 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 36440490 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 49088474 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 82982799 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 285452366 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 117099942 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 36487423 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 49163698 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 83096651 # number of overall hits
system.cpu0.dcache.overall_hits::total 285847714 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2030815 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 644672 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 1011990 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 3458249 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7145726 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 845412 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 260042 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 597066 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 3459376 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5161896 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 464867 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 155176 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 204272 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 351146 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1175461 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 679112 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 108775 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data 155074 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data 283537 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1226498 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 93472 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37729 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 46508 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 179586 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 357295 # number of LoadLockedReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2876227 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 904714 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1609056 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 6917625 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 12307622 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3341094 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1059890 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1813328 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 7268771 # number of overall misses
system.cpu0.dcache.overall_misses::total 13483083 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 10698804500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 17340107500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 59913845000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 87952757000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9909194500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 21738446500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 123192835885 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 154840476885 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2652200500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 3869251000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 7740685005 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 14262136505 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 537037000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 691796000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2392369500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3621202500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 96000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 96000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 20607999000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 39078554000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 183106680885 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 242793233885 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 20607999000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 39078554000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 183106680885 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 242793233885 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 62782487 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 19629588 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 27058754 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 48513127 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 157983956 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 57034343 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 17715616 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 23638776 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 41387297 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 139776032 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 624206 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 202109 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 279496 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 464998 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1570809 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 806972 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 153925 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 213387 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 381192 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1555476 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1544762 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 484047 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 610094 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1118896 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3757799 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1544041 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 483834 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 609806 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1079893 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3717574 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 119816830 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 37345204 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 50697530 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 89900424 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 297759988 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 120441036 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 37547313 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 50977026 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 90365422 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 299330797 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032347 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032842 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.037400 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071285 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.045231 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014823 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014679 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025258 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.083585 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.036930 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.744733 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.767784 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.730858 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.755156 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748316 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.841556 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.706675 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.726727 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.743817 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788503 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060509 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077945 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.076231 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.160503 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095081 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000002 # miss rate for StoreCondReq accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024005 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024226 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.031738 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076948 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041334 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027740 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028228 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.035571 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.080438 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.045044 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16595.733179 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17134.662892 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17324.907778 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 12308.442417 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38106.130933 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36408.783116 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 35611.288245 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 29996.822269 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24382.445415 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 24950.997588 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 27300.440525 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 11628.340613 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14234.063983 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14874.774232 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13321.581304 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10135.049469 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 48000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 32000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22778.468113 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24286.633902 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 26469.587595 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19727.062944 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19443.526215 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21550.736546 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 25190.872141 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18007.249075 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 13349622 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 42813 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 888017 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 383 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.033070 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 111.783290 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.dcache.writebacks::writebacks 7515525 # number of writebacks
system.cpu0.dcache.writebacks::total 7515525 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3276 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 134843 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1916488 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 2054607 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4909 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 264522 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2873336 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3142767 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 30 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2182 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 2212 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8103 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10295 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 111171 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 129569 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 8185 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 399365 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 4789824 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 5197374 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 8185 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 399365 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 4789824 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 5197374 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 641396 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 877147 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1541761 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3060304 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 255133 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 332544 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 586040 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1173717 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 154795 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 201619 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 344076 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 700490 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 108775 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 155044 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 281355 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 545174 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29626 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 36213 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 68415 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 134254 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 896529 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 1209691 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 2127801 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4234021 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1051324 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 1411310 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 2471877 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4934511 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6822 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6471 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6195 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19488 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 6365 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5967 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 5946 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18278 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 13187 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12438 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 12141 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 37766 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9839335500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13798480000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26372542500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50010358000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9439452500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 11608777000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 22371985686 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 43420215186 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3097810500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 4113843000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6612019000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13823672500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2543425500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 3712452000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 7304828505 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 13560706005 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 387292500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 482037500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 972190500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1841520500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 94000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 94000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19278788000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25407257000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 48744528186 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 93430573186 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22376598500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 29521100000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 55356547186 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 107254245686 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1337930000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1252976500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1175066000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3765972500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1285279500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1186994000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1151196455 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3623469955 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2623209500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2439970500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2326262455 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7389442455 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032675 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.032416 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031780 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019371 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014402 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014068 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014160 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008397 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765899 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.721366 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.739952 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.445942 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.706675 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.726586 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.738093 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.350487 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061205 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.059356 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.061145 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035727 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024007 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023861 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023668 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.014220 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028000 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027685 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027354 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.016485 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15340.500253 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15731.091824 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17105.467384 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16341.630766 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36998.163703 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34908.995501 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 38174.844185 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36993.768673 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20012.342130 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20404.044262 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19216.739906 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19734.289569 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23382.445415 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 23944.506076 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 25963.030709 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 24874.087915 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13072.723284 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13311.172783 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14210.195133 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13716.690006 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 47000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 47000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21503.808577 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21003.096659 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22908.405526 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22066.629614 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21284.207818 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20917.516350 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22394.539528 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21735.536852 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196119.906186 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 193629.500850 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189679.741727 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193245.715312 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201929.222310 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 198926.428691 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 193608.552809 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 198242.146570 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 198923.902328 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 196170.646406 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 191603.859237 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 195663.889610 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.replacements 15734993 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.971408 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 559674194 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 15735505 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.567603 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 11770190500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 476.852160 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.999201 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 23.919768 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 6.200279 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.931352 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.009764 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.046718 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.012110 # Average percentage of cache occupancy
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.tags.tag_accesses 591503704 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 591503704 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 341216233 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 106915953 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 63798123 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 47743885 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 559674194 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 341216233 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 106915953 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 63798123 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 47743885 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 559674194 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 341216233 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 106915953 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 63798123 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 47743885 # number of overall hits
system.cpu0.icache.overall_hits::total 559674194 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5591000 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1659602 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 3868569 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 4974758 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 16093929 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5591000 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1659602 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 3868569 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 4974758 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 16093929 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5591000 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1659602 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 3868569 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 4974758 # number of overall misses
system.cpu0.icache.overall_misses::total 16093929 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22460583500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 53232501500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 67243887803 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 142936972803 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 22460583500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 53232501500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 67243887803 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 142936972803 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 22460583500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 53232501500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 67243887803 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 142936972803 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 346807233 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 108575555 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 67666692 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 52718643 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 575768123 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 346807233 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 108575555 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 67666692 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 52718643 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 575768123 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 346807233 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 108575555 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 67666692 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 52718643 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 575768123 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016121 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015285 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057171 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.094364 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.027952 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016121 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015285 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057171 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.094364 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.027952 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016121 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015285 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057171 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.094364 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.027952 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13533.716819 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13760.256441 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13517.016869 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8881.421858 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13533.716819 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13760.256441 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13517.016869 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8881.421858 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13533.716819 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13760.256441 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13517.016869 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8881.421858 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 61843 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.blocked::no_mshrs 3753 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.478284 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu0.icache.writebacks::writebacks 15734993 # number of writebacks
system.cpu0.icache.writebacks::total 15734993 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 358348 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 358348 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 358348 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 358348 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 358348 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 358348 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1659602 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3868569 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4616410 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 10144581 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 1659602 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 3868569 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 4616410 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 10144581 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 1659602 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 3868569 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 4616410 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 10144581 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 20800981500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 49363932500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 59359822840 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 129524736840 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 20800981500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 49363932500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 59359822840 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 129524736840 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 20800981500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 49363932500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 59359822840 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 129524736840 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015285 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.057171 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.087567 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017619 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015285 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.057171 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.087567 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017619 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015285 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.057171 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.087567 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017619 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12533.716819 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12760.256441 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12858.438232 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12767.874478 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12533.716819 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12760.256441 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12858.438232 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12767.874478 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12533.716819 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12760.256441 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12858.438232 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12767.874478 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walks 31825 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 31825 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4653 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23077 # Level at which table walker walks with long descriptors terminate
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walkWaitTime::samples 31819 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 1.099972 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 196.211646 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 31818 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 31819 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 27736 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24896.776752 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21479.770946 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15609.675218 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 27586 99.46% 99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.01% 99.47% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 129 0.47% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 11 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 27736 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 3125373784 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.674826 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.468440 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1016289500 32.52% 32.52% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 2109084284 67.48% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 3125373784 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 23077 83.22% 83.22% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 4653 16.78% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 27730 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31825 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31825 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27730 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27730 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 59555 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.read_hits 20322566 # DTB read hits
system.cpu1.dtb.read_misses 24426 # DTB read misses
system.cpu1.dtb.write_hits 18362474 # DTB write hits
system.cpu1.dtb.write_misses 7399 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu1.dtb.flush_tlb 1186 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 5702 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 134 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 18006 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.prefetch_faults 961 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.perms_faults 2721 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 20346992 # DTB read accesses
system.cpu1.dtb.write_accesses 18369873 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.dtb.hits 38685040 # DTB hits
system.cpu1.dtb.misses 31825 # DTB misses
system.cpu1.dtb.accesses 38716865 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walks 20346 # Table walker walks requested
system.cpu1.itb.walker.walksLong 20346 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 938 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17905 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 20346 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 20346 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 20346 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 18843 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28149.073927 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24906.041063 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 17543.804263 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 9517 50.51% 50.51% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 9170 48.67% 99.17% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 113 0.60% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 25 0.13% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 7 0.04% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 18843 # Table walker service (enqueue to completion) latency
stats: Update switcheroo reference stats The Minor draining fixes affect perturb the timing slightly since it affects how the simulator is drained. Update reference statistics to reflect this expected change.
2015-07-31 18:04:59 +02:00
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkPageSizes::4K 17905 95.02% 95.02% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 938 4.98% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 18843 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20346 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20346 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18843 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18843 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 39189 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 108575555 # ITB inst hits
system.cpu1.itb.inst_misses 20346 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu1.itb.flush_tlb 1186 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.flush_tlb_mva_asid 5702 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 134 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 13443 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.itb.inst_accesses 108595901 # ITB inst accesses
system.cpu1.itb.hits 108575555 # DTB hits
system.cpu1.itb.misses 20346 # DTB misses
system.cpu1.itb.accesses 108595901 # DTB accesses
system.cpu1.numCycles 1186099317 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update for UDelayEvent quiesce change
2015-10-10 23:45:41 +02:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.committedInsts 108493989 # Number of instructions committed
system.cpu1.committedOps 127332484 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 116990571 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 112697 # Number of float alu accesses
system.cpu1.num_func_calls 6392203 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 16488906 # number of instructions that are conditional controls
system.cpu1.num_int_insts 116990571 # number of integer instructions
system.cpu1.num_fp_insts 112697 # number of float instructions
system.cpu1.num_int_register_reads 169322857 # number of times the integer registers were read
system.cpu1.num_int_register_writes 92877962 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 186200 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 85320 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 28186380 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 28117162 # number of times the CC registers were written
system.cpu1.num_mem_refs 38682469 # number of memory refs
system.cpu1.num_load_insts 20321860 # Number of load instructions
system.cpu1.num_store_insts 18360609 # Number of store instructions
system.cpu1.num_idle_cycles 1161291203.919647 # Number of idle cycles
system.cpu1.num_busy_cycles 24808113.080353 # Number of busy cycles
system.cpu1.not_idle_fraction 0.020916 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.979084 # Percentage of idle cycles
system.cpu1.Branches 24140854 # Number of branches fetched
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.op_class::IntAlu 88426718 69.40% 69.40% # Class of executed instruction
system.cpu1.op_class::IntMult 282557 0.22% 69.62% # Class of executed instruction
system.cpu1.op_class::IntDiv 11066 0.01% 69.63% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.63% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 11198 0.01% 69.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.64% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.64% # Class of executed instruction
system.cpu1.op_class::MemRead 20321860 15.95% 85.59% # Class of executed instruction
system.cpu1.op_class::MemWrite 18360609 14.41% 100.00% # Class of executed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu1.op_class::total 127414050 # Class of executed instruction
system.cpu2.branchPred.lookups 39333191 # Number of BP lookups
system.cpu2.branchPred.condPredicted 27294641 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 2001884 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 28467796 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 20146403 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.branchPred.BTBHitPct 70.769100 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4823620 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 322221 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.walker.walks 93913 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 93913 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6917 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29157 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 93913 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 93913 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 93913 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 36074 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 25782.752121 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 22543.379913 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 16665.993144 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-65535 35851 99.38% 99.38% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-196607 193 0.54% 99.92% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-262143 7 0.02% 99.94% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-327679 7 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::393216-458751 12 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 36074 # Table walker service (enqueue to completion) latency
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.walker.walkPageSizes::4K 29157 80.83% 80.83% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M 6917 19.17% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 36074 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93913 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93913 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36074 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36074 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 129987 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.read_hits 28226009 # DTB read hits
system.cpu2.dtb.read_misses 78415 # DTB read misses
system.cpu2.dtb.write_hits 24563003 # DTB write hits
system.cpu2.dtb.write_misses 15498 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu2.dtb.flush_tlb 1186 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.flush_tlb_mva_asid 6329 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 174 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 21839 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 87 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 2106 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.perms_faults 3581 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 28304424 # DTB read accesses
system.cpu2.dtb.write_accesses 24578501 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.dtb.hits 52789012 # DTB hits
system.cpu2.dtb.misses 93913 # DTB misses
system.cpu2.dtb.accesses 52882925 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.itb.walker.walks 26523 # Table walker walks requested
system.cpu2.itb.walker.walksLong 26523 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1844 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22169 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 26523 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 26523 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 26523 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 24013 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 29387.415150 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 26253.368545 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 17691.333892 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767 11731 48.85% 48.85% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535 12005 49.99% 98.85% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303 1 0.00% 98.85% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839 207 0.86% 99.71% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607 44 0.18% 99.90% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.91% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143 5 0.02% 99.93% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911 11 0.05% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679 4 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 24013 # Table walker service (enqueue to completion) latency
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.itb.walker.walkPageSizes::4K 22169 92.32% 92.32% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M 1844 7.68% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 24013 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 26523 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 26523 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24013 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24013 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 50536 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 67723691 # ITB inst hits
system.cpu2.itb.inst_misses 26523 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu2.itb.flush_tlb 1186 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.itb.flush_tlb_mva_asid 6329 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 174 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 16138 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.itb.perms_faults 54061 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.itb.inst_accesses 67750214 # ITB inst accesses
system.cpu2.itb.hits 67723691 # DTB hits
system.cpu2.itb.misses 26523 # DTB misses
system.cpu2.itb.accesses 67750214 # DTB accesses
system.cpu2.numCycles 6659048617 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.committedInsts 144506436 # Number of instructions committed
system.cpu2.committedOps 169371182 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 13466455 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 1418 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 95896546126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 46.081329 # CPI: cycles per instruction
system.cpu2.ipc 0.021701 # IPC: instructions per cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu2.tickCycles 268737972 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 6390310645 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 73239801 # Number of BP lookups
system.cpu3.branchPred.condPredicted 49591629 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 3277800 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 49581893 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 35671982 # Number of BTB hits
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.branchPred.BTBHitPct 71.945583 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 9593725 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 104101 # Number of incorrect RAS predictions.
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.walker.walks 505460 # Table walker walks requested
system.cpu3.dtb.walker.walksLong 505460 # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8485 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50148 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 317089 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 188371 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 2400.557942 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 14374.756208 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535 187128 99.34% 99.34% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071 697 0.37% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607 376 0.20% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143 72 0.04% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679 52 0.03% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751 17 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::458752-524287 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total 188371 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 238710 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 23086.443802 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 18810.822067 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 18314.114651 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-65535 233850 97.96% 97.96% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3840 1.61% 99.57% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-196607 732 0.31% 99.88% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-262143 60 0.03% 99.90% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-327679 102 0.04% 99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-458751 30 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 238710 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -29357088016 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean 0.121049 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -29941141016 101.99% 101.99% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7 322648500 -1.10% 100.89% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11 112094000 -0.38% 100.51% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15 67602000 -0.23% 100.28% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19 26479500 -0.09% 100.19% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23 15506000 -0.05% 100.14% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27 14594500 -0.05% 100.09% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31 20339000 -0.07% 100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35 4463500 -0.02% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39 262500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43 36500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47 11000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51 16000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -29357088016 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 50148 85.53% 85.53% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M 8485 14.47% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 58633 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 505460 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 505460 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58633 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58633 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 564093 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.read_hits 58374270 # DTB read hits
system.cpu3.dtb.read_misses 343208 # DTB read misses
system.cpu3.dtb.write_hits 45394406 # DTB write hits
system.cpu3.dtb.write_misses 162252 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu3.dtb.flush_tlb 1185 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.flush_tlb_mva_asid 11285 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries 30021 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 85 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.perms_faults 33059 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 58717478 # DTB read accesses
system.cpu3.dtb.write_accesses 45556658 # DTB write accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.dtb.hits 103768676 # DTB hits
system.cpu3.dtb.misses 505460 # DTB misses
system.cpu3.dtb.accesses 104274136 # DTB accesses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.itb.walker.walks 59314 # Table walker walks requested
system.cpu3.itb.walker.walksLong 59314 # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1821 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40895 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 8206 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 51108 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1703.676528 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 11026.142257 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-65535 50913 99.62% 99.62% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-131071 102 0.20% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-196607 75 0.15% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-262143 8 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::327680-393215 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 51108 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 50922 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 29945.907466 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 25308.766579 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 21817.874172 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-32767 25421 49.92% 49.92% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-65535 24387 47.89% 97.81% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-98303 352 0.69% 98.50% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::98304-131071 53 0.10% 98.61% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-163839 469 0.92% 99.53% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::163840-196607 137 0.27% 99.80% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.84% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::229376-262143 18 0.04% 99.87% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-294911 34 0.07% 99.94% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::294912-327679 8 0.02% 99.96% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::360448-393215 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::393216-425983 10 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 50922 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -29359762516 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 0.915313 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::stdev 0.271710 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 -2440067696 8.31% 8.31% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -26959816320 91.83% 100.14% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 35306500 -0.12% 100.02% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 3658500 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 936500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5 210500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::6 9500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -29359762516 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 40895 95.74% 95.74% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M 1821 4.26% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 42716 # Table walker page sizes translated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59314 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59314 # Table walker requests started/completed, data/inst
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42716 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42716 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 102030 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 52851082 # ITB inst hits
system.cpu3.itb.inst_misses 59314 # ITB inst misses
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu3.itb.flush_tlb 1185 # Number of times complete TLB was flushed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.itb.flush_tlb_mva_asid 11285 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 309 # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries 23077 # Number of entries that have been flushed from TLB
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.itb.perms_faults 115085 # Number of TLB faults due to permissions restrictions
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.itb.inst_accesses 52910396 # ITB inst accesses
system.cpu3.itb.hits 52851082 # DTB hits
system.cpu3.itb.misses 59314 # DTB misses
system.cpu3.itb.accesses 52910396 # DTB accesses
system.cpu3.numCycles 366771262 # number of cpu cycles simulated
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.fetch.icacheStallCycles 138418640 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 325485816 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 73239801 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 45265707 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 205393679 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 7423141 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 1497672 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 9430 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 2924706 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 99692 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 5815 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 52718711 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 2024184 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 23519 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 352062887 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.083114 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.330461 # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.fetch.rateDist::0 271718451 77.18% 77.18% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 10078354 2.86% 80.04% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 10184487 2.89% 82.93% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 7481893 2.13% 85.06% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 15414285 4.38% 89.44% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 5033705 1.43% 90.87% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 5437919 1.54% 92.41% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 4732299 1.34% 93.76% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 21981494 6.24% 100.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.fetch.rateDist::total 352062887 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.199688 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.887435 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 113153102 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 169455061 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 59387304 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 7156871 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2908724 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 10935425 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 813859 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 356017985 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 2501114 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 2908724 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 117268615 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 13616294 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 135215564 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 62340466 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 20711186 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 347737029 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 54468 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 1175747 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 937238 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 10392106 # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents 2088 # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands 332468090 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 532744217 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 410951019 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 499537 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 279653291 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 52814794 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 7988531 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 6878375 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 39718769 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 56231921 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 47708003 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 7270204 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 7954464 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 330360579 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 7980408 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 330210395 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 469256 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 44146528 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 28275391 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 197239 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 352062887 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.937930 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.662080 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.issued_per_cycle::0 223668227 63.53% 63.53% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 53015699 15.06% 78.59% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 24255391 6.89% 85.48% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 17227433 4.89% 90.37% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 12830165 3.64% 94.02% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 9047221 2.57% 96.59% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 6060563 1.72% 98.31% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 3584032 1.02% 99.33% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 2374156 0.67% 100.00% # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.issued_per_cycle::total 352062887 # Number of insts issued each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.fu_full::IntAlu 1667670 25.64% 25.64% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 16900 0.26% 25.90% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 1465 0.02% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 2 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.93% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 2634602 40.51% 66.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 2182377 33.56% 100.00% # attempts to use FU when none available
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 223824222 67.78% 67.78% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 774202 0.23% 68.02% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 40056 0.01% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 168 0.00% 68.03% # Type of FU issued
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.03% # Type of FU issued
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.03% # Type of FU issued
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.FU_type_0::SimdFloatMisc 44646 0.01% 68.04% # Type of FU issued
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.FU_type_0::MemRead 59535864 18.03% 86.07% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 45991226 13.93% 100.00% # Type of FU issued
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iq.FU_type_0::total 330210395 # Type of FU issued
system.cpu3.iq.rate 0.900317 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 6503016 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.019694 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 1018785662 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 382537276 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 318334132 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 670287 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 332759 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 299480 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 336355093 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 358307 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 2644941 # Number of loads that had data forwarded from stores
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iew.lsq.thread0.squashedLoads 8880043 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 11323 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 388636 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 4860112 # Number of stores squashed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iew.lsq.thread0.rescheduledLoads 2108647 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 4155835 # Number of times an access to memory failed due to the cache being blocked
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iew.iewSquashCycles 2908724 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 8517603 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 3858124 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 338416485 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 997667 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 56231921 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 47708003 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 6730848 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 119383 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 3692835 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 388636 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 1480307 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1295138 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 2775445 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 326459428 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 58365019 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 3251449 # Number of squashed instructions skipped in execute
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.iew.exec_nop 75498 # number of nop insts executed
system.cpu3.iew.exec_refs 103758179 # number of memory reference insts executed
system.cpu3.iew.exec_branches 60585574 # Number of branches executed
system.cpu3.iew.exec_stores 45393160 # Number of stores executed
system.cpu3.iew.exec_rate 0.890090 # Inst execution rate
system.cpu3.iew.wb_sent 319299995 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 318633612 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 157331551 # num instructions producing a value
system.cpu3.iew.wb_consumers 273213532 # num instructions consuming a value
system.cpu3.iew.wb_rate 0.868753 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.575856 # average fanout of values written-back
system.cpu3.commit.commitSquashedInsts 44171670 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7783169 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 2474762 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 344535281 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.853888 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.850951 # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.commit.committed_per_cycle::0 237617500 68.97% 68.97% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 51794932 15.03% 84.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 18673564 5.42% 89.42% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 8409945 2.44% 91.86% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 6103204 1.77% 93.63% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 3702818 1.07% 94.71% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 3412254 0.99% 95.70% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 2146383 0.62% 96.32% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 12674681 3.68% 100.00% # Number of insts commited each cycle
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.commit.committed_per_cycle::total 344535281 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 250269181 # Number of instructions committed
system.cpu3.commit.committedOps 294194454 # Number of ops (including micro ops) committed
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.commit.refs 90199768 # Number of memory references committed
system.cpu3.commit.loads 47351877 # Number of loads committed
system.cpu3.commit.membars 1984419 # Number of memory barriers committed
system.cpu3.commit.branches 55927856 # Number of branches committed
system.cpu3.commit.fp_insts 287957 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 270378967 # Number of committed integer instructions.
system.cpu3.commit.function_calls 7437415 # Number of function calls committed.
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.commit.op_class_0::IntAlu 203317857 69.11% 69.11% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 607807 0.21% 69.32% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 30328 0.01% 69.33% # Class of committed instruction
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.commit.op_class_0::SimdFloatMisc 38694 0.01% 69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 47351877 16.10% 85.44% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 42847891 14.56% 100.00% # Class of committed instruction
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.cpu3.commit.op_class_0::total 294194454 # Class of committed instruction
system.cpu3.commit.bw_lim_events 12674681 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 668190501 # The number of ROB reads
system.cpu3.rob.rob_writes 684271435 # The number of ROB writes
system.cpu3.timesIdled 2367007 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 14708375 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 98631571593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 250269181 # Number of Instructions Simulated
system.cpu3.committedOps 294194454 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.465507 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.465507 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.682358 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.682358 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 384861666 # number of integer regfile reads
system.cpu3.int_regfile_writes 227851781 # number of integer regfile writes
system.cpu3.fp_regfile_reads 577247 # number of floating regfile reads
system.cpu3.fp_regfile_writes 366452 # number of floating regfile writes
system.cpu3.cc_regfile_reads 69640374 # number of cc regfile reads
system.cpu3.cc_regfile_writes 70304463 # number of cc regfile writes
system.cpu3.misc_regfile_reads 653638120 # number of misc regfile reads
system.cpu3.misc_regfile_writes 7847503 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40268 # Transaction distribution
system.iobus.trans_dist::ReadResp 40268 # Transaction distribution
system.iobus.trans_dist::WriteReq 136537 # Transaction distribution
system.iobus.trans_dist::WriteResp 136537 # Transaction distribution
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_count::total 353610 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.pkt_size::total 7492064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 30025500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer2.occupancy 84500 # Layer occupancy (ticks)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 5500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer23.occupancy 12632000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer24.occupancy 21450000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.reqLayer25.occupancy 266387325 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.respLayer0.occupancy 55488000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iobus.respLayer3.occupancy 76928000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.replacements 115463 # number of replacements
system.iocache.tags.tagsinuse 10.420638 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.warmup_cycle 13089107754009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.547310 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.873329 # Average occupied blocks per requestor
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.iocache.tags.occ_percent::realview.ethernet 0.221707 # Average percentage of cache occupancy
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.occ_percent::realview.ide 0.429583 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651290 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
system.iocache.tags.data_accesses 1039686 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.overall_misses::realview.ide 8817 # number of overall misses
system.iocache.overall_misses::total 8857 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 1084750278 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1084750278 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 6232375047 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 6232375047 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 1084750278 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1084750278 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 1084750278 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1084750278 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 123029.406601 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122515.278744 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58429.976815 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 58429.976815 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 123029.406601 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 122473.780964 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 123029.406601 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 122473.780964 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 22350 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.blocked::no_mshrs 2283 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.789750 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.iocache.ReadReq_mshr_misses::realview.ide 5720 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 5720 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 49552 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 49552 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 5720 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 5720 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 5720 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 5720 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 798750278 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 798750278 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3752561184 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3752561184 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 798750278 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 798750278 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 798750278 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 798750278 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.648747 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.646036 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.464562 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.464562 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.648747 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.645817 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.648747 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.645817 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139641.656993 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 139641.656993 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75729.762351 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75729.762351 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 139641.656993 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 139641.656993 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 139641.656993 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 139641.656993 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.tags.replacements 1152001 # number of replacements
system.l2c.tags.tagsinuse 65364.503704 # Cycle average of tags in use
system.l2c.tags.total_refs 47325190 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1214241 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 38.975121 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.tags.occ_blocks::writebacks 36534.063150 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 140.857117 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 210.834659 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3951.941056 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 8895.013876 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 26.293145 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 42.761147 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 396.523627 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1954.511694 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 39.315280 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 54.611947 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1674.225724 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3526.758908 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 87.445501 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker 133.246574 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 2425.897125 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 5270.203173 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.557466 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002149 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003217 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.060302 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.135727 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000401 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000652 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.006050 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.029823 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000600 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000833 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.025547 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.053814 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001334 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker 0.002033 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.037016 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.080417 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.997383 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 364 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 61876 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 364 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 543 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2771 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5102 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53332 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.944153 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 418991554 # Number of tag accesses
system.l2c.tags.data_accesses 418991554 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 161707 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 111056 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 55681 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 42228 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 155392 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 57216 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 297207 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 110657 # number of ReadReq hits
system.l2c.ReadReq_hits::total 991144 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 7515525 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 7515525 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 15732455 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 15732455 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 3869 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1314 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 1461 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 2683 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9327 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 646802 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 198937 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 265889 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 470326 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1581954 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 5553301 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 1652567 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 3844981 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 4588985 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15639834 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 2479386 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 798102 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 1075132 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 1875111 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6227731 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 285085 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 90358 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data 128268 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data 228305 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 732016 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 161707 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 111056 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 5553301 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3126188 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 55681 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 42228 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 1652567 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 997039 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 155392 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 57216 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 3844981 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 1341021 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 297207 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 110657 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 4588985 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 2345437 # number of demand (read+write) hits
system.l2c.demand_hits::total 24440663 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 161707 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 111056 # number of overall hits
system.l2c.overall_hits::cpu0.inst 5553301 # number of overall hits
system.l2c.overall_hits::cpu0.data 3126188 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 55681 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 42228 # number of overall hits
system.l2c.overall_hits::cpu1.inst 1652567 # number of overall hits
system.l2c.overall_hits::cpu1.data 997039 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 155392 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 57216 # number of overall hits
system.l2c.overall_hits::cpu2.inst 3844981 # number of overall hits
system.l2c.overall_hits::cpu2.data 1341021 # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker 297207 # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker 110657 # number of overall hits
system.l2c.overall_hits::cpu3.inst 4588985 # number of overall hits
system.l2c.overall_hits::cpu3.data 2345437 # number of overall hits
system.l2c.overall_hits::total 24440663 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1246 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1267 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 329 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 291 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 497 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 462 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker 1040 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker 967 # number of ReadReq misses
system.l2c.ReadReq_misses::total 6099 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 13877 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::cpu3.data 9548 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 33887 # number of UpgradeReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_misses::cpu3.data 1 # number of SCUpgradeReq misses
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
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system.l2c.ReadCleanReq_misses::cpu1.inst 7035 # number of ReadCleanReq misses
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system.l2c.ReadCleanReq_misses::cpu3.inst 27340 # number of ReadCleanReq misses
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system.l2c.ReadSharedReq_misses::cpu1.data 27715 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 39815 # number of ReadSharedReq misses
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system.l2c.InvalidateReq_misses::cpu3.data 53050 # number of InvalidateReq misses
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system.l2c.demand_misses::cpu2.inst 23588 # number of demand (read+write) misses
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system.l2c.demand_misses::cpu3.inst 27340 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 182625 # number of demand (read+write) misses
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system.l2c.overall_misses::cpu0.inst 37699 # number of overall misses
system.l2c.overall_misses::cpu0.data 290632 # number of overall misses
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system.l2c.overall_misses::cpu1.inst 7035 # number of overall misses
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system.l2c.overall_misses::cpu2.inst 23588 # number of overall misses
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system.l2c.ReadReq_miss_latency::total 493532500 # number of ReadReq miss cycles
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system.l2c.ReadExReq_miss_latency::total 30108958000 # number of ReadExReq miss cycles
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system.l2c.ReadCleanReq_miss_latency::cpu2.inst 3152426500 # number of ReadCleanReq miss cycles
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system.l2c.ReadCleanReq_miss_latency::total 7800660998 # number of ReadCleanReq miss cycles
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system.l2c.ReadSharedReq_miss_latency::cpu3.data 10770788500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 19852258000 # number of ReadSharedReq miss cycles
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system.l2c.InvalidateReq_miss_latency::total 4366000 # number of InvalidateReq miss cycles
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system.l2c.demand_miss_latency::cpu1.data 10280582000 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu2.inst 3152426500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 13231261500 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::cpu3.itb.walker 133336500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 3722238498 # number of demand (read+write) miss cycles
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system.l2c.demand_miss_latency::total 58255409498 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 43558000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 40022000 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu2.itb.walker 62622000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 3152426500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 13231261500 # number of overall miss cycles
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system.l2c.overall_miss_latency::cpu3.itb.walker 133336500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 3722238498 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 26449372500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 58255409498 # number of overall miss cycles
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system.l2c.ReadReq_accesses::cpu0.itb.walker 112323 # number of ReadReq accesses(hits+misses)
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system.l2c.ReadReq_accesses::cpu1.itb.walker 42519 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 155889 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 57678 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker 298247 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker 111624 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 997243 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 7515525 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 7515525 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 15732455 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 15732455 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 17746 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5980 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 7257 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 12231 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 43214 # number of UpgradeReq accesses(hits+misses)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.SCUpgradeReq_accesses::cpu3.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::cpu3.data 576402 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 1978540 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 5591000 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 1659602 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 3868569 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu3.inst 4616325 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 15735496 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 2589154 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 825817 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 1114947 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu3.data 1951660 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 6481578 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 679112 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 108775 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu2.data 155044 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu3.data 281355 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 1224286 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 162953 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu1.inst 1659602 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu2.inst 3868569 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 1440266 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.dtb.walker 298247 # number of demand (read+write) accesses
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system.l2c.demand_accesses::cpu3.inst 4616325 # number of demand (read+write) accesses
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system.l2c.overall_accesses::cpu1.inst 1659602 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu3.itb.walker 111624 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 4616325 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 2528062 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 25192857 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.007646 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.011280 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005874 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.006844 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003188 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.008010 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003487 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.008663 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.006116 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.781979 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780268 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.798677 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 0.780639 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.784167 # miss rate for UpgradeReq accesses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.500000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.666667 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.218523 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.201547 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.182682 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 0.184031 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.200444 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006743 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004239 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006097 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.005922 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.006079 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.042395 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.033561 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.035710 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.039223 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.039164 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.580209 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.169313 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu2.data 0.172699 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu3.data 0.188552 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.402087 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.007646 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu0.inst 0.006743 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.inst 0.004239 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.072496 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003188 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.itb.walker 0.008010 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.006097 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.068907 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003487 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.itb.walker 0.008663 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.005922 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.072239 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.029857 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.007646 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.011280 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.006743 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.085059 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005874 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.006844 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.004239 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.072496 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003188 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.itb.walker 0.008010 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.006097 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.068907 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003487 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.itb.walker 0.008663 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.005922 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.072239 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.029857 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132395.136778 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 137532.646048 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 139667.002012 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 135545.454545 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 139018.750000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 137886.763185 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 80920.232825 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 38576.403772 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 40761.128364 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 41169.826142 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 23883.450881 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131122.231958 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 132019.855292 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 147805.196274 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 75920.375404 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131627.007818 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 133645.349330 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 136146.250841 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 81543.988188 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 133362.727765 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 135258.608565 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 140704.496466 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 78205.604163 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 8.524733 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 37.888408 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 60.216777 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 8.869117 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132395.136778 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 137532.646048 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 131627.007818 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 131919.030938 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 139667.002012 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.itb.walker 135545.454545 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 133645.349330 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 133319.174770 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 139018.750000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.itb.walker 137886.763185 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 136146.250841 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 144828.870637 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 77447.320104 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132395.136778 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 137532.646048 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 131627.007818 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 131919.030938 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 139667.002012 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.itb.walker 135545.454545 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 133645.349330 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 133319.174770 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 139018.750000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.itb.walker 137886.763185 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 136146.250841 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 144828.870637 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 77447.320104 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.writebacks::writebacks 959163 # number of writebacks
system.l2c.writebacks::total 959163 # number of writebacks
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker 2 # number of ReadReq MSHR hits
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.ReadReq_mshr_hits::cpu3.itb.walker 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 2 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 3 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data 2 # number of demand (read+write) MSHR hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.demand_mshr_hits::cpu3.dtb.walker 2 # number of demand (read+write) MSHR hits
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.demand_mshr_hits::cpu3.itb.walker 11 # number of demand (read+write) MSHR hits
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.demand_mshr_hits::cpu3.data 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data 2 # number of overall MSHR hits
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.l2c.overall_mshr_hits::cpu3.dtb.walker 2 # number of overall MSHR hits
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.overall_mshr_hits::cpu3.itb.walker 11 # number of overall MSHR hits
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.overall_mshr_hits::cpu3.data 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 329 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 291 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 497 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 462 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 1038 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 956 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 3573 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 4666 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 5796 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 9548 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 20010 # number of UpgradeReq MSHR misses
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_mshr_misses::cpu1.data 50216 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 59430 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 106076 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 215722 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 7035 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 23588 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 27340 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 57963 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 27715 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 39813 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu3.data 76546 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 144074 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 18417 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu2.data 26776 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu3.data 53050 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 98243 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 329 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 291 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 7035 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 77931 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 497 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 462 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 23588 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 99243 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.dtb.walker 1038 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.itb.walker 956 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 27340 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 182622 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 421332 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 329 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 291 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 7035 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 77931 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 497 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 462 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 23588 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 99243 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.dtb.walker 1038 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.itb.walker 956 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 27340 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 182622 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 421332 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6822 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 6471 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu3.data 6195 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 19488 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6365 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5967 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu3.data 5946 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 18278 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13187 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 12438 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu3.data 12141 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 37766 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 40268000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 37112000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 64444500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 58002000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 133899506 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 122529505 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 456255511 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 316827000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 394164500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 649148500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 1360140000 # number of UpgradeReq MSHR miss cycles
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 69500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6082274000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 7251639002 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 14617462372 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 27951375374 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 855646000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2916543007 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 3448798584 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 7220987591 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 3418956583 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 4986972561 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 10004880216 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 18410809360 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1247334000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 1833774000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 3644679500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 6725787500 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 40268000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 37112000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 855646000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 9501230583 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 64444500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 58002000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 2916543007 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 12238611563 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 133899506 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 122529505 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 3448798584 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 24622342588 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 54039427836 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 40268000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 37112000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 855646000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 9501230583 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 64444500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 58002000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 2916543007 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 12238611563 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 133899506 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 122529505 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 3448798584 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 24622342588 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 54039427836 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1252584500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1172085500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1097573500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3522243500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1212082000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1118297000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1082758998 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 3413137998 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2464666500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2290382500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2180332498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 6935381498 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005874 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.006844 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003188 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.008010 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003480 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008564 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.003583 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780268 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.798677 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.780639 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.463044 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.201547 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.182682 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.184031 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.109031 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.004239 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006097 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005922 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003684 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033561 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.035708 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.039221 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.022228 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.169313 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.172699 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.188552 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.080245 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005874 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.006844 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004239 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.072496 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003188 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008010 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006097 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.068906 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003480 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008564 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005922 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.072238 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.016724 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005874 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006844 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004239 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.072496 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003188 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008010 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006097 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.068906 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003480 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008564 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005922 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.072238 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.016724 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127695.357123 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67901.200171 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68006.297447 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 67987.903226 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67973.013493 # average UpgradeReq mshr miss latency
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 69500 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121122.231958 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 122019.838499 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137801.787134 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 129571.278655 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121627.007818 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123645.201246 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 126144.790929 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124579.259027 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 123361.233375 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 125259.904077 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 130704.154574 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127787.174369 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 67727.317153 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 68485.733493 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 68702.723845 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 68460.730027 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121627.007818 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121918.499480 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123645.201246 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123319.645345 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 126144.790929 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134826.814885 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 128258.541568 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122395.136778 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127532.646048 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121627.007818 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121918.499480 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 129667.002012 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 125545.454545 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123645.201246 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123319.645345 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 128997.597303 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 128168.938285 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 126144.790929 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134826.814885 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 128258.541568 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183609.571973 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181128.959975 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 177170.863600 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180739.095854 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190429.222310 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 187413.608178 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 182098.721493 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 186734.762994 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 186901.228483 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 184143.954012 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 179584.259781 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 183640.880633 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::ReadReq 76733 # Transaction distribution
system.membus.trans_dist::ReadResp 441177 # Transaction distribution
system.membus.trans_dist::WriteReq 33644 # Transaction distribution
system.membus.trans_dist::WriteResp 33644 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1065794 # Transaction distribution
system.membus.trans_dist::CleanEvict 200684 # Transaction distribution
system.membus.trans_dist::UpgradeReq 34575 # Transaction distribution
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.trans_dist::UpgradeResp 14206 # Transaction distribution
system.membus.trans_dist::ReadExReq 395991 # Transaction distribution
system.membus.trans_dist::ReadExResp 395991 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 364444 # Transaction distribution
system.membus.trans_dist::InvalidateReq 598844 # Transaction distribution
system.membus.trans_dist::InvalidateResp 451105 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3680339 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3809718 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295481 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 295481 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4105199 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 109670240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 109839634 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7296832 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7296832 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 117136466 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1635 # Total snoops (count)
system.membus.snoop_fanout::samples 2770738 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::1 2770738 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.snoop_fanout::total 2770738 # Request fanout histogram
system.membus.reqLayer0.occupancy 64261000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.reqLayer2.occupancy 1770502 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.reqLayer5.occupancy 3078925491 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.respLayer2.occupancy 2289724659 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.membus.respLayer3.occupancy 28858376 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_filter.tot_requests 51493979 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 26073999 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 3069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2287 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.trans_dist::ReadReq 1482158 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23699758 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 7970176 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 15734993 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2276280 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 43214 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 43217 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1978540 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1978540 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 15735581 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6487298 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1273838 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1224286 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47292320 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29274050 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 815247 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1729718 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 79111335 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2014283796 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1022659326 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2960744 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6155576 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 3046059442 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1649768 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 38047944 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.016242 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.126407 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_fanout::0 37429952 98.38% 98.38% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 617992 1.62% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoop_fanout::total 38047944 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 30711072482 # Layer occupancy (ticks)
stats: Update stats to match cache changes
2015-11-06 09:26:50 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.snoopLayer0.occupancy 825172 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer0.occupancy 15222500163 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer1.occupancy 7880833554 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer2.occupancy 287037671 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.toL2Bus.respLayer3.occupancy 701756875 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats after Minor switcheroo inclusion
2015-07-30 11:16:36 +02:00
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
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