gem5/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                 178067                       # Simulator instruction rate (inst/s)
host_mem_usage                                 212832                       # Number of bytes of host memory used
host_seconds                                  2109.17                       # Real time elapsed on the host
host_tick_rate                               64635199                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   375574819                       # Number of instructions simulated
sim_seconds                                  0.136327                       # Number of seconds simulated
sim_ticks                                136326909500                       # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits                 35459307                       # Number of BTB hits
system.cpu.BPredUnit.BTBLookups              43810174                       # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect                1426                       # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect            5614078                       # Number of conditional branches incorrect
system.cpu.BPredUnit.condPredicted           35351284                       # Number of conditional branches predicted
system.cpu.BPredUnit.lookups                 62456368                       # Number of BP lookups
system.cpu.BPredUnit.usedRAS                 12662154                       # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches               44587532                       # Number of branches committed
system.cpu.commit.COM:bw_lim_events          12699878                       # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited                    0                       # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples    256761438                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean     1.552665                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev     2.229770                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::0    124458766     48.47%     48.47% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1     50855968     19.81%     68.28% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2     19650568      7.65%     75.93% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3     20252396      7.89%     83.82% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4     10775172      4.20%     88.02% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5      8940653      3.48%     91.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6      5548934      2.16%     93.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7      3579103      1.39%     95.05% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8     12699878      4.95%    100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::total    256761438                       # Number of insts commited each cycle
system.cpu.commit.COM:count                 398664594                       # Number of instructions committed
system.cpu.commit.COM:loads                  94754489                       # Number of loads committed
system.cpu.commit.COM:membars                       0                       # Number of memory barriers committed
system.cpu.commit.COM:refs                  168275218                       # Number of memory references committed
system.cpu.commit.COM:swp_count                     0                       # Number of s/w prefetches committed
system.cpu.commit.branchMispredicts           5609735                       # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts      398664594                       # The number of committed instructions
system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.commitSquashedInsts        98058240                       # The number of squashed insts skipped by commit
system.cpu.committedInsts                   375574819                       # Number of Instructions Simulated
system.cpu.committedInsts_total             375574819                       # Number of Instructions Simulated
system.cpu.cpi                               0.725964                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.725964                       # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits                3                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses           96258234                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 33424.104432                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31993.883792                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits               96256587                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency       55049500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.000017                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                 1647                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits               666                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency     31386000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses             981                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses          73520729                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 30170.708432                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35486.697966                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits              73502915                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency     537461000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.000242                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses               17814                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits            14619                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency    113380000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.000043                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses           3195                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs               40651.222462                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses           169778963                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 30446.045938                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34666.187739                       # average overall mshr miss latency
system.cpu.dcache.demand_hits               169759502                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency       592510500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.000115                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                 19461                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits              15285                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency    144766000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses             4176                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.804250                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0           3294.209288                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses          169778963                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 30446.045938                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34666.187739                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits              169759502                       # number of overall hits
system.cpu.dcache.overall_miss_latency      592510500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.000115                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                19461                       # number of overall misses
system.cpu.dcache.overall_mshr_hits             15285                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency    144766000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses            4176                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                    781                       # number of replacements
system.cpu.dcache.sampled_refs                   4176                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse               3294.209288                       # Cycle average of tags in use
system.cpu.dcache.total_refs                169759505                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                      662                       # number of writebacks
system.cpu.decode.DECODE:BlockedCycles       21274693                       # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred           4421                       # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved      11335478                       # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts       536362282                       # Number of instructions handled by decode
system.cpu.decode.DECODE:IdleCycles         133648516                       # Number of cycles decode is idle
system.cpu.decode.DECODE:RunCycles          100614513                       # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles        15751437                       # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts          13226                       # Number of squashed instructions handled by decode
system.cpu.decode.DECODE:UnblockCycles        1223716                       # Number of cycles decode is unblocking
system.cpu.dtb.data_accesses                185361756                       # DTB accesses
system.cpu.dtb.data_acv                             1                       # DTB access violations
system.cpu.dtb.data_hits                    185333824                       # DTB hits
system.cpu.dtb.data_misses                      27932                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                105061264                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                    105034802                       # DTB read hits
system.cpu.dtb.read_misses                      26462                       # DTB read misses
system.cpu.dtb.write_accesses                80300492                       # DTB write accesses
system.cpu.dtb.write_acv                            1                       # DTB write access violations
system.cpu.dtb.write_hits                    80299022                       # DTB write hits
system.cpu.dtb.write_misses                      1470                       # DTB write misses
system.cpu.fetch.Branches                    62456368                       # Number of branches that fetch encountered
system.cpu.fetch.CacheLines                  64427463                       # Number of cache lines fetched
system.cpu.fetch.Cycles                     104167812                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes               1484985                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts                      548969588                       # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles                  304                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.SquashCycles                 6021463                       # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate                  0.229068                       # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles           64427463                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches           48121461                       # Number of branches that fetch has predicted taken
system.cpu.fetch.rate                        2.013431                       # Number of inst fetches per cycle
system.cpu.fetch.rateDist::samples          272512875                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.014472                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.018403                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                168345063     61.78%     61.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 11153110      4.09%     65.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 11633749      4.27%     70.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  6179991      2.27%     72.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 14406846      5.29%     77.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  9876694      3.62%     81.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  7175383      2.63%     83.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  3990457      1.46%     85.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 39751582     14.59%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            272512875                       # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses           64427463                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 32238.031366                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits               64422617                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency      156225500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.000075                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                 4846                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits               935                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency    120601500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.000061                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses            3911                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs               16472.159806                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses            64427463                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 32238.031366                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 30836.486832                       # average overall mshr miss latency
system.cpu.icache.demand_hits                64422617                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency       156225500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.000075                       # miss rate for demand accesses
system.cpu.icache.demand_misses                  4846                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                935                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency    120601500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.000061                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses             3911                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.891874                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0           1826.557172                       # Average occupied blocks per context
system.cpu.icache.overall_accesses           64427463                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 32238.031366                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 30836.486832                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits               64422617                       # number of overall hits
system.cpu.icache.overall_miss_latency      156225500                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.000075                       # miss rate for overall accesses
system.cpu.icache.overall_misses                 4846                       # number of overall misses
system.cpu.icache.overall_mshr_hits               935                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency    120601500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.000061                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses            3911                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                   1989                       # number of replacements
system.cpu.icache.sampled_refs                   3911                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse               1826.557172                       # Cycle average of tags in use
system.cpu.icache.total_refs                 64422617                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                          140947                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches                 51277692                       # Number of branches executed
system.cpu.iew.EXEC:nop                      27475837                       # number of nop insts executed
system.cpu.iew.EXEC:rate                     1.546858                       # Inst execution rate
system.cpu.iew.EXEC:refs                    185361805                       # number of memory reference insts executed
system.cpu.iew.EXEC:stores                   80300524                       # Number of stores executed
system.cpu.iew.EXEC:swp                             0                       # number of swp insts executed
system.cpu.iew.WB:consumers                 290508552                       # num instructions consuming a value
system.cpu.iew.WB:count                     417530576                       # cumulative count of insts written-back
system.cpu.iew.WB:fanout                     0.697486                       # average fanout of values written-back
system.cpu.iew.WB:penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers                 202625525                       # num instructions producing a value
system.cpu.iew.WB:rate                       1.531358                       # insts written-back per cycle
system.cpu.iew.WB:sent                      418298724                       # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts              6117740                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles                 3299737                       # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts             117580442                       # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts                241                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts           6436127                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts             92914841                       # Number of dispatched store instructions
system.cpu.iew.iewDispatchedInsts           496723261                       # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts             105061281                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           8627247                       # Number of squashed instructions skipped in execute
system.cpu.iew.iewExecutedInsts             421756759                       # Number of executed instructions
system.cpu.iew.iewIQFullEvents                 169659                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents                 28133                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles               15751437                       # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles                607162                       # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads         8600585                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses        30861                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation       663165                       # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads       175980                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads     22825953                       # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores     19394112                       # Number of stores squashed
system.cpu.iew.memOrderViolationEvents         663165                       # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect      1101512                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect        5016228                       # Number of branches that were predicted taken incorrectly
system.cpu.ipc                               1.377479                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.377479                       # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass        33581      0.01%      0.01% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu       175581687     40.80%     40.80% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult        2149994      0.50%     41.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv               0      0.00%     41.30% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd      34727338      8.07%     49.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCmp       7823215      1.82%     51.19% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatCvt       2961066      0.69%     51.88% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatMult     16836878      3.91%     55.79% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatDiv       1569908      0.36%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAdd              0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu              0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCmp              0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdCvt              0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMisc             0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMult             0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShift            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdSqrt             0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt            0      0.00%     56.16% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemRead      106389727     24.72%     80.88% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite      82310612     19.12%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess            0      0.00%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch            0      0.00%    100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::total        430384006                       # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt               8629906                       # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate             0.020052                       # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass             0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu             24317      0.28%      0.28% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult                0      0.00%      0.28% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv                 0      0.00%      0.28% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd           44159      0.51%      0.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp            3134      0.04%      0.83% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCvt            6690      0.08%      0.91% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatMult        1184776     13.73%     14.64% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatDiv          981942     11.38%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatSqrt              0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAdd                0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAddAcc             0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdAlu                0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCmp                0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdCvt                0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMisc               0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMult               0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdMultAcc            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShift              0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdShiftAcc            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdSqrt               0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAdd            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatAlu            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCmp            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatCvt            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatDiv            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMisc            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt            0      0.00%     26.01% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemRead          5222594     60.52%     86.53% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite         1162294     13.47%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess              0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:issued_per_cycle::samples    272512875                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::mean     1.579316                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::stdev     1.717067                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::0     101003308     37.06%     37.06% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::1      58496079     21.47%     58.53% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::2      41698303     15.30%     73.83% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::3      27977806     10.27%     84.10% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::4      23760656      8.72%     92.82% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::5      11524865      4.23%     97.05% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::6       5162499      1.89%     98.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7       2198912      0.81%     99.75% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8        690447      0.25%    100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::total    272512875                       # Number of insts issued each cycle
system.cpu.iq.ISSUE:rate                     1.578500                       # Inst issue rate
system.cpu.iq.iqInstsAdded                  469247183                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued                 430384006                       # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded                 241                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqSquashedInstsExamined        92662056                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued            866219                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved             26                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined     70475093                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses                64427767                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                    64427463                       # ITB hits
system.cpu.itb.fetch_misses                       304                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses            3199                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 34601.370736                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.240357                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits                  62                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency    108544500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate       0.980619                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses              3137                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency     98684500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.980619                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses         3137                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses              4888                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34357.345635                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.742134                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                   661                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency     145228500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.864771                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                4227                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency    131754500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.864771                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses           4227                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses             662                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits                 662                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.153637                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses               8087                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 34461.298207                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31292.639870                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                    723                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency      253773000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.910597                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                 7364                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency    230439000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.910597                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses            7364                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.108677                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1                  0.011575                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0          3561.129355                       # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1           379.284506                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses              8087                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34461.298207                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31292.639870                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                   723                       # number of overall hits
system.cpu.l2cache.overall_miss_latency     253773000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.910597                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                7364                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency    230439000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.910597                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses           7364                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                    13                       # number of replacements
system.cpu.l2cache.sampled_refs                  4771                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse              3940.413861                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                     733                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.memDep0.conflictingLoads          71937561                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         54246192                       # Number of conflicting stores.
system.cpu.memDep0.insertedLoads            117580442                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            92914841                       # Number of stores inserted to the mem dependence unit.
system.cpu.numCycles                        272653822                       # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles         10643219                       # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps      259532341                       # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents         2331141                       # Number of times rename has blocked due to IQ full
system.cpu.rename.RENAME:IdleCycles         138476212                       # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents        7076079                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents              2                       # Number of times rename has blocked due to ROB full
system.cpu.rename.RENAME:RenameLookups      688559814                       # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts       522801702                       # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands    337940166                       # Number of destination operands rename has renamed
system.cpu.rename.RENAME:RunCycles           96677987                       # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles        15751437                       # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles       10596756                       # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps          78407825                       # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles       367264                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts        37559                       # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts           23060243                       # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts          258                       # count of temporary serializing insts renamed
system.cpu.timesIdled                            3093                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls             215                       # Number of system calls

---------- End Simulation Statistics   ----------