2007-02-01 00:47:23 +01:00
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---------- Begin Simulation Statistics ----------
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2010-09-22 08:07:35 +02:00
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host_inst_rate 209084 # Simulator instruction rate (inst/s)
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host_mem_usage 200220 # Number of bytes of host memory used
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host_seconds 1796.28 # Real time elapsed on the host
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host_tick_rate 75032789 # Simulator tick rate (ticks/s)
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2007-02-01 00:47:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2008-02-26 08:20:40 +01:00
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sim_insts 375574819 # Number of instructions simulated
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2010-09-22 08:07:35 +02:00
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sim_seconds 0.134780 # Number of seconds simulated
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sim_ticks 134780256500 # Number of ticks simulated
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2010-09-22 08:07:35 +02:00
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system.cpu.BPredUnit.BTBHits 34013245 # Number of BTB hits
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system.cpu.BPredUnit.BTBLookups 43763729 # Number of BTB lookups
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system.cpu.BPredUnit.RASInCorrect 1420 # Number of incorrect RAS predictions.
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system.cpu.BPredUnit.condIncorrect 5537198 # Number of conditional branches incorrect
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system.cpu.BPredUnit.condPredicted 35178330 # Number of conditional branches predicted
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system.cpu.BPredUnit.lookups 62077463 # Number of BP lookups
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system.cpu.BPredUnit.usedRAS 12488414 # Number of times the RAS was used to get a target.
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2008-02-26 08:20:40 +01:00
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system.cpu.commit.COM:branches 44587532 # Number of branches committed
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2010-09-22 08:07:35 +02:00
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system.cpu.commit.COM:bw_lim_events 13095097 # number cycles where commit BW limit reached
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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2010-09-22 08:07:35 +02:00
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system.cpu.commit.COM:committed_per_cycle::samples 254238271 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::mean 1.568075 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::stdev 2.238705 # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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2010-09-22 08:07:35 +02:00
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system.cpu.commit.COM:committed_per_cycle::0 122261214 48.09% 48.09% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::1 50419868 19.83% 67.92% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::2 19851999 7.81% 75.73% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::3 19999442 7.87% 83.60% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::4 10886968 4.28% 87.88% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::5 9291241 3.65% 91.53% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::6 5249545 2.06% 93.60% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::7 3182897 1.25% 94.85% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::8 13095097 5.15% 100.00% # Number of insts commited each cycle
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2009-07-07 00:49:48 +02:00
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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2010-09-22 08:07:35 +02:00
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system.cpu.commit.COM:committed_per_cycle::total 254238271 # Number of insts commited each cycle
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2008-02-26 08:20:40 +01:00
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system.cpu.commit.COM:count 398664594 # Number of instructions committed
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system.cpu.commit.COM:loads 100651995 # Number of loads committed
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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2008-02-26 08:20:40 +01:00
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system.cpu.commit.COM:refs 174183397 # Number of memory references committed
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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2010-09-22 08:07:35 +02:00
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system.cpu.commit.branchMispredicts 5532855 # The number of times a branch was mispredicted
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2008-02-26 08:20:40 +01:00
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system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
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2007-02-01 00:47:23 +01:00
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system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
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2010-09-22 08:07:35 +02:00
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system.cpu.commit.commitSquashedInsts 94873241 # The number of squashed insts skipped by commit
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2008-02-26 08:20:40 +01:00
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system.cpu.committedInsts 375574819 # Number of Instructions Simulated
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system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
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2010-09-22 08:07:35 +02:00
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system.cpu.cpi 0.717728 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.717728 # CPI: Total CPI of All Threads
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.ReadReq_accesses 95565604 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 33374.015748 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31987.257900 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 95563953 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 55100500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1651 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 670 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 31379500 # number of ReadReq MSHR miss cycles
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
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2008-03-18 04:07:22 +01:00
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system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.WriteReq_avg_miss_latency 30116.133558 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35471.048513 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73502909 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 536669500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 17820 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 14625 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 113330000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.avg_refs 40485.360393 # Average number of references to valid blocks.
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.demand_accesses 169086333 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 30392.378409 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 169066862 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 591770000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000115 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 19471 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 15295 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 144709500 # number of demand (read+write) MSHR miss cycles
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2008-02-26 08:20:40 +01:00
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system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.occ_%::0 0.804225 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 3294.106020 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 169086333 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 30392.378409 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency
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2009-04-22 19:25:17 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.overall_hits 169066862 # number of overall hits
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system.cpu.dcache.overall_miss_latency 591770000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000115 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 19471 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 15295 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 144709500 # number of overall MSHR miss cycles
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2008-02-26 08:20:40 +01:00
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system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2010-09-09 20:40:19 +02:00
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system.cpu.dcache.replacements 781 # number of replacements
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system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.tagsinuse 3294.106020 # Cycle average of tags in use
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system.cpu.dcache.total_refs 169066865 # Total number of references to valid blocks.
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2007-02-01 00:47:23 +01:00
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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2010-09-22 08:07:35 +02:00
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system.cpu.dcache.writebacks 662 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 22152007 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 4419 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 11286796 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 532040738 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 132274950 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 98625859 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 15181213 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 13245 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 1185455 # Number of cycles decode is unblocking
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system.cpu.dtb.data_accesses 184734537 # DTB accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.dtb.data_acv 0 # DTB access violations
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2010-09-22 08:07:35 +02:00
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system.cpu.dtb.data_hits 184683089 # DTB hits
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system.cpu.dtb.data_misses 51448 # DTB misses
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2009-04-09 07:21:30 +02:00
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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2010-09-22 08:07:35 +02:00
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system.cpu.dtb.read_accesses 104442295 # DTB read accesses
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2008-08-04 00:13:29 +02:00
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system.cpu.dtb.read_acv 0 # DTB read access violations
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2010-09-22 08:07:35 +02:00
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system.cpu.dtb.read_hits 104392308 # DTB read hits
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system.cpu.dtb.read_misses 49987 # DTB read misses
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system.cpu.dtb.write_accesses 80292242 # DTB write accesses
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2010-09-09 20:40:19 +02:00
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system.cpu.dtb.write_acv 0 # DTB write access violations
|
2010-09-22 08:07:35 +02:00
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|
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system.cpu.dtb.write_hits 80290781 # DTB write hits
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system.cpu.dtb.write_misses 1461 # DTB write misses
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system.cpu.fetch.Branches 62077463 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 63755206 # Number of cache lines fetched
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system.cpu.fetch.Cycles 165857748 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 1527822 # Number of outstanding Icache misses that were squashed
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|
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system.cpu.fetch.Insts 544006695 # Number of instructions fetch has processed
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system.cpu.fetch.SquashCycles 5884776 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.230291 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 63755206 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 46501659 # Number of branches that fetch has predicted taken
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|
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system.cpu.fetch.rate 2.018125 # Number of inst fetches per cycle
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|
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system.cpu.fetch.rateDist::samples 269419484 # Number of instructions fetched each cycle (Total)
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|
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system.cpu.fetch.rateDist::mean 2.019181 # Number of instructions fetched each cycle (Total)
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|
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system.cpu.fetch.rateDist::stdev 3.021968 # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
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|
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
2010-09-22 08:07:35 +02:00
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|
|
system.cpu.fetch.rateDist::0 167317249 62.10% 62.10% # Number of instructions fetched each cycle (Total)
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|
|
|
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system.cpu.fetch.rateDist::1 9830332 3.65% 65.75% # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.fetch.rateDist::2 10264297 3.81% 69.56% # Number of instructions fetched each cycle (Total)
|
|
|
|
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system.cpu.fetch.rateDist::3 7467850 2.77% 72.33% # Number of instructions fetched each cycle (Total)
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|
|
|
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system.cpu.fetch.rateDist::4 14528793 5.39% 77.73% # Number of instructions fetched each cycle (Total)
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|
|
|
system.cpu.fetch.rateDist::5 9632139 3.58% 81.30% # Number of instructions fetched each cycle (Total)
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|
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system.cpu.fetch.rateDist::6 7095921 2.63% 83.93% # Number of instructions fetched each cycle (Total)
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|
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|
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system.cpu.fetch.rateDist::7 3870398 1.44% 85.37% # Number of instructions fetched each cycle (Total)
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|
|
|
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system.cpu.fetch.rateDist::8 39412505 14.63% 100.00% # Number of instructions fetched each cycle (Total)
|
2009-07-07 00:49:48 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
|
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
2010-09-22 08:07:35 +02:00
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|
|
system.cpu.fetch.rateDist::total 269419484 # Number of instructions fetched each cycle (Total)
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 63755206 # number of ReadReq accesses(hits+misses)
|
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|
system.cpu.icache.ReadReq_avg_miss_latency 32282.788581 # average ReadReq miss latency
|
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 30880.348450 # average ReadReq mshr miss latency
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|
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|
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system.cpu.icache.ReadReq_hits 63750372 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 156055000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 4834 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 931 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 120526000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 3903 # number of ReadReq MSHR misses
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.avg_refs 16333.684858 # Average number of references to valid blocks.
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.demand_accesses 63755206 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 32282.788581 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits 63750372 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 156055000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 4834 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 931 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 120526000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 3903 # number of demand (read+write) MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.occ_%::0 0.891530 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 1825.852920 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses 63755206 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 32282.788581 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.overall_hits 63750372 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 156055000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 4834 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 931 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 120526000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 3903 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.replacements 1981 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.icache.tagsinuse 1825.852920 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 63750372 # Total number of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.idleCycles 141032 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 50928648 # Number of branches executed
|
|
|
|
|
system.cpu.iew.EXEC:nop 27198310 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.EXEC:rate 1.554098 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 191466035 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.EXEC:stores 80302922 # Number of stores executed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.WB:consumers 288648946 # num instructions consuming a value
|
|
|
|
|
system.cpu.iew.WB:count 415155943 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.WB:fanout 0.699341 # average fanout of values written-back
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.WB:producers 201863998 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.WB:rate 1.540121 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 415846665 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 6072161 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewBlockCycles 3214599 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 125039862 # Number of dispatched load instructions
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 6489838 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 92505583 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 493538259 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 111163113 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 8697897 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 418923368 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 138014 # Number of times the IQ has become full, causing a stall
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 28455 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 15181213 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 561595 # Number of cycles IEW is unblocking
|
2007-04-16 04:29:37 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 8650010 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 47350 # Number of memory responses ignored because the instruction is squashed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 540044 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 176691 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 24387867 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 18974181 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 540044 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 1086448 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 4985713 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 1.393286 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 1.393286 # IPC: Total IPC of All Threads
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntAlu 166094034 38.84% 38.85% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntMult 2150895 0.50% 39.35% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.35% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34767843 8.13% 47.48% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7837636 1.83% 49.32% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2956341 0.69% 50.01% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatMult 16811834 3.93% 53.94% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571362 0.37% 54.31% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.31% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemRead 113187864 26.47% 80.78% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::MemWrite 82209875 19.22% 100.00% # Type of FU issued
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:FU_type_0::total 427621265 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 9425623 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.022042 # FU busy rate (busy events/executed inst)
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IntAlu 22465 0.24% 0.24% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.24% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.24% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatAdd 44257 0.47% 0.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCmp 507 0.01% 0.71% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatCvt 7079 0.08% 0.79% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatMult 1310742 13.91% 14.69% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatDiv 1081807 11.48% 26.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.17% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemRead 5661778 60.07% 86.24% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::MemWrite 1296988 13.76% 100.00% # attempts to use FU when none available
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::samples 269419484 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::mean 1.587195 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.714658 # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::0 98807587 36.67% 36.67% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::1 58261038 21.62% 58.30% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::2 40917124 15.19% 73.49% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::3 29020181 10.77% 84.26% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::4 23205890 8.61% 92.87% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::5 11236315 4.17% 97.04% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::6 5001720 1.86% 98.90% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::7 2307051 0.86% 99.75% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::8 662578 0.25% 100.00% # Number of insts issued each cycle
|
2009-07-07 00:49:48 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle::total 269419484 # Number of insts issued each cycle
|
|
|
|
|
system.cpu.iq.ISSUE:rate 1.586365 # Inst issue rate
|
|
|
|
|
system.cpu.iq.iqInstsAdded 466339708 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 427621265 # Number of instructions issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.iqSquashedInstsExamined 89739850 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 704910 # Number of squashed instructions issued
|
2010-05-14 05:45:59 +02:00
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 69710487 # Number of squashed operands that are examined and possibly removed from graph
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
|
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
|
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
|
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.itb.fetch_accesses 63755513 # ITB accesses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.itb.fetch_hits 63755206 # ITB hits
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.itb.fetch_misses 307 # ITB misses
|
2009-04-09 07:21:30 +02:00
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34585.272553 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31456.646478 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 108494000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.980619 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98679500 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980619 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 4880 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34357.396450 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.467456 # average ReadReq mshr miss latency
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 145160000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.865779 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4225 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 131691000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865779 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4225 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.avg_refs 0.152443 # Average number of references to valid blocks.
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 8079 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34454.496061 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 253654000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.911251 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 7362 # number of demand (read+write) misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 230370500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.911251 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 7362 # number of demand (read+write) MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.occ_%::0 0.108627 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_%::1 0.011574 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_blocks::0 3559.477751 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 379.255991 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8079 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34454.496061 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.overall_hits 717 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 253654000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.911251 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7362 # number of overall misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 230370500 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.911251 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7362 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.replacements 13 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 4769 # Sample count of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 3938.733742 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks.
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.memDep0.conflictingLoads 72822522 # Number of conflicting loads.
|
|
|
|
|
system.cpu.memDep0.conflictingStores 52763057 # Number of conflicting stores.
|
|
|
|
|
system.cpu.memDep0.insertedLoads 125039862 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.memDep0.insertedStores 92505583 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
system.cpu.numCycles 269560516 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.rename.RENAME:BlockCycles 11010620 # Number of cycles rename is blocking
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.rename.RENAME:IQFullEvents 2256823 # Number of times rename has blocked due to IQ full
|
|
|
|
|
system.cpu.rename.RENAME:IdleCycles 137290050 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 7674469 # Number of times rename has blocked due to LSQ full
|
2008-08-04 00:13:29 +02:00
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
2010-09-22 08:07:35 +02:00
|
|
|
system.cpu.rename.RENAME:RenameLookups 683176131 # Number of register rename lookups that rename has made
|
|
|
|
|
system.cpu.rename.RENAME:RenamedInsts 518444566 # Number of instructions processed by rename
|
|
|
|
|
system.cpu.rename.RENAME:RenamedOperands 335488186 # Number of destination operands rename has renamed
|
|
|
|
|
system.cpu.rename.RENAME:RunCycles 94400681 # Number of cycles rename is running
|
|
|
|
|
system.cpu.rename.RENAME:SquashCycles 15181213 # Number of cycles rename is squashing
|
|
|
|
|
system.cpu.rename.RENAME:UnblockCycles 11169785 # Number of cycles rename is unblocking
|
|
|
|
|
system.cpu.rename.RENAME:UndoneMaps 75955845 # Number of HB maps that are undone due to squashing
|
|
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 367135 # count of cycles rename stalled for serializing inst
|
|
|
|
|
system.cpu.rename.RENAME:serializingInsts 37569 # count of serializing insts renamed
|
|
|
|
|
system.cpu.rename.RENAME:skidInsts 24308277 # count of insts added to the skid buffer
|
|
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 261 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 3095 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
