gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.817750                       # Number of seconds simulated
sim_ticks                                2817750443000                       # Number of ticks simulated
final_tick                               2817750443000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 301376                       # Simulator instruction rate (inst/s)
host_op_rate                                   365951                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             6727532391                       # Simulator tick rate (ticks/s)
host_mem_usage                                 628096                       # Number of bytes of host memory used
host_seconds                                   418.84                       # Real time elapsed on the host
sim_insts                                   126227981                       # Number of instructions simulated
sim_ops                                     153274395                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst           653732                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          4510496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           124544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1058884                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker         5696                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst           520896                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data          4080320                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             10955912                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst       653732                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       124544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst       520896                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1299172                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8264128                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17516                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             8                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8281652                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             18668                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data             70995                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              1946                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             16546                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker           89                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst              8139                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data             63755                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                180159                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          129127                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4379                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                2                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               133508                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker            91                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              232005                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             1600744                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker            23                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               44200                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              375791                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker          2021                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst              184862                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data             1448077                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              341                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 3888177                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         232005                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          44200                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst         184862                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             461067                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2932881                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6216                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  3                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2939101                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2932881                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker           91                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             232005                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            1606960                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker           23                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              44200                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             375793                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker         2021                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst             184862                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data            1448077                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             341                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6827277                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         90477                       # Number of read requests accepted
system.physmem.writeReqs                        65811                       # Number of write requests accepted
system.physmem.readBursts                       90477                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      65811                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  5784832                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5696                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4210432                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   5790468                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4211784                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       89                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          23137                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                5834                       # Per bank write bursts
system.physmem.perBankRdBursts::1                5704                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5463                       # Per bank write bursts
system.physmem.perBankRdBursts::3                5405                       # Per bank write bursts
system.physmem.perBankRdBursts::4                5372                       # Per bank write bursts
system.physmem.perBankRdBursts::5                5837                       # Per bank write bursts
system.physmem.perBankRdBursts::6                6284                       # Per bank write bursts
system.physmem.perBankRdBursts::7                6486                       # Per bank write bursts
system.physmem.perBankRdBursts::8                6223                       # Per bank write bursts
system.physmem.perBankRdBursts::9                6339                       # Per bank write bursts
system.physmem.perBankRdBursts::10               5440                       # Per bank write bursts
system.physmem.perBankRdBursts::11               5142                       # Per bank write bursts
system.physmem.perBankRdBursts::12               5381                       # Per bank write bursts
system.physmem.perBankRdBursts::13               5279                       # Per bank write bursts
system.physmem.perBankRdBursts::14               4952                       # Per bank write bursts
system.physmem.perBankRdBursts::15               5247                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4133                       # Per bank write bursts
system.physmem.perBankWrBursts::1                3840                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4117                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4118                       # Per bank write bursts
system.physmem.perBankWrBursts::4                3952                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4415                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4512                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4650                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4383                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4609                       # Per bank write bursts
system.physmem.perBankWrBursts::10               3956                       # Per bank write bursts
system.physmem.perBankWrBursts::11               3578                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4192                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4199                       # Per bank write bursts
system.physmem.perBankWrBursts::14               3505                       # Per bank write bursts
system.physmem.perBankWrBursts::15               3629                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
system.physmem.totGap                    2816184296500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       1                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   90476                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  65809                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     59474                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     27494                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      2874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       538                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                        58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                        55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                        54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                        52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                        52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                        51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                        51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                        51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                        51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                        51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1098                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3358                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4984                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4451                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     3853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4093                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4124                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     3437                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     3376                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     3245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      153                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      113                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       69                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       78                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       42                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        32481                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      307.722545                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     177.643491                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     335.464678                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          12661     38.98%     38.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         7717     23.76%     62.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         2982      9.18%     71.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1687      5.19%     77.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1406      4.33%     81.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          745      2.29%     83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          513      1.58%     85.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          495      1.52%     86.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4275     13.16%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          32481                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          3213                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        28.128852                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      487.877717                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           3211     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.03%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            3213                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          3213                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.475568                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.644293                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev       13.368139                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3                 6      0.19%      0.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7                 1      0.03%      0.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11                1      0.03%      0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15               2      0.06%      0.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19            2703     84.13%     84.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23              65      2.02%     86.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             109      3.39%     89.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              35      1.09%     90.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              33      1.03%     91.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             100      3.11%     95.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               9      0.28%     95.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               3      0.09%     95.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               4      0.12%     95.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               8      0.25%     95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               2      0.06%     95.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.03%     95.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             103      3.21%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.06%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75               3      0.09%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               4      0.12%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83               1      0.03%     99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               2      0.06%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.03%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.03%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             7      0.22%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.03%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.06%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             1      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             2      0.06%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            3213                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1180806250                       # Total ticks spent queuing
system.physmem.totMemAccLat                2875581250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    451940000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13063.75                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31813.75                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.05                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.49                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.05                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.49                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         6.07                       # Average write queue length when enqueuing
system.physmem.readRowHits                      74627                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     49067                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.56                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.56                       # Row buffer hit rate for writes
system.physmem.avgGap                     18019197.23                       # Average gap between requests
system.physmem.pageHitRate                      79.19                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  128285640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   69757875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 361803000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                218615760                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           178850889360                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            68913339435                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           1610809853250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             1859352544320                       # Total energy per rank (pJ)
system.physmem_0.averagePower              667.527151                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   2632589257000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     91437060000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     14382937750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  117270720                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   63772500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 343207800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                207690480                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           178850889360                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            68192676180                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           1609047407250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             1856822914290                       # Total energy per rank (pJ)
system.physmem_1.averagePower              667.575499                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   2633644277500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     91437060000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     13328364750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               7                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     5725                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                5725                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples         5725                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           5725    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         5725                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 166068997868                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.475665                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.499407                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0    87075845118     52.43%     52.43% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1    78993152750     47.57%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 166068997868                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         3165     67.41%     67.41% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1530     32.59%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         4695                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         5725                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         5725                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         4695                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         4695                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        10420                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    14454415                       # DTB read hits
system.cpu0.dtb.read_misses                      4808                       # DTB read misses
system.cpu0.dtb.write_hits                   11087884                       # DTB write hits
system.cpu0.dtb.write_misses                      917                       # DTB write misses
system.cpu0.dtb.flush_tlb                         190                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     446                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3341                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                   964                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      218                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                14459223                       # DTB read accesses
system.cpu0.dtb.write_accesses               11088801                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         25542299                       # DTB hits
system.cpu0.dtb.misses                           5725                       # DTB misses
system.cpu0.dtb.accesses                     25548024                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     2784                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                2784                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples         2784                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           2784    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         2784                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 166068997868                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.475665                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.499407                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    87075735118     52.43%     52.43% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1    78993262750     47.57%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 166068997868                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         1521     75.19%     75.19% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          502     24.81%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2023                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         2784                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         2784                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2023                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2023                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         4807                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    67912569                       # ITB inst hits
system.cpu0.itb.inst_misses                      2784                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                         190                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     446                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2012                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                67915353                       # ITB inst accesses
system.cpu0.itb.hits                         67912569                       # DTB hits
system.cpu0.itb.misses                           2784                       # DTB misses
system.cpu0.itb.accesses                     67915353                       # DTB accesses
system.cpu0.numCycles                        82537208                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.committedInsts                   66134007                       # Number of instructions committed
system.cpu0.committedOps                     80648826                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses             70905199                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  5550                       # Number of float alu accesses
system.cpu0.num_func_calls                    7283350                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts      8754499                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                    70905199                       # number of integer instructions
system.cpu0.num_fp_insts                         5550                       # number of float instructions
system.cpu0.num_int_register_reads          131519590                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          49325288                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                4326                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               1228                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           245878640                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           29383702                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     26210186                       # number of memory refs
system.cpu0.num_load_insts                   14630349                       # Number of load instructions
system.cpu0.num_store_insts                  11579837                       # Number of store instructions
system.cpu0.num_idle_cycles              77938505.493998                       # Number of idle cycles
system.cpu0.num_busy_cycles              4598702.506002                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.055717                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.944283                       # Percentage of idle cycles
system.cpu0.Branches                         16436363                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2195      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 55791644     67.98%     67.99% # Class of executed instruction
system.cpu0.op_class::IntMult                   58049      0.07%     68.06% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              4498      0.01%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     68.06% # Class of executed instruction
system.cpu0.op_class::MemRead                14630349     17.83%     85.89% # Class of executed instruction
system.cpu0.op_class::MemWrite               11579837     14.11%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                  82066572                       # Class of executed instruction
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    3052                       # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements           831549                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          511.997019                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           47051301                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           832061                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            56.547899                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   485.952083                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data    16.619501                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data     9.425436                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.949125                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data     0.032460                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data     0.018409                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          194                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        198549695                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       198549695                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     13772496                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data      4439535                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data      8487535                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       26699566                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     10693159                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data      3177520                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data      5185286                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      19055965                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       188127                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data        61521                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data       132231                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       381879                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       234713                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        80499                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data       136030                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       451242                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       236172                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data        82928                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data       140692                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       459792                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     24465655                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data      7617055                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data     13672821                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        45755531                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     24653782                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data      7678576                       # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data     13805052                       # number of overall hits
system.cpu0.dcache.overall_hits::total       46137410                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       187736                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data        59438                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data       321333                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       568507                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       147259                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data        35061                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data      1471187                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1653507                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data        54734                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data        20499                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data        66219                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       141452                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         4535                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         3220                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         9718                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total        17473                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data            3                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data           16                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       334995                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data        94499                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data      1792520                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       2222014                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       389729                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data       114998                       # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data      1858739                       # number of overall misses
system.cpu0.dcache.overall_misses::total      2363466                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    910326500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   4892855500                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total   5803182000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1430484500                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  70357084944                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total  71787569444                       # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     43754500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    128953000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total    172707500                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data       313500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total       313500                       # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data   2340811000                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data  75249940444                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total  77590751444                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data   2340811000                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data  75249940444                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total  77590751444                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     13960232                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data      4498973                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data      8808868                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     27268073                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     10840418                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data      3212581                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data      6656473                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     20709472                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       242861                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data        82020                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data       198450                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       523331                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       239248                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        83719                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data       145748                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       468715                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       236175                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        82928                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data       140708                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       459811                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     24800650                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data      7711554                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data     15465341                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     47977545                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     25043511                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data      7793574                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data     15663791                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     48500876                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.013448                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.013211                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.036478                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.020849                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.013584                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.010914                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.221016                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.079843                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.225372                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data     0.249927                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data     0.333681                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.270292                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.018955                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.038462                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.066677                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.037279                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000013                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000114                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000041                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.013508                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data     0.012254                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data     0.115906                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.046314                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.015562                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data     0.014755                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data     0.118665                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.048730                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15315.564117                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15226.744530                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10207.758216                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40799.877357                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 47823.346008                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43415.340512                       # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.354037                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13269.499897                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9884.249986                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 19593.750000                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        16500                       # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24770.748897                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41979.972577                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 34919.110070                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20355.232265                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40484.403913                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 32829.222610                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs       384529                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets        27036                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs            18388                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets            711                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    20.911953                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    38.025316                       # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks       690633                       # number of writebacks
system.cpu0.dcache.writebacks::total           690633                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data           93                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       159890                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total       159983                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data      1354576                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      1354576                       # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data         1940                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         6930                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total         8870                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data           93                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data      1514466                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total      1514559                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data           93                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data      1514466                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total      1514559                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        59345                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       161443                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total       220788                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        35061                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data       116611                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total       151672                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data        20123                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data        43935                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total        64058                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1280                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         2788                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total         4068                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data           16                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data        94406                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data       278054                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total       372460                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data       114529                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data       321989                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total       436518                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data         5882                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data         8601                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        14483                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data         4590                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data         6802                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        11392                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data        10472                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data        15403                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        25875                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    849299000                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   2242226500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3091525500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1395423500                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   5679297435                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7074720935                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data    276712000                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data    590115500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total    866827500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     20457500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     37492500                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57950000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data       297500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       297500                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   2244722500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   7921523935                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total  10166246435                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   2521434500                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   8511639435                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total  11033073935                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   1056963000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data   1715153500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   2772116500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    811573000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data   1342286000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2153859000                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data   1868536000                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data   3057439500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   4925975500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.013191                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.018327                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.008097                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.010914                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.017518                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007324                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.245343                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data     0.221391                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.122404                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.015289                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.019129                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.008679                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000114                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.012242                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.017979                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.007763                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.014695                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.020556                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.009000                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14311.214087                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13888.657297                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14002.235176                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39799.877357                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48702.930555                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46644.871400                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13751.031158                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13431.557983                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13531.916388                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15982.421875                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13447.812052                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14245.329400                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 18593.750000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18593.750000                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23777.328771                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28489.156549                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27294.867731                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22015.685983                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26434.565886                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25275.186670                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179694.491670                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 199413.265899                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191404.853967                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176813.289760                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 197336.959718                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189067.679073                       # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178431.627196                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 198496.364345                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190375.864734                       # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements          1799604                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.542681                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          100855692                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1800115                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            56.027360                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      10987259500                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   478.414957                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst    20.920922                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst    12.206802                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.934404                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst     0.040861                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst     0.023841                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999107                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          157                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        104509492                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       104509492                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     67050712                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst     21807219                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst     11997761                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      100855692                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     67050712                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst     21807219                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst     11997761                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       100855692                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     67050712                       # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst     21807219                       # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst     11997761                       # number of overall hits
system.cpu0.icache.overall_hits::total      100855692                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst       863880                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst       249894                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst       739869                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1853643                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst       863880                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst       249894                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst       739869                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1853643                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst       863880                       # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst       249894                       # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst       739869                       # number of overall misses
system.cpu0.icache.overall_misses::total      1853643                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   3388286000                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst  10019746984                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  13408032984                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst   3388286000                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst  10019746984                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  13408032984                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst   3388286000                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst  10019746984                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  13408032984                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst     67914592                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst     22057113                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst     12737630                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    102709335                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     67914592                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst     22057113                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst     12737630                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    102709335                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     67914592                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst     22057113                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst     12737630                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    102709335                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.012720                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.011329                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.058085                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.018047                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.012720                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst     0.011329                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst     0.058085                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.018047                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.012720                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst     0.011329                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst     0.058085                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.018047                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13558.892971                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13542.596033                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total  7233.341579                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13558.892971                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13542.596033                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total  7233.341579                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13558.892971                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13542.596033                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total  7233.341579                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs         7691                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs              418                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.399522                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        53485                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total        53485                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst        53485                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total        53485                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst        53485                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total        53485                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       249894                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       686384                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total       936278                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst       249894                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst       686384                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total       936278                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst       249894                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst       686384                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total       936278                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   3138392000                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   8843257984                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  11981649984                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   3138392000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   8843257984                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  11981649984                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   3138392000                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   8843257984                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  11981649984                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.053886                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009116                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.053886                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.009116                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.053886                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.009116                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12558.892971                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12883.834681                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12797.107252                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12558.892971                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12883.834681                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12797.107252                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12558.892971                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12883.834681                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12797.107252                       # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     1911                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                1911                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1          628                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2         1283                       # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples         1911                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           1911    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         1911                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples         1624                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 12817.118227                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11165.640992                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev  6539.405372                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191          417     25.68%     25.68% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383          849     52.28%     77.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575          357     21.98%     99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::81920-90111            1      0.06%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total         1624                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples   1000016000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     1000016000    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   1000016000                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1004     61.82%     61.82% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          620     38.18%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         1624                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         1911                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         1911                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         1624                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         1624                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         3535                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                     4670594                       # DTB read hits
system.cpu1.dtb.read_misses                      1655                       # DTB read misses
system.cpu1.dtb.write_hits                    3300164                       # DTB write hits
system.cpu1.dtb.write_misses                      256                       # DTB write misses
system.cpu1.dtb.flush_tlb                         167                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     123                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    1332                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   252                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                       65                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                 4672249                       # DTB read accesses
system.cpu1.dtb.write_accesses                3300420                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                          7970758                       # DTB hits
system.cpu1.dtb.misses                           1911                       # DTB misses
system.cpu1.dtb.accesses                      7972669                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                      935                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                 935                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1          229                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2          706                       # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples          935                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0            935    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total          935                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples          723                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 13501.383126                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11823.554991                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev  6487.735992                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-6143          166     22.96%     22.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287          228     31.54%     54.50% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335          139     19.23%     73.72% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::14336-16383            7      0.97%     74.69% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575          183     25.31%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total          723                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     1000000500    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   1000000500                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          494     68.33%     68.33% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          229     31.67%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total          723                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst          935                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total          935                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst          723                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total          723                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         1658                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    22057113                       # ITB inst hits
system.cpu1.itb.inst_misses                       935                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                         167                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     123                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                     783                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                22058048                       # ITB inst accesses
system.cpu1.itb.hits                         22057113                       # DTB hits
system.cpu1.itb.misses                            935                       # DTB misses
system.cpu1.itb.accesses                     22058048                       # DTB accesses
system.cpu1.numCycles                       158011873                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.committedInsts                   21342205                       # Number of instructions committed
system.cpu1.committedOps                     25582989                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             22730381                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1657                       # Number of float alu accesses
system.cpu1.num_func_calls                    2417962                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      2740367                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    22730381                       # number of integer instructions
system.cpu1.num_fp_insts                         1657                       # number of float instructions
system.cpu1.num_int_register_reads           41903720                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          15946634                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1337                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                320                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads            92962985                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes            9452948                       # number of times the CC registers were written
system.cpu1.num_mem_refs                      8180627                       # number of memory refs
system.cpu1.num_load_insts                    4716601                       # Number of load instructions
system.cpu1.num_store_insts                   3464026                       # Number of store instructions
system.cpu1.num_idle_cycles              151538894.643419                       # Number of idle cycles
system.cpu1.num_busy_cycles              6472978.356581                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.040965                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.959035                       # Percentage of idle cycles
system.cpu1.Branches                          5307887                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   38      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 18096671     68.81%     68.81% # Class of executed instruction
system.cpu1.op_class::IntMult                   19327      0.07%     68.89% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              1187      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     68.89% # Class of executed instruction
system.cpu1.op_class::MemRead                 4716601     17.94%     86.83% # Class of executed instruction
system.cpu1.op_class::MemWrite                3464026     13.17%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  26297850                       # Class of executed instruction
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
system.cpu2.branchPred.lookups               17205761                       # Number of BP lookups
system.cpu2.branchPred.condPredicted          9385761                       # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect           401350                       # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups            10751395                       # Number of BTB lookups
system.cpu2.branchPred.BTBHits                8022189                       # Number of BTB hits
system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct            74.615331                       # BTB Hit Percentage
system.cpu2.branchPred.usedRAS                4025562                       # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect             21207                       # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.dtb.walker.walks                    43873                       # Table walker walks requested
system.cpu2.dtb.walker.walksShort               43873                       # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1        13923                       # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2        10993                       # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksSquashedBefore        18957                       # Table walks squashed before starting
system.cpu2.dtb.walker.walkWaitTime::samples        24916                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::mean   571.078825                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::stdev  3693.718026                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0-16383        24688     99.08%     99.08% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::16384-32767          176      0.71%     99.79% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::32768-49151           30      0.12%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::49152-65535            9      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::65536-81919            9      0.04%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::81920-98303            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::98304-114687            1      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::114688-131071            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::131072-147455            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total        24916                       # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples         9164                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 13158.828023                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 10878.635204                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev  7680.126787                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-8191         2739     29.89%     29.89% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::8192-16383         3883     42.37%     72.26% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::16384-24575         2316     25.27%     97.53% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::24576-32767           72      0.79%     98.32% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-40959           91      0.99%     99.31% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::40960-49151           60      0.65%     99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::57344-65535            1      0.01%     99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-73727            1      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::81920-90111            1      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total         9164                       # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples  60380803468                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::mean     0.564289                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::stdev     0.516018                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0-1  60322207968     99.90%     99.90% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::2-3     41747500      0.07%     99.97% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::4-5      8670500      0.01%     99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::6-7      3297500      0.01%     99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::8-9      1514000      0.00%     99.99% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::10-11       972000      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::12-13       454500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::14-15      1161000      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::16-17       173500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::18-19       164000      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::20-21       123500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::22-23        89000      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::24-25       134500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::26-27        15500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::28-29         5500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::30-31        73000      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total  60380803468                       # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K         2766     73.10%     73.10% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::1M         1018     26.90%    100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total         3784                       # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data        43873                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total        43873                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data         3784                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total         3784                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total        47657                       # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
system.cpu2.dtb.read_hits                     9620013                       # DTB read hits
system.cpu2.dtb.read_misses                     37991                       # DTB read misses
system.cpu2.dtb.write_hits                    7129568                       # DTB write hits
system.cpu2.dtb.write_misses                     5882                       # DTB write misses
system.cpu2.dtb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva                     348                       # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries                    2312                       # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults                      478                       # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults                   974                       # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults                      415                       # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses                 9658004                       # DTB read accesses
system.cpu2.dtb.write_accesses                7135450                       # DTB write accesses
system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu2.dtb.hits                         16749581                       # DTB hits
system.cpu2.dtb.misses                          43873                       # DTB misses
system.cpu2.dtb.accesses                     16793454                       # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu2.itb.walker.walks                     5947                       # Table walker walks requested
system.cpu2.itb.walker.walksShort                5947                       # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1         1786                       # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksShortTerminationLevel::Level2         4054                       # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksSquashedBefore          107                       # Table walks squashed before starting
system.cpu2.itb.walker.walkWaitTime::samples         5840                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::mean  1732.534247                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::stdev  7455.028366                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0-8191         5455     93.41%     93.41% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::8192-16383          164      2.81%     96.22% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::16384-24575          114      1.95%     98.17% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::24576-32767           45      0.77%     98.94% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::32768-40959           19      0.33%     99.26% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::40960-49151            8      0.14%     99.40% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::49152-57343           13      0.22%     99.62% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::57344-65535            3      0.05%     99.67% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::65536-73727            6      0.10%     99.78% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::73728-81919            3      0.05%     99.83% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::81920-90111            5      0.09%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::90112-98303            1      0.02%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::98304-106495            2      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::106496-114687            1      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::122880-131071            1      0.02%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total         5840                       # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples         1844                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 13438.177874                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 11167.697103                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev  8164.078124                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-8191          568     30.80%     30.80% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::8192-16383          796     43.17%     73.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::16384-24575          418     22.67%     96.64% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::24576-32767           27      1.46%     98.10% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-40959           12      0.65%     98.75% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::40960-49151           15      0.81%     99.57% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::49152-57343            4      0.22%     99.78% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::57344-65535            3      0.16%     99.95% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-73727            1      0.05%    100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total         1844                       # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples  13135820712                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::mean     0.816052                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::stdev     0.388899                       # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0     2421306500     18.43%     18.43% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::1    10711149212     81.54%     99.97% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::2        2311000      0.02%     99.99% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::3         636500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::4         285000      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::5          97500      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::6          35000      0.00%    100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total  13135820712                       # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K         1342     77.26%     77.26% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::1M          395     22.74%    100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total         1737                       # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst         5947                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total         5947                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst         1737                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total         1737                       # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total         7684                       # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits                    12739134                       # ITB inst hits
system.cpu2.itb.inst_misses                      5947                       # ITB inst misses
system.cpu2.itb.read_hits                           0                       # DTB read hits
system.cpu2.itb.read_misses                         0                       # DTB read misses
system.cpu2.itb.write_hits                          0                       # DTB write hits
system.cpu2.itb.write_misses                        0                       # DTB write misses
system.cpu2.itb.flush_tlb                         179                       # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva                     348                       # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries                    1664                       # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults                     1123                       # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses                       0                       # DTB read accesses
system.cpu2.itb.write_accesses                      0                       # DTB write accesses
system.cpu2.itb.inst_accesses                12745081                       # ITB inst accesses
system.cpu2.itb.hits                         12739134                       # DTB hits
system.cpu2.itb.misses                           5947                       # DTB misses
system.cpu2.itb.accesses                     12745081                       # DTB accesses
system.cpu2.numCycles                        69598203                       # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles          26515709                       # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts                      68908003                       # Number of instructions fetch has processed
system.cpu2.fetch.Branches                   17205761                       # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches          12047751                       # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles                     39848524                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles                2067901                       # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles                     93242                       # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles                1673                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles              258                       # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles       197550                       # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles       103741                       # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles          733                       # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines                 12737635                       # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes               269288                       # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes                   2836                       # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples          67795354                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean             1.222311                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev            2.353518                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0                49366248     72.82%     72.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1                 2347568      3.46%     76.28% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2                 1568593      2.31%     78.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3                 4737747      6.99%     85.58% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4                 1131198      1.67%     87.25% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5                  711180      1.05%     88.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6                 3791892      5.59%     93.89% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7                  790451      1.17%     95.06% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8                 3350477      4.94%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total            67795354                       # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate                 0.247216                       # Number of branch fetches per cycle
system.cpu2.fetch.rate                       0.990083                       # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles                18554298                       # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles             36869392                       # Number of cycles decode is blocked
system.cpu2.decode.RunCycles                 10385190                       # Number of cycles decode is running
system.cpu2.decode.UnblockCycles              1060917                       # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles                925294                       # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved             1315001                       # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred               110273                       # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts              59218991                       # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts               355421                       # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles                925294                       # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles                19165450                       # Number of cycles rename is idle
system.cpu2.rename.BlockCycles                3849841                       # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles      27045066                       # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles                 10823220                       # Number of cycles rename is running
system.cpu2.rename.UnblockCycles              5986178                       # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts              56757014                       # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents                 1753                       # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents                886942                       # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents                164990                       # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents               4446768                       # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands           58681863                       # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups            260617277                       # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups        63638433                       # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups             4180                       # Number of floating rename lookups
system.cpu2.rename.CommittedMaps             48518636                       # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps                10163211                       # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts            951510                       # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts        887874                       # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts                  5959133                       # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads            10269621                       # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores            7907555                       # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads          1397245                       # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores         1927093                       # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded                  54497262                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded             673331                       # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued                 51805193                       # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued            68913                       # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined        8128009                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined     18480591                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved         69367                       # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples     67795354                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean        0.764141                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev       1.469300                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0           47462334     70.01%     70.01% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1            6771907      9.99%     80.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2            5071293      7.48%     87.48% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3            4140398      6.11%     93.58% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4            1621050      2.39%     95.98% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5            1073842      1.58%     97.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6            1127363      1.66%     99.22% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7             365418      0.54%     99.76% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8             161749      0.24%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total       67795354                       # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu                  78874      9.93%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult                     1      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv                      0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult                   0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult                    0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift                   0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      9.93% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead                365128     45.98%     55.91% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite               350163     44.09%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass              104      0.00%      0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu             34340504     66.29%     66.29% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult               39551      0.08%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu                   1      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc                  1      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.36% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc          2876      0.01%     66.37% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     66.37% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     66.37% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.37% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead             9906412     19.12%     85.49% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite            7515741     14.51%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total              51805193                       # Type of FU issued
system.cpu2.iq.rate                          0.744347                       # Inst issue rate
system.cpu2.iq.fu_busy_cnt                     794166                       # FU busy when requested
system.cpu2.iq.fu_busy_rate                  0.015330                       # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads         172259378                       # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes         63331070                       # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses     50263649                       # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads               9441                       # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes              4992                       # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses         4167                       # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses              52594172                       # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses                   5083                       # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads          269403                       # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads      1615728                       # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses         1799                       # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation        38192                       # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores       801002                       # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads       130832                       # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked        65205                       # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles                925294                       # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles                3298023                       # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles               403705                       # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts           55280627                       # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts            94381                       # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts             10269621                       # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts             7907555                       # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts            360066                       # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents                 33263                       # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents               361678                       # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents         38192                       # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect        184473                       # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect       164818                       # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts              349291                       # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts             51367571                       # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts              9727601                       # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts           393852                       # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
system.cpu2.iew.exec_nop                       110034                       # number of nop insts executed
system.cpu2.iew.exec_refs                    17167980                       # number of memory reference insts executed
system.cpu2.iew.exec_branches                 9465672                       # Number of branches executed
system.cpu2.iew.exec_stores                   7440379                       # Number of stores executed
system.cpu2.iew.exec_rate                    0.738059                       # Inst execution rate
system.cpu2.iew.wb_sent                      50970582                       # cumulative count of insts sent to commit
system.cpu2.iew.wb_count                     50267816                       # cumulative count of insts written-back
system.cpu2.iew.wb_producers                 26418019                       # num instructions producing a value
system.cpu2.iew.wb_consumers                 45975704                       # num instructions consuming a value
system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate                      0.722257                       # insts written-back per cycle
system.cpu2.iew.wb_fanout                    0.574608                       # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts        8162826                       # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls         603964                       # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts           292667                       # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples     66072678                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean     0.712969                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev     1.621762                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0     48122515     72.83%     72.83% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1      8016673     12.13%     84.97% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2      3951454      5.98%     90.95% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3      1700222      2.57%     93.52% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4       874557      1.32%     94.84% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5       615125      0.93%     95.77% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6      1261958      1.91%     97.68% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7       299480      0.45%     98.14% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8      1230694      1.86%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total     66072678                       # Number of insts commited each cycle
system.cpu2.commit.committedInsts            38816949                       # Number of instructions committed
system.cpu2.commit.committedOps              47107760                       # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu2.commit.refs                      15760446                       # Number of memory references committed
system.cpu2.commit.loads                      8653893                       # Number of loads committed
system.cpu2.commit.membars                     226862                       # Number of memory barriers committed
system.cpu2.commit.branches                   8887739                       # Number of branches committed
system.cpu2.commit.fp_insts                      4128                       # Number of committed floating point instructions.
system.cpu2.commit.int_insts                 41222164                       # Number of committed integer instructions.
system.cpu2.commit.function_calls             1631970                       # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu        31306209     66.46%     66.46% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult          38229      0.08%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv               0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd             0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp             0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt             0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv             0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd              0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu              0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp              0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt              0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc             0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult             0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt             0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc         2876      0.01%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt            0      0.00%     66.54% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead        8653893     18.37%     84.91% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite       7106553     15.09%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total         47107760                       # Class of committed instruction
system.cpu2.commit.bw_lim_events              1230694                       # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads                   112781874                       # The number of ROB reads
system.cpu2.rob.rob_writes                  112267275                       # The number of ROB writes
system.cpu2.timesIdled                         279594                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles                        1802849                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles                  5249879064                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts                   38751769                       # Number of Instructions Simulated
system.cpu2.committedOps                     47042580                       # Number of Ops (including micro ops) Simulated
system.cpu2.cpi                              1.796001                       # CPI: Cycles Per Instruction
system.cpu2.cpi_total                        1.796001                       # CPI: Total CPI of All Threads
system.cpu2.ipc                              0.556793                       # IPC: Instructions Per Cycle
system.cpu2.ipc_total                        0.556793                       # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads                56233169                       # number of integer regfile reads
system.cpu2.int_regfile_writes               31866388                       # number of integer regfile writes
system.cpu2.fp_regfile_reads                    15654                       # number of floating regfile reads
system.cpu2.fp_regfile_writes                   13819                       # number of floating regfile writes
system.cpu2.cc_regfile_reads                181781148                       # number of cc regfile reads
system.cpu2.cc_regfile_writes                19208893                       # number of cc regfile writes
system.cpu2.misc_regfile_reads               94223470                       # number of misc regfile reads
system.cpu2.misc_regfile_writes                484431                       # number of misc regfile writes
system.iobus.trans_dist::ReadReq                30182                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30182                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59005                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59005                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        54134                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          116                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       105422                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  178374                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        67851                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          232                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       159079                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2480327                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             18337000                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 1000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 8000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer19.occupancy                2000                       # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer20.occupancy                8000                       # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy             2698000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy                1000                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy            15728000                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer26.occupancy               25000                       # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer27.occupancy           107120699                       # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            39854000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy            20948000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements                36442                       # number of replacements
system.iocache.tags.tagsinuse                0.991924                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         244949964009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide     0.991924                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.061995                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.061995                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
system.iocache.tags.data_accesses              328284                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide          252                       # number of overall misses
system.iocache.overall_misses::total              252                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide     14446931                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total     14446931                       # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide   2442151768                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total   2442151768                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide     14446931                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total     14446931                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide     14446931                       # number of overall miss cycles
system.iocache.overall_miss_latency::total     14446931                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 57329.091270                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 57329.091270                       # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 67418.058966                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 67418.058966                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 57329.091270                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 57329.091270                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 57329.091270                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 57329.091270                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide          122                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total          122                       # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide        20704                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total        20704                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide          122                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total          122                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide          122                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total          122                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide      8346931                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total      8346931                       # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   1406951768                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   1406951768                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide      8346931                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total      8346931                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide      8346931                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total      8346931                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide     0.484127                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total     0.484127                       # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide     0.571555                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total     0.571555                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide     0.484127                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total     0.484127                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide     0.484127                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total     0.484127                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68417.467213                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68417.467213                       # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67955.552937                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67955.552937                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68417.467213                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68417.467213                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68417.467213                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68417.467213                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.l2c.tags.replacements                   100800                       # number of replacements
system.l2c.tags.tagsinuse                65125.449839                       # Cycle average of tags in use
system.l2c.tags.total_refs                    4808585                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   165996                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                    28.968078                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   49726.772555                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     1.939327                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000095                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     5415.190350                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     2959.237721                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.969230                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1018.129085                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      815.178543                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker    59.704078                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst     3616.145822                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data     1512.183033                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.758770                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000030                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.082629                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.045154                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.015535                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.012439                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000911                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst       0.055178                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data       0.023074                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.993736                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023           48                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        65148                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4           48                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          322                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2981                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         8244                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53579                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000732                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.994080                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 42763917                       # Number of tag accesses
system.l2c.tags.data_accesses                42763917                       # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker         4590                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker         2386                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker         1717                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker          931                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker        27091                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker         5953                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  42668                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          690633                       # number of Writeback hits
system.l2c.Writeback_hits::total               690633                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data              10                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data              34                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  48                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data            11                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total                11                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            81720                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            20255                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data            55422                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               157397                       # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst        854225                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst        247947                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst        678133                       # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total           1780305                       # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       239843                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        78268                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data       203677                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           521788                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker          4590                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          2386                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              854225                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              321563                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker          1717                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker           931                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              247947                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               98523                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker         27091                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker          5953                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst              678133                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data              259099                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2502158                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker         4590                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         2386                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             854225                       # number of overall hits
system.l2c.overall_hits::cpu0.data             321563                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker         1717                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker          931                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             247947                       # number of overall hits
system.l2c.overall_hits::cpu1.data              98523                       # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker        27091                       # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker         5953                       # number of overall hits
system.l2c.overall_hits::cpu2.inst             678133                       # number of overall hits
system.l2c.overall_hits::cpu2.data             259099                       # number of overall hits
system.l2c.overall_hits::total                2502158                       # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker            4                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker           89                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                   95                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data          1320                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data           342                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data          1053                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2715                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data            3                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data            5                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total               8                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          64209                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          14460                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data          60110                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             138779                       # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst         9651                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst         1946                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst         8147                       # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total           19744                       # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data         7162                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         2480                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data         4481                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          14123                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            4                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst              9651                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data             71371                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              1946                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             16940                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker           89                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst              8147                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data             64591                       # number of demand (read+write) misses
system.l2c.demand_misses::total                172741                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            4                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu0.inst             9651                       # number of overall misses
system.l2c.overall_misses::cpu0.data            71371                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             1946                       # number of overall misses
system.l2c.overall_misses::cpu1.data            16940                       # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker           89                       # number of overall misses
system.l2c.overall_misses::cpu2.inst             8147                       # number of overall misses
system.l2c.overall_misses::cpu2.data            64591                       # number of overall misses
system.l2c.overall_misses::total               172741                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        82500                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      7918000                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total        8000500                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data        92500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data       339500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total       432000                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data       127000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total       127000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   1119587000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data   4880855000                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   6000442000                       # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst    159178000                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst    680250500                       # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total    839428500                       # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data    203493500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data    391802000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total    595295500                       # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker        82500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst    159178000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data   1323080500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker      7918000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst    680250500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data   5272657000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      7443166500                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker        82500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst    159178000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data   1323080500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker      7918000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst    680250500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data   5272657000                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     7443166500                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker         4594                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker         2387                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker         1718                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker          931                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker        27180                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker         5953                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total              42763                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       690633                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           690633                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data         1330                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data          346                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data         1087                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2763                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data            3                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data           16                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       145929                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        34715                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data       115532                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           296176                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst       863876                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst       249893                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst       686280                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total       1800049                       # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       247005                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        80748                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data       208158                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       535911                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker         4594                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         2387                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          863876                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          392934                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker         1718                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker          931                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          249893                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          115463                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker        27180                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker         5953                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst          686280                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data          323690                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             2674899                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker         4594                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         2387                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         863876                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         392934                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker         1718                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker          931                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         249893                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         115463                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker        27180                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker         5953                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst         686280                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data         323690                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            2674899                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000871                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000419                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000582                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.003274                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.002222                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.992481                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.988439                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data     0.968721                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.982628                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.312500                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.421053                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.440002                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.416535                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data     0.520289                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.468569                       # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst     0.011172                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst     0.007787                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst     0.011871                       # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total     0.010969                       # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.028995                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.030713                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data     0.021527                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.026353                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000871                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.000419                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.011172                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.181636                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000582                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.007787                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.146714                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker     0.003274                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst       0.011871                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data       0.199546                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.064579                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000871                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.000419                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.011172                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.181636                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000582                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.007787                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.146714                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker     0.003274                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst      0.011871                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data      0.199546                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.064579                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        82500                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 88966.292135                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 84215.789474                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   270.467836                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   322.412156                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total   159.116022                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data        25400                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total        15875                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77426.486860                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81198.719015                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 43237.391824                       # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81797.533402                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83497.054130                       # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 42515.625000                       # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82053.830645                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 87436.286543                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 42150.782412                       # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81797.533402                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 78103.925620                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 88966.292135                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 83497.054130                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 81631.450202                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 43088.592170                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        82500                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81797.533402                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 78103.925620                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 88966.292135                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 83497.054130                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 81631.450202                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 43088.592170                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               92937                       # number of writebacks
system.l2c.writebacks::total                    92937                       # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data           44                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total           44                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data             44                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                 49                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data            44                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total                49                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           89                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total              90                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data          342                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data         1053                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total         1395                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            5                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total            5                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        14460                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data        60110                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         74570                       # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst         1946                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst         8142                       # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total        10088                       # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data         2480                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data         4437                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total         6917                       # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst         1946                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data        16940                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker           89                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst         8142                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data        64547                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            91665                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst         1946                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data        16940                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker           89                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst         8142                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data        64547                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           91665                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data         5882                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data         8601                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        14483                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data         4590                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data         6802                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        11392                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        10472                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data        15403                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        25875                       # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      7028000                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total      7100500                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7101000                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     21856500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total     28957500                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data       108000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total       108000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    974987000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   4279755000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   5254742000                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst    139718000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst    598575000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total    738293000                       # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data    178693500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data    344725500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total    523419000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst    139718000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data   1153680500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      7028000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst    598575000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data   4624480500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   6523554500                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        72500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst    139718000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data   1153680500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      7028000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst    598575000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data   4624480500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   6523554500                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    983438000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data   1607640500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   2591078500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    758788000                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   1264062500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   2022850500                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1742226000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data   2871703000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4613929000                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000582                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.003274                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.002105                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.988439                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.968721                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.504886                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.312500                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.263158                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.416535                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.520289                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.251776                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.007787                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst     0.011864                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total     0.005604                       # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.030713                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data     0.021316                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.012907                       # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000582                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007787                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.146714                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.003274                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011864                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data     0.199410                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.034269                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000582                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007787                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.146714                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.003274                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011864                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data     0.199410                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.034269                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 78894.444444                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.157895                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20756.410256                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.064516                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        21600                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        21600                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67426.486860                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71198.719015                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70467.238836                       # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71797.533402                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73516.949153                       # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73185.269627                       # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72053.830645                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 77693.373901                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75671.389331                       # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71797.533402                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68103.925620                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73516.949153                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71645.165538                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 71167.343043                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        72500                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71797.533402                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68103.925620                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 78966.292135                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73516.949153                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71645.165538                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 71167.343043                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167194.491670                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186913.207767                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 178904.819443                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165313.289760                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185836.886210                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177567.635183                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166369.938885                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 186437.901707                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 178316.096618                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               40110                       # Transaction distribution
system.membus.trans_dist::ReadResp              74274                       # Transaction distribution
system.membus.trans_dist::WriteReq              27559                       # Transaction distribution
system.membus.trans_dist::WriteResp             27559                       # Transaction distribution
system.membus.trans_dist::Writeback            129127                       # Transaction distribution
system.membus.trans_dist::CleanEvict             7993                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4555                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              8                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4563                       # Transaction distribution
system.membus.trans_dist::ReadExReq            136939                       # Transaction distribution
system.membus.trans_dist::ReadExResp           136939                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         34165                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       105422                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         2000                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       479379                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       586811                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109150                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       109150                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 695961                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       159079                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio         4000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     16928316                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     17091415                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2324480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2324480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                19415895                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                              278                       # Total snoops (count)
system.membus.snoop_fanout::samples            416813                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  416813    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              416813                       # Request fanout histogram
system.membus.reqLayer0.occupancy            45715500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy              475000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy           457691597                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy          520011564                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           36772084                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.toL2Bus.trans_dist::ReadReq             105713                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           2441896                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             27559                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            27559                       # Transaction distribution
system.toL2Bus.trans_dist::Writeback           756453                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1923004                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq            2763                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq            19                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp           2782                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           296176                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          296176                       # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq       1800158                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       536033                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq        20704                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      5399808                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2615033                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28551                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        87799                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               8131191                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side    115239416                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     97644319                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        47800                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       155188                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              213086723                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          121684                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          5505945                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            1.031256                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.174010                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                5333849     96.87%     96.87% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                 172096      3.13%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            5505945                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         1781656500                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy           172500                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        1404823682                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy         679741283                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy          11544481                       # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy          39263676                       # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------