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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

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stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
sim_seconds 2.403594 # Number of seconds simulated
sim_ticks 2403594294500 # Number of ticks simulated
final_tick 2403594294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
host_inst_rate 127977 # Simulator instruction rate (inst/s)
host_op_rate 164357 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5098961801 # Simulator tick rate (ticks/s)
host_mem_usage 401544 # Number of bytes of host memory used
host_seconds 471.39 # Real time elapsed on the host
sim_insts 60327163 # Number of instructions simulated
sim_ops 77476179 # Number of ops (including micro ops) simulated
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_read::cpu0.inst 511136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 7143248 # Number of bytes read from this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 688768 # Number of bytes read from this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_read::cpu2.inst 171584 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1244640 # Number of bytes read from this memory
system.physmem.bytes_read::total 124657616 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 511136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 171584 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 761248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3742592 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1523692 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 157804 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data 1334320 # Number of bytes written to this memory
system.physmem.bytes_written::total 6758408 # Number of bytes written to this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.num_reads::cpu0.inst 14189 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 111647 # Number of read requests responded to by this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10762 # Number of read requests responded to by this memory
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.num_reads::cpu2.inst 2681 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 19455 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14512355 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58478 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 380923 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 39451 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data 333580 # Number of write requests responded to by this memory
system.physmem.num_writes::total 812432 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47769739 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_read::cpu0.inst 212655 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2971903 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_read::cpu1.inst 32671 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 286558 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_read::cpu2.inst 71386 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 517824 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51863002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 212655 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 32671 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 71386 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 316712 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1557081 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 633922 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 65653 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data 555135 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2811792 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1557081 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47769739 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_total::cpu0.inst 212655 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3605825 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_total::cpu1.inst 32671 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 352211 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_total::cpu2.inst 71386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1072960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54674794 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 13478004 # Total number of read requests seen
system.physmem.writeReqs 390132 # Total number of write requests seen
system.physmem.cpureqs 53582 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 862592256 # Total number of bytes read from memory
system.physmem.bytesWritten 24968448 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 109734944 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2586588 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 837777 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 837385 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 837533 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 838713 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 839756 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 839804 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 839650 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 840522 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 841715 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 844141 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 844930 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 846498 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 848135 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 848079 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 846803 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 846563 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 25455 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 25327 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 25409 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 25902 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 26300 # Track writes on a per bank basis
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.perBankWrReqs::6 25421 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 23356 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 23184 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 23261 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 21260 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 21580 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 24628 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 24253 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 23500 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 25208 # Track writes on a per bank basis
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.totGap 2402559124000 # Total gap between requests
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::2 8 # Categorize read packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.readPktSize::3 13443872 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.readPktSize::6 34124 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.writePktSize::2 373031 # Categorize write packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.writePktSize::6 17101 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 870514 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 846629 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 868006 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3320451 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2492641 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2492474 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2466384 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 13873 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 13526 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 25989 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 38321 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 25827 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 858 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 842 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 820 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::0 2518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2533 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2546 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2544 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2543 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2550 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 16973 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 16965 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 16963 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 16956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 16951 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 16946 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 16941 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 16938 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 16929 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 16923 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 16921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 16918 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 16918 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::25 14472 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::27 14453 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.wrQLenPdf::29 14444 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 14430 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 14424 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 22008 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 40328.985823 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 6672.817905 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 32794.691650 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-95 2992 13.60% 13.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-159 1338 6.08% 19.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-223 840 3.82% 23.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-287 568 2.58% 26.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-351 356 1.62% 27.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-415 350 1.59% 29.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-479 274 1.25% 30.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-543 258 1.17% 31.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-607 159 0.72% 32.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-671 152 0.69% 33.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-735 129 0.59% 33.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-799 166 0.75% 34.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-863 85 0.39% 34.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-927 79 0.36% 35.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-991 56 0.25% 35.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1055 66 0.30% 35.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1119 41 0.19% 35.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1183 34 0.15% 36.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1247 24 0.11% 36.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1311 38 0.17% 36.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1375 28 0.13% 36.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1439 94 0.43% 36.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1503 111 0.50% 37.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1567 95 0.43% 37.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1631 19 0.09% 37.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1695 37 0.17% 38.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1759 24 0.11% 38.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1823 40 0.18% 38.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1887 12 0.05% 38.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1951 17 0.08% 38.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2015 8 0.04% 38.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2079 19 0.09% 38.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2143 12 0.05% 38.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2207 11 0.05% 38.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2271 5 0.02% 38.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2335 5 0.02% 38.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2399 3 0.01% 38.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2463 10 0.05% 38.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2527 2 0.01% 38.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2591 1 0.00% 38.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2655 1 0.00% 38.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2719 5 0.02% 38.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2783 5 0.02% 38.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2847 5 0.02% 38.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2911 3 0.01% 38.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2975 1 0.00% 38.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3039 1 0.00% 38.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3103 7 0.03% 39.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3167 2 0.01% 39.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3231 3 0.01% 39.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3295 4 0.02% 39.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3359 7 0.03% 39.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3423 2 0.01% 39.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3487 2 0.01% 39.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3615 3 0.01% 39.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3679 2 0.01% 39.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3743 1 0.00% 39.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3807 2 0.01% 39.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3871 3 0.01% 39.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4063 3 0.01% 39.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4127 7 0.03% 39.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4383 3 0.01% 39.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4447 1 0.00% 39.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4703 1 0.00% 39.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4767 2 0.01% 39.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4831 3 0.01% 39.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4895 1 0.00% 39.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5023 1 0.00% 39.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5215 1 0.00% 39.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5407 2 0.01% 39.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5471 1 0.00% 39.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5919 2 0.01% 39.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6175 8 0.04% 39.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6303 1 0.00% 39.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6431 1 0.00% 39.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6559 1 0.00% 39.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6815 4 0.02% 39.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7071 2 0.01% 39.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7391 2 0.01% 39.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7455 1 0.00% 39.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7711 2 0.01% 39.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7839 1 0.00% 39.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7903 1 0.00% 39.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7967 2 0.01% 39.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8095 1 0.00% 39.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8223 3 0.01% 39.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8479 1 0.00% 39.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8576-8607 1 0.00% 39.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8735 1 0.00% 39.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12319 3 0.01% 39.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13343 1 0.00% 39.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13983 1 0.00% 39.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14623 1 0.00% 39.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19231 1 0.00% 39.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19487 1 0.00% 39.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19999 1 0.00% 39.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21791 1 0.00% 39.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22559 2 0.01% 39.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23327 1 0.00% 39.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23583 1 0.00% 39.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28191 1 0.00% 39.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30751 1 0.00% 39.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32031 2 0.01% 39.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33055 2 0.01% 39.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33311 2 0.01% 39.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33567 2 0.01% 39.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33823 1 0.00% 39.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34847 1 0.00% 39.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35871 1 0.00% 39.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36895 1 0.00% 39.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37919 1 0.00% 39.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38943 1 0.00% 39.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40991 1 0.00% 39.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-42015 1 0.00% 39.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42783 1 0.00% 39.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46111 1 0.00% 39.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49408-49439 1 0.00% 39.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50944-50975 1 0.00% 39.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::53248-53279 1 0.00% 39.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54272-54303 1 0.00% 39.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::54464-54495 1 0.00% 39.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56576-56607 1 0.00% 39.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58240-58271 1 0.00% 39.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::58624-58655 1 0.00% 39.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59392-59423 1 0.00% 39.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65567 13106 59.55% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131103 181 0.82% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 22008 # Bytes accessed per row activation
system.physmem.totQLat 259991264250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 339839911750 # Sum of mem lat for all requests
system.physmem.totBusLat 67390020000 # Total cycles spent in databus access
system.physmem.totBankLat 12458627500 # Total cycles spent in bank access
system.physmem.avgQLat 19290.04 # Average queueing delay per request
system.physmem.avgBankLat 924.37 # Average bank access latency per request
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgMemAccLat 25214.41 # Average memory access latency
system.physmem.avgRdBW 358.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 45.65 # Average consumed read bandwidth in MB/s
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.busUtil 2.88 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.14 # Average read queue length over time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgWrQLen 0.40 # Average write queue length over time
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.readRowHits 13460829 # Number of row buffer hits during reads
system.physmem.writeRowHits 385299 # Number of row buffer hits during writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgGap 173243.12 # Average gap between requests
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.throughput 55672102 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 13817032 # Transaction distribution
system.membus.trans_dist::ReadResp 13817032 # Transaction distribution
system.membus.trans_dist::WriteReq 375870 # Transaction distribution
system.membus.trans_dist::WriteResp 375870 # Transaction distribution
system.membus.trans_dist::Writeback 17101 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2357 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2357 # Transaction distribution
system.membus.trans_dist::ReadExReq 26474 # Transaction distribution
system.membus.trans_dist::ReadExResp 26474 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736448 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836141 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1572823 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887744 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 26887744 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 736448 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 27723885 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 28460567 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4770556 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 5511420 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550976 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 107550976 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 112321532 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 113062396 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 133813146 # Total data (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer0.occupancy 415491000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer2.occupancy 14469192250 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer2.utilization 0.6 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer3.occupancy 218000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.respLayer1.occupancy 1494318294 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.respLayer2.occupancy 30346616000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.l2c.tags.replacements 63199 # number of replacements
system.l2c.tags.tagsinuse 50350.442050 # Cycle average of tags in use
system.l2c.tags.total_refs 1748255 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 128595 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.595046 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2375554811500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36868.064409 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5218.650868 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3758.862884 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 721.252750 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 766.461515 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 4.929404 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1435.478788 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 1575.747972 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.562562 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.079630 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.011005 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.011695 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.021904 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.024044 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.768287 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3220 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 462102 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 166367 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 2587 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1159 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 134524 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 65754 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 18045 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 4210 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 282039 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 141097 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1290004 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 597664 # number of Writeback hits
system.l2c.Writeback_hits::total 597664 # number of Writeback hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 60793 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 19412 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 33407 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113612 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3220 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 462102 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 227160 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 2587 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1159 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 134524 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 85166 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 18045 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 4210 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 282039 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 174504 # number of demand (read+write) hits
system.l2c.demand_hits::total 1403616 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 8900 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3220 # number of overall hits
system.l2c.overall_hits::cpu0.inst 462102 # number of overall hits
system.l2c.overall_hits::cpu0.data 227160 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 2587 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1159 # number of overall hits
system.l2c.overall_hits::cpu1.inst 134524 # number of overall hits
system.l2c.overall_hits::cpu1.data 85166 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 18045 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 4210 # number of overall hits
system.l2c.overall_hits::cpu2.inst 282039 # number of overall hits
system.l2c.overall_hits::cpu2.data 174504 # number of overall hits
system.l2c.overall_hits::total 1403616 # number of overall hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_misses::cpu0.inst 7573 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6382 # number of ReadReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_misses::cpu1.inst 1227 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1212 # number of ReadReq misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_misses::cpu2.dtb.walker 6 # number of ReadReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_misses::cpu2.inst 2682 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 2534 # number of ReadReq misses
system.l2c.ReadReq_misses::total 21620 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1417 # number of UpgradeReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_misses::cpu1.data 474 # number of UpgradeReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_misses::cpu2.data 1011 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2902 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 106027 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 9825 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 17521 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133373 # number of ReadExReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_misses::cpu0.inst 7573 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 112409 # number of demand (read+write) misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_misses::cpu1.inst 1227 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 11037 # number of demand (read+write) misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_misses::cpu2.dtb.walker 6 # number of demand (read+write) misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_misses::cpu2.inst 2682 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 20055 # number of demand (read+write) misses
system.l2c.demand_misses::total 154993 # number of demand (read+write) misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_misses::cpu0.inst 7573 # number of overall misses
system.l2c.overall_misses::cpu0.data 112409 # number of overall misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_misses::cpu1.inst 1227 # number of overall misses
system.l2c.overall_misses::cpu1.data 11037 # number of overall misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_misses::cpu2.dtb.walker 6 # number of overall misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_misses::cpu2.inst 2682 # number of overall misses
system.l2c.overall_misses::cpu2.data 20055 # number of overall misses
system.l2c.overall_misses::total 154993 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 88750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 89183000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 89694250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 534000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 214633000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 192644000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 586777000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 93496 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 187492 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 627602225 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1227849653 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1855451878 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 88750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 89183000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 717296475 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 534000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 214633000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 1420493653 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2442228878 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 88750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 89183000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 717296475 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 534000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 214633000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 1420493653 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2442228878 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 8901 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3222 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 469675 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 172749 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 2588 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1159 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 135751 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 66966 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 18051 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 4210 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 284721 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 143631 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1311624 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 597664 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 597664 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1431 # number of UpgradeReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_accesses::cpu1.data 478 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_accesses::cpu2.data 1026 # number of UpgradeReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_accesses::total 2935 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadExReq_accesses::cpu0.data 166820 # number of ReadExReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_accesses::cpu1.data 29237 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 50928 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246985 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 8901 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3222 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 469675 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 339569 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 2588 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1159 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 135751 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 96203 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 18051 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 4210 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 284721 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 194559 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1558609 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 8901 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3222 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 469675 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 339569 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 2588 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1159 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 135751 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 96203 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 18051 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 4210 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 284721 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 194559 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1558609 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000621 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.016124 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.036944 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000386 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.009039 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.018099 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.009420 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.017642 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016483 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990217 # miss rate for UpgradeReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991632 # miss rate for UpgradeReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.985380 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.988756 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.635577 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.336047 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.344035 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.540004 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000621 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.016124 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.331034 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000386 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.009039 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.114726 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.009420 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.103079 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.099443 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000621 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.016124 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.331034 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000386 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.009039 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.114726 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000332 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.009420 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.103079 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.099443 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72683.781581 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74005.156766 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 80027.218494 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 76023.677979 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 27140.471785 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 198.303797 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 92.478734 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 64.607857 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63878.089059 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 70078.742823 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 13911.750339 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72683.781581 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 64990.167165 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 80027.218494 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 70829.900424 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 15757.026950 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88750 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72683.781581 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 64990.167165 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 80027.218494 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 70829.900424 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 15757.026950 # average overall miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.writebacks::writebacks 58478 # number of writebacks
system.l2c.writebacks::total 58478 # number of writebacks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_hits::cpu2.data 11 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_hits::cpu2.data 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_hits::cpu2.data 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 1227 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1212 # number of ReadReq MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 6 # number of ReadReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_misses::cpu2.inst 2681 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 2523 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 7650 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_mshr_misses::cpu1.data 474 # number of UpgradeReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_mshr_misses::cpu2.data 1011 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 1485 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 9825 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 17521 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 27346 # number of ReadExReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 1227 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 11037 # number of demand (read+write) MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.demand_mshr_misses::cpu2.dtb.walker 6 # number of demand (read+write) MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_misses::cpu2.inst 2681 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 20044 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 34996 # number of demand (read+write) MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 1227 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 11037 # number of overall MSHR misses
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.l2c.overall_mshr_misses::cpu2.dtb.walker 6 # number of overall MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_misses::cpu2.inst 2681 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 20044 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 34996 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 73683000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 74301250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 457500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 180621750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 160030500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 489170250 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4740974 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10111011 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 14851985 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 504138275 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1005417847 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1509556122 # number of ReadExReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_miss_latency::cpu1.inst 73683000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 578439525 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 457500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 180621750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 1165448347 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 1998726372 # number of demand (read+write) MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_miss_latency::cpu1.inst 73683000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 578439525 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 457500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 180621750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 1165448347 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 1998726372 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25110922000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26464964500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 51575886500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 934919099 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9811837250 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 10746756349 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26045841099 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36276801750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 62322642849 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018099 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017566 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.005832 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991632 # mshr miss rate for UpgradeReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985380 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.505963 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.336047 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344035 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.110719 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.114726 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.103023 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.022453 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.114726 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.103023 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.022453 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61304.661716 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63428.656361 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 63943.823529 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.054852 # average UpgradeReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.336700 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51311.783715 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 57383.588094 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 55202.081548 # average ReadExReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52409.126121 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 58144.499451 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57112.994971 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52409.126121 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58144.499451 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57112.994971 # average overall mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.throughput 58801079 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 1037457 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 1037456 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 375870 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 375870 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 275194 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1507 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 80165 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 80165 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 841603 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2342492 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15419 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50807 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count 3250321 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26910144 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38454204 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21476 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 82556 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size 65468380 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 141234858 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 99080 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2173969472 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer0.occupancy 1896208409 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer1.occupancy 1871332229 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer2.occupancy 10065963 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.toL2Bus.respLayer3.occupancy 30326428 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.throughput 48764132 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 13809327 # Transaction distribution
system.iobus.trans_dist::ReadResp 13809327 # Transaction distribution
system.iobus.trans_dist::WriteReq 2769 # Transaction distribution
system.iobus.trans_dist::WriteResp 2769 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count_system.bridge.master::total 736448 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 26887744 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 27624192 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 740396 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550976 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 108291372 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 117209190 # Total data (bytes)
system.iobus.reqLayer0.occupancy 7942000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.reqLayer1.occupancy 1545000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.reqLayer7.occupancy 361211000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.reqLayer25.occupancy 13443872000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 733679000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.respLayer1.occupancy 36855511000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.read_hits 8066197 # DTB read hits
system.cpu0.dtb.read_misses 6232 # DTB read misses
system.cpu0.dtb.write_hits 6664992 # DTB write hits
system.cpu0.dtb.write_misses 2050 # DTB write misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.flush_entries 5697 # Number of entries that have been flushed from TLB
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.read_accesses 8072429 # DTB read accesses
system.cpu0.dtb.write_accesses 6667042 # DTB write accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dtb.hits 14731189 # DTB hits
system.cpu0.dtb.misses 8282 # DTB misses
system.cpu0.dtb.accesses 14739471 # DTB accesses
system.cpu0.itb.inst_hits 32886560 # ITB inst hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.inst_misses 3493 # ITB inst misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.itb.flush_entries 2599 # Number of entries that have been flushed from TLB
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.itb.inst_accesses 32890053 # ITB inst accesses
system.cpu0.itb.hits 32886560 # DTB hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.itb.misses 3493 # DTB misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.itb.accesses 32890053 # DTB accesses
system.cpu0.numCycles 114224752 # number of cpu cycles simulated
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.committedInsts 32403519 # Number of instructions committed
system.cpu0.committedOps 42610516 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 37756553 # Number of integer alu accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.num_func_calls 1186218 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4240514 # number of instructions that are conditional controls
system.cpu0.num_int_insts 37756553 # number of integer instructions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.num_fp_insts 5021 # number of float instructions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.num_int_register_reads 192274568 # number of times the integer registers were read
system.cpu0.num_int_register_writes 39869839 # number of times the integer registers were written
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.num_mem_refs 15395098 # number of memory refs
system.cpu0.num_load_insts 8432454 # Number of load instructions
system.cpu0.num_store_insts 6962644 # Number of store instructions
system.cpu0.num_idle_cycles 13455441823.416426 # Number of idle cycles
system.cpu0.num_busy_cycles -13341217071.416426 # Number of busy cycles
system.cpu0.not_idle_fraction -116.797952 # Percentage of non-idle cycles
system.cpu0.idle_fraction 117.797952 # Percentage of idle cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.icache.tags.replacements 891011 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.603846 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 44299550 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 891523 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 49.689744 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 482.268023 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 22.017936 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 7.317887 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.941930 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.043004 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.014293 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 32418840 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 8204019 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3676691 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 44299550 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 32418840 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 8204019 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3676691 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 44299550 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 32418840 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 8204019 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3676691 # number of overall hits
system.cpu0.icache.overall_hits::total 44299550 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 470403 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 136004 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 309613 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 916020 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 470403 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 136004 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 309613 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 916020 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 470403 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 136004 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 309613 # number of overall misses
system.cpu0.icache.overall_misses::total 916020 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1849388500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4165072081 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6014460581 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1849388500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4165072081 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6014460581 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1849388500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4165072081 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6014460581 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32889243 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8340023 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3986304 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 45215570 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32889243 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 8340023 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3986304 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 45215570 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32889243 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 8340023 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3986304 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 45215570 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014303 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016307 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.077669 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.020259 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014303 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016307 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.077669 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.020259 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014303 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016307 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.077669 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.020259 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.044910 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13452.510331 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6565.861642 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13598.044910 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13452.510331 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6565.861642 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13598.044910 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13452.510331 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6565.861642 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4560 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.icache.blocked::no_mshrs 244 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.688525 # average number of cycles each access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24485 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 24485 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 24485 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 24485 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 24485 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 24485 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136004 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285128 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 421132 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 136004 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 285128 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 421132 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 136004 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 285128 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 421132 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1576777500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3389021328 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4965798828 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1576777500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3389021328 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4965798828 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1576777500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3389021328 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4965798828 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016307 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.071527 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009314 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016307 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.071527 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009314 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016307 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.071527 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009314 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11791.549509 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11791.549509 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11593.611217 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11885.964647 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11791.549509 # average overall mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.tags.replacements 629819 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 23234096 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 630331 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 36.860151 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.812833 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 10.396627 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.787658 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966431 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.020306 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013257 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 6949237 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1880036 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4481409 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13310682 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5977872 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1354370 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2102552 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9434794 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131076 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34176 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73005 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 238257 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137394 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35968 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74026 # number of StoreCondReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.StoreCondReq_hits::total 247388 # number of StoreCondReq hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.demand_hits::cpu0.data 12927109 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 3234406 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6583961 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 22745476 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12927109 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 3234406 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6583961 # number of overall hits
system.cpu0.dcache.overall_hits::total 22745476 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 166432 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 65173 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 288335 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 519940 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 168251 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 29715 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 583568 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 781534 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6317 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1793 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3873 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11983 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 334683 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 94888 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 871903 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1301474 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 334683 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 94888 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 871903 # number of overall misses
system.cpu0.dcache.overall_misses::total 1301474 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 929748000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4191596038 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 5121344038 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 926575749 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 20791104854 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 21717680603 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 23532750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 51118749 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 74651499 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 1856323749 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 24982700892 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 26839024641 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 1856323749 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 24982700892 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 26839024641 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7115669 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1945209 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4769744 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13830622 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6146123 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1384085 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2686120 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10216328 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137393 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35969 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76878 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 250240 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137394 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35968 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74029 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247391 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13261792 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 3329294 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7455864 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24046950 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13261792 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 3329294 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7455864 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24046950 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023390 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033504 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.060451 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.037593 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027375 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021469 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217253 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.076499 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045978 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049848 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050379 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047886 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000041 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025237 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028501 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116942 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.054122 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025237 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028501 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116942 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.054122 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14265.846286 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14537.243269 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9849.875059 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31182.088137 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35627.561576 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 27788.529486 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13124.790853 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13198.747483 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6229.783777 # average LoadLockedReq miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19563.314107 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28653.073670 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 20622.021370 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19563.314107 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 28653.073670 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 20622.021370 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 9525 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 3241 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 1204 # number of cycles access was blocked
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.911130 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 66.142857 # average number of cycles each access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.writebacks::writebacks 597664 # number of writebacks
system.cpu0.dcache.writebacks::total 597664 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 148092 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 148092 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 531664 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 531664 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 435 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 435 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 679756 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 679756 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 679756 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 679756 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65173 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 140243 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 205416 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29715 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 51904 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 81619 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1793 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3438 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5231 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 94888 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 192147 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 287035 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 94888 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 192147 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 287035 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 798815000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1812392117 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2611207117 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 862528251 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1666606492 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2529134743 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19945250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39526251 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59471501 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1661343251 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3478998609 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 5140341860 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1661343251 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478998609 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 5140341860 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27433716000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893863250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56327579250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1437767401 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930226833 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15367994234 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28871483401 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42824090083 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71695573484 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033504 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029403 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014852 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021469 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019323 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007989 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049848 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044720 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020904 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011936 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011936 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12256.839489 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12923.226949 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12711.800040 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29026.695305 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32109.403745 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30987.083191 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11123.954267 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.873473 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11369.050086 # average LoadLockedReq mshr miss latency
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.read_hits 2159851 # DTB read hits
system.cpu1.dtb.read_misses 2083 # DTB read misses
system.cpu1.dtb.write_hits 1460405 # DTB write hits
system.cpu1.dtb.write_misses 373 # DTB write misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.flush_entries 1742 # Number of entries that have been flushed from TLB
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.prefetch_faults 44 # Number of TLB faults due to prefetch
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.read_accesses 2161934 # DTB read accesses
system.cpu1.dtb.write_accesses 1460778 # DTB write accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.dtb.hits 3620256 # DTB hits
system.cpu1.dtb.misses 2456 # DTB misses
system.cpu1.dtb.accesses 3622712 # DTB accesses
system.cpu1.itb.inst_hits 8340023 # ITB inst hits
system.cpu1.itb.inst_misses 1172 # ITB inst misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.itb.inst_accesses 8341195 # ITB inst accesses
system.cpu1.itb.hits 8340023 # DTB hits
system.cpu1.itb.misses 1172 # DTB misses
system.cpu1.itb.accesses 8341195 # DTB accesses
system.cpu1.numCycles 580203695 # number of cpu cycles simulated
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.committedInsts 8134078 # Number of instructions committed
system.cpu1.committedOps 10379103 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 9286356 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 2127 # Number of float alu accesses
system.cpu1.num_func_calls 319009 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1149936 # number of instructions that are conditional controls
system.cpu1.num_int_insts 9286356 # number of integer instructions
system.cpu1.num_fp_insts 2127 # number of float instructions
system.cpu1.num_int_register_reads 53580768 # number of times the integer registers were read
system.cpu1.num_int_register_writes 10053974 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1614 # number of times the floating registers were read
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu1.num_mem_refs 3795930 # number of memory refs
system.cpu1.num_load_insts 2256544 # Number of load instructions
system.cpu1.num_store_insts 1539386 # Number of store instructions
system.cpu1.num_idle_cycles 585938491.751716 # Number of idle cycles
system.cpu1.num_busy_cycles -5734796.751716 # Number of busy cycles
system.cpu1.not_idle_fraction -0.009884 # Percentage of non-idle cycles
system.cpu1.idle_fraction 1.009884 # Percentage of idle cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.branchPred.lookups 4707573 # Number of BP lookups
system.cpu2.branchPred.condPredicted 3829869 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 221083 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 3125328 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 2519731 # Number of BTB hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.branchPred.BTBHitPct 80.622930 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 410392 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 21556 # Number of incorrect RAS predictions.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.dtb.read_hits 10881991 # DTB read hits
system.cpu2.dtb.read_misses 22472 # DTB read misses
system.cpu2.dtb.write_hits 3235005 # DTB write hits
system.cpu2.dtb.write_misses 5987 # DTB write misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.dtb.flush_entries 2290 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 674 # Number of TLB faults due to alignment restrictions
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.dtb.perms_faults 480 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 10904463 # DTB read accesses
system.cpu2.dtb.write_accesses 3240992 # DTB write accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.dtb.hits 14116996 # DTB hits
system.cpu2.dtb.misses 28459 # DTB misses
system.cpu2.dtb.accesses 14145455 # DTB accesses
system.cpu2.itb.inst_hits 3987789 # ITB inst hits
system.cpu2.itb.inst_misses 4600 # ITB inst misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.itb.flush_entries 1704 # Number of entries that have been flushed from TLB
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.itb.perms_faults 1012 # Number of TLB faults due to permissions restrictions
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.itb.inst_accesses 3992389 # ITB inst accesses
system.cpu2.itb.hits 3987789 # DTB hits
system.cpu2.itb.misses 4600 # DTB misses
system.cpu2.itb.accesses 3992389 # DTB accesses
system.cpu2.numCycles 88356031 # number of cpu cycles simulated
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.fetch.icacheStallCycles 9299223 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 32583630 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 4707573 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 2930123 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 6845670 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 1836223 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 50265 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles 18768642 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 865 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 32747 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 722165 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3986309 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 272069 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 2032 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 36980430 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.055775 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.444098 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.fetch.rateDist::0 30139736 81.50% 81.50% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 382786 1.04% 82.54% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 509834 1.38% 83.92% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 817196 2.21% 86.13% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 649833 1.76% 87.88% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 340544 0.92% 88.80% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1001875 2.71% 91.51% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 233328 0.63% 92.14% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 2905298 7.86% 100.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.fetch.rateDist::total 36980430 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.053280 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.368777 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 9914058 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 19374148 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 6194025 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 289491 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 1207748 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 608647 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 53413 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36680754 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 180211 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 1207748 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 10448619 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 6814881 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 11054882 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 5930497 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1522855 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 34729839 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 374808 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 885539 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 37310430 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 158812282 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 158784890 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 27392 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 25602072 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 11708357 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 230914 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 207478 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3294482 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6519802 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3791560 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 528920 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 689934 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 31598942 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 510602 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 34143520 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 55455 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 7440971 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 19631999 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 154198 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 36980430 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.923286 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.579350 # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.issued_per_cycle::0 24453619 66.13% 66.13% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3907365 10.57% 76.69% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 2316831 6.27% 82.96% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 2013006 5.44% 88.40% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 2745101 7.42% 95.82% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 885827 2.40% 98.22% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 492123 1.33% 99.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 131266 0.35% 99.90% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 35292 0.10% 100.00% # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.issued_per_cycle::total 36980430 # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.fu_full::IntAlu 18547 1.21% 1.21% # attempts to use FU when none available
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available
stats: Update stats for O3 switching fix.
2013-04-22 19:20:33 +02:00
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.fu_full::MemRead 1407485 91.52% 92.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 111832 7.27% 100.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.FU_type_0::No_OpClass 61314 0.18% 0.18% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 19310512 56.56% 56.74% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 26216 0.08% 56.81% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 56.81% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 56.81% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.81% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 56.81% # Type of FU issued
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.FU_type_0::MemRead 11345203 33.23% 90.04% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3399891 9.96% 100.00% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iq.FU_type_0::total 34143520 # Type of FU issued
system.cpu2.iq.rate 0.386431 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 1537865 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.045041 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 106882112 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 39555566 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 27370238 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 7010 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 3779 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3144 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 35616337 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 3734 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 206224 # Number of loads that had data forwarded from stores
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iew.lsq.thread0.squashedLoads 1563789 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 2001 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 9138 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 567371 # Number of stores squashed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iew.lsq.thread0.rescheduledLoads 5351721 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 380538 # Number of times an access to memory failed due to the cache being blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iew.iewSquashCycles 1207748 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 5118466 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 92736 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 32192718 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 58170 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6519802 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3791560 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 368228 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 31927 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2425 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 9138 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 105201 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 88411 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 193612 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 33245955 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 11093572 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 897565 # Number of squashed instructions skipped in execute
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iew.exec_nop 83174 # number of nop insts executed
system.cpu2.iew.exec_refs 14459722 # number of memory reference insts executed
system.cpu2.iew.exec_branches 3671566 # Number of branches executed
system.cpu2.iew.exec_stores 3366150 # Number of stores executed
system.cpu2.iew.exec_rate 0.376273 # Inst execution rate
system.cpu2.iew.wb_sent 32817620 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 27373382 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 15610718 # num instructions producing a value
system.cpu2.iew.wb_consumers 28284338 # num instructions consuming a value
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.iew.wb_rate 0.309808 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.551921 # average fanout of values written-back
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.commit.commitSquashedInsts 7382656 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 356404 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 168463 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 35772498 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.686059 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.714745 # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.commit.committed_per_cycle::0 27202420 76.04% 76.04% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4136400 11.56% 87.61% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1256838 3.51% 91.12% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 645513 1.80% 92.92% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 564789 1.58% 94.50% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 319868 0.89% 95.40% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 386889 1.08% 96.48% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 302652 0.85% 97.32% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 957129 2.68% 100.00% # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.commit.committed_per_cycle::total 35772498 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 19845047 # Number of instructions committed
system.cpu2.commit.committedOps 24542041 # Number of ops (including micro ops) committed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.commit.refs 8180202 # Number of memory references committed
system.cpu2.commit.loads 4956013 # Number of loads committed
system.cpu2.commit.membars 94398 # Number of memory barriers committed
system.cpu2.commit.branches 3153060 # Number of branches committed
system.cpu2.commit.fp_insts 3107 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 21774748 # Number of committed integer instructions.
system.cpu2.commit.function_calls 294560 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 957129 # number cycles where commit BW limit reached
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu2.rob.rob_reads 66215885 # The number of ROB reads
system.cpu2.rob.rob_writes 65102408 # The number of ROB writes
system.cpu2.timesIdled 362250 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 51375601 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 3556629546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 19789566 # Number of Instructions Simulated
system.cpu2.committedOps 24486560 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 19789566 # Number of Instructions Simulated
system.cpu2.cpi 4.464779 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 4.464779 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.223975 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.223975 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 153595531 # number of integer regfile reads
system.cpu2.int_regfile_writes 29235365 # number of integer regfile writes
system.cpu2.fp_regfile_reads 22348 # number of floating regfile reads
system.cpu2.fp_regfile_writes 20810 # number of floating regfile writes
system.cpu2.misc_regfile_reads 8997423 # number of misc regfile reads
system.cpu2.misc_regfile_writes 241258 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1279969503000 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1279969503000 # number of overall MSHR uncacheable cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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