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gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
sim_seconds 0.231519 # Number of seconds simulated
sim_ticks 231518815500 # Number of ticks simulated
final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
host_inst_rate 137569 # Simulator instruction rate (inst/s)
host_op_rate 149036 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 63039200 # Simulator tick rate (ticks/s)
host_mem_usage 324016 # Number of bytes of host memory used
host_seconds 3672.62 # Real time elapsed on the host
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
sim_insts 505237723 # Number of instructions simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_ops 547350944 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory
system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory
system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory
system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory
system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 448618 # Number of read requests accepted
system.physmem.writeReqs 303849 # Number of write requests accepted
system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue
system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 28534 # Per bank write bursts
system.physmem.perBankRdBursts::1 27313 # Per bank write bursts
system.physmem.perBankRdBursts::2 27956 # Per bank write bursts
system.physmem.perBankRdBursts::3 26702 # Per bank write bursts
system.physmem.perBankRdBursts::4 30075 # Per bank write bursts
system.physmem.perBankRdBursts::5 29207 # Per bank write bursts
system.physmem.perBankRdBursts::6 27700 # Per bank write bursts
system.physmem.perBankRdBursts::7 26438 # Per bank write bursts
system.physmem.perBankRdBursts::8 28442 # Per bank write bursts
system.physmem.perBankRdBursts::9 26796 # Per bank write bursts
system.physmem.perBankRdBursts::10 28037 # Per bank write bursts
system.physmem.perBankRdBursts::11 28667 # Per bank write bursts
system.physmem.perBankRdBursts::12 28663 # Per bank write bursts
system.physmem.perBankRdBursts::13 27984 # Per bank write bursts
system.physmem.perBankRdBursts::14 26659 # Per bank write bursts
system.physmem.perBankRdBursts::15 27067 # Per bank write bursts
system.physmem.perBankWrBursts::0 19504 # Per bank write bursts
system.physmem.perBankWrBursts::1 19011 # Per bank write bursts
system.physmem.perBankWrBursts::2 18881 # Per bank write bursts
system.physmem.perBankWrBursts::3 18629 # Per bank write bursts
system.physmem.perBankWrBursts::4 19556 # Per bank write bursts
system.physmem.perBankWrBursts::5 19014 # Per bank write bursts
system.physmem.perBankWrBursts::6 18738 # Per bank write bursts
system.physmem.perBankWrBursts::7 18227 # Per bank write bursts
system.physmem.perBankWrBursts::8 18808 # Per bank write bursts
system.physmem.perBankWrBursts::9 18381 # Per bank write bursts
system.physmem.perBankWrBursts::10 19036 # Per bank write bursts
system.physmem.perBankWrBursts::11 19525 # Per bank write bursts
system.physmem.perBankWrBursts::12 19578 # Per bank write bursts
system.physmem.perBankWrBursts::13 19080 # Per bank write bursts
system.physmem.perBankWrBursts::14 18969 # Per bank write bursts
system.physmem.perBankWrBursts::15 18884 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.totGap 231518762500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.readPktSize::6 448618 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.writePktSize::6 303849 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads
system.physmem.totQLat 10651839911 # Total ticks spent queuing
system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers
system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.busUtil 1.62 # Data bus utilization in percentage
system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing
system.physmem.readRowHits 331076 # Number of row buffer hits during reads
system.physmem.writeRowHits 99609 # Number of row buffer hits during writes
system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes
system.physmem.avgGap 307679.62 # Average gap between requests
system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states
system.physmem.memoryStateTime::REF 7730840000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Add DRAM power statistics to reference output
2014-10-09 23:52:13 +02:00
system.physmem.actEnergy::0 1204270200 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 1209705840 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 657091875 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 660057750 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 1746123600 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 1733674800 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 981894960 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 986450400 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 15121523040 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 15121523040 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 75885673770 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 75815795475 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 72343590000 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 72404886750 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 167940167445 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 167932094055 # Total energy per rank (pJ)
system.physmem.averagePower::0 725.391418 # Core power per rank (mW)
system.physmem.averagePower::1 725.356546 # Core power per rank (mW)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.trans_dist::ReadReq 445006 # Transaction distribution
system.membus.trans_dist::ReadResp 445005 # Transaction distribution
system.membus.trans_dist::Writeback 303849 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4 # Transaction distribution
system.membus.trans_dist::ReadExReq 3612 # Transaction distribution
system.membus.trans_dist::ReadExResp 3612 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 752471 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 752471 # Request fanout histogram
system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.branchPred.lookups 175071152 # Number of BP lookups
system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups
system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits
stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3 This patch bumps the stats for 20.parser for ARM o3-timing to reflect a namechange of the branch predictor.
2013-01-28 13:44:26 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions.
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.numCycles 463037632 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed
system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.fetch.SquashCycles 14941835 # Number of cycles fetch has spent squashing
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued
system.cpu.iq.rate 1.317880 # Inst issue rate
system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.exec_nop 1486621 # number of nop insts executed
system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed
system.cpu.iew.exec_branches 131372634 # Number of branches executed
system.cpu.iew.exec_stores 60949141 # Number of stores executed
system.cpu.iew.exec_rate 1.294450 # Inst execution rate
system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back
system.cpu.iew.wb_producers 349881958 # num instructions producing a value
system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 172745233 # Number of memory references committed
system.cpu.commit.loads 115884756 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 1488542 # Number of memory barriers committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.branches 121548301 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.rob.rob_reads 1090469902 # The number of ROB reads
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.rob.rob_writes 1334452492 # The number of ROB writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads
system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.cpu.int_regfile_reads 611059162 # number of integer regfile reads
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.int_regfile_writes 328109228 # number of integer regfile writes
Stats: Re update stats.
2011-02-08 04:23:13 +01:00
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads
system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes
system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 453214 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
system.cpu.icache.tags.replacements 73538 # number of replacements
system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses
system.cpu.icache.tags.data_accesses 473451718 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits
system.cpu.icache.overall_hits::total 236609871 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses
system.cpu.icache.overall_misses::total 78950 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 236688821 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 236688821 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 236688821 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 236688821 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 236688821 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000334 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000334 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000334 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000334 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000334 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11031.212983 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 11031.212983 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 11031.212983 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 11031.212983 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 56449 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 14 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 5209 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 10.836821 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 14 # average number of cycles each access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4873 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 4873 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 4873 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 4873 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 4873 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74077 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 74077 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 74077 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 74077 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 74077 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 74077 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 689302633 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 689302633 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 689302633 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 689302633 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 689302633 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 689302633 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9305.217989 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9305.217989 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 9798854 # number of hwpf identified
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 305321 # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9106282 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 15837 # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6052 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 365354 # number of hwpf issued
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 921882 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.tags.replacements 438181 # number of replacements
system.cpu.l2cache.tags.tagsinuse 15477.013957 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4572801 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 454520 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.060726 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 34588215000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8046.531064 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.372204 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 4345.243734 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3000.866954 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.491121 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005150 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.265213 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183158 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.944642 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 4229 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 12110 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 106 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2013 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1770 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8654 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1689 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.258118 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.739136 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 84920061 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 84920061 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 70946 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 2166314 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2237260 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2348838 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2348838 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 516602 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 516602 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 70946 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2682916 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2753862 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 70946 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2682916 # number of overall hits
system.cpu.l2cache.overall_hits::total 2753862 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3100 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 135521 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 138621 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 5139 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 5139 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3100 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 140660 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 143760 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3100 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 140660 # number of overall misses
system.cpu.l2cache.overall_misses::total 143760 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 221563221 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9589796237 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 9811359458 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14999 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 14999 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 412963248 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 412963248 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 221563221 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10002759485 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10224322706 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 221563221 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10002759485 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10224322706 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 74046 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 2301835 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2375881 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2348838 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2348838 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 26 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 26 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 521741 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 521741 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 74046 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2823576 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2897622 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 74046 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2823576 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2897622 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.041866 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.058875 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.058345 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009850 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.009850 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.041866 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.049816 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.049613 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.041866 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.049816 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.049613 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71472.006774 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70762.437091 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70778.305293 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4999.666667 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4999.666667 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80358.678342 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80358.678342 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71120.775640 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71472.006774 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71113.034871 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71120.775640 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 8362 # number of cycles access was blocked
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.blocked::no_mshrs 219 # number of cycles access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 38.182648 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.writebacks::writebacks 303849 # number of writebacks
system.cpu.l2cache.writebacks::total 303849 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 992 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5184 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 6176 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1526 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 1526 # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 992 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6710 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 7702 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 992 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6710 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 7702 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2108 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 130337 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 132445 # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 365353 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 365353 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3613 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3613 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2108 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 133950 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 136058 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2108 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 133950 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 365353 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 501411 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154832998 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8096605997 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8251438995 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21877894699 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 18003 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 18003 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 231375752 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 231375752 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154832998 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8327981749 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8482814747 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154832998 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8327981749 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21877894699 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 30360709446 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.056623 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.055746 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006925 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006925 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.046955 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028469 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047440 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173042 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73450.188805 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62120.549015 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62300.872022 # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.replacements 2823064 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits
system.cpu.dcache.overall_hits::total 166678355 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses
system.cpu.dcache.overall_misses::total 7049008 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks
system.cpu.dcache.writebacks::total 2348838 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
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