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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

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X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
---------- Begin Simulation Statistics ----------
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
sim_seconds 5.132858 # Number of seconds simulated
sim_ticks 5132857897000 # Number of ticks simulated
final_tick 5132857897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
host_inst_rate 156379 # Simulator instruction rate (inst/s)
host_op_rate 309121 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1967786651 # Simulator tick rate (ticks/s)
host_mem_usage 752412 # Number of bytes of host memory used
host_seconds 2608.44 # Real time elapsed on the host
sim_insts 407905700 # Number of instructions simulated
sim_ops 806325509 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2501312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.bytes_read::cpu.inst 1078144 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10788736 # Number of bytes read from this memory
system.physmem.bytes_read::total 14371776 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1078144 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1078144 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9560192 # Number of bytes written to this memory
system.physmem.bytes_written::total 9560192 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 39083 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.num_reads::cpu.inst 16846 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168574 # Number of read requests responded to by this memory
system.physmem.num_reads::total 224559 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 149378 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149378 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 487314 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 623 # Total read bandwidth from this memory (bytes/s)
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.bw_read::cpu.inst 210048 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2101896 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2799956 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 210048 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 210048 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1862548 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1862548 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1862548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 487314 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 623 # Total bandwidth to/from this memory (bytes/s)
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.bw_total::cpu.inst 210048 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2101896 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4662504 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 224559 # Total number of read requests seen
system.physmem.writeReqs 149378 # Total number of write requests seen
system.physmem.cpureqs 379116 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 14371776 # Total number of bytes read from memory
system.physmem.bytesWritten 9560192 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 14371776 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 9560192 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 86 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 3988 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 14046 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 12988 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 13113 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 16256 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 13686 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 13149 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 13495 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 13981 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 13311 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 13328 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 15635 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 13184 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 12667 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 13446 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 15958 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 9012 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 8453 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 8452 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 11545 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 8811 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 8570 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 8847 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 11675 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 9048 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 8676 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 8758 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 11176 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 8354 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 8087 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 8705 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 11209 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.numWrRetry 1191 # Number of times wr buffer was full causing retry
system.physmem.totGap 5132857844500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.readPktSize::6 224559 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.writePktSize::6 149378 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 172944 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 19784 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 7536 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3483 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3003 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1885 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1824 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1768 # What read queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.rdQLenPdf::10 1142 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1043 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 975 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 814 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 816 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 857 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 400 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 249 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.wrQLenPdf::0 5358 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5717 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 6325 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 6471 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 6478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6495 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6494 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 1137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 778 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 100 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
system.physmem.totQLat 4795272000 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 9305637000 # Sum of mem lat for all requests
system.physmem.totBusLat 1122365000 # Total cycles spent in databus access
system.physmem.totBankLat 3388000000 # Total cycles spent in bank access
system.physmem.avgQLat 21362.36 # Average queueing delay per request
system.physmem.avgBankLat 15093.13 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.avgMemAccLat 41455.48 # Average memory access latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdQLen 0.00 # Average read queue length over time
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.physmem.avgWrQLen 11.03 # Average write queue length over time
system.physmem.readRowHits 193515 # Number of row buffer hits during reads
system.physmem.writeRowHits 105640 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.21 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 70.72 # Row buffer hit rate for writes
system.physmem.avgGap 13726531.06 # Average gap between requests
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.replacements 47576 # number of replacements
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.tagsinuse 0.103924 # Cycle average of tags in use
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.occ_blocks::pc.south_bridge.ide 0.103924 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.006495 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.006495 # Average percentage of cache occupancy
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
system.iocache.overall_misses::total 47631 # number of overall misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146639932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 146639932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10056560160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10056560160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10203200092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10203200092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10203200092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10203200092 # number of overall miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160965.896817 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 160965.896817 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215251.715753 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 215251.715753 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 214213.434360 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 214213.434360 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 137627 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.blocked::no_mshrs 12509 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 11.002238 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99246962 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 99246962 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7625786368 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 7625786368 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 7725033330 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 7725033330 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108942.878156 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 108942.878156 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163223.167123 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 163223.167123 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.branchPred.lookups 86194611 # Number of BP lookups
system.cpu.branchPred.condPredicted 86194611 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1105724 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 81284951 # Number of BTB lookups
system.cpu.branchPred.BTBHits 79210874 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.branchPred.BTBHitPct 97.448387 # BTB Hit Percentage
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.numCycles 448157181 # number of cpu cycles simulated
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.fetch.icacheStallCycles 27411589 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 425916361 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86194611 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79210874 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 163569758 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4698258 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 127091 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 63100705 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 36134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 51634 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 488 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9006921 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 482292 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 2784 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 257851520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.260962 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.418035 # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.fetch.rateDist::0 94708741 36.73% 36.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1565189 0.61% 37.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 71915500 27.89% 65.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 936812 0.36% 65.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1597915 0.62% 66.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2418163 0.94% 67.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1071060 0.42% 67.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1376608 0.53% 68.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 82261532 31.90% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.fetch.rateDist::total 257851520 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.192331 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.950373 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31130056 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 60542452 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 159362996 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3261895 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3554121 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 837710983 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 948 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3554121 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 33866246 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 37401594 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 11010183 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 159560886 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 12458490 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 834077749 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19680 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5867270 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4756403 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 8649 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 995584301 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1810575684 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1810574876 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 808 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 964290633 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 31293661 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 458949 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 466891 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 28798932 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 17055930 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10122177 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1247187 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 990912 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 827964566 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1250540 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 823033686 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 148209 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 21990342 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33439565 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 197993 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 257851520 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 3.191890 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.384052 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iq.issued_per_cycle::0 71392246 27.69% 27.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 15523930 6.02% 33.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10289230 3.99% 37.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7461063 2.89% 40.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 75902807 29.44% 70.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3840005 1.49% 71.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72510870 28.12% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 779318 0.30% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 152051 0.06% 100.00% # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iq.issued_per_cycle::total 257851520 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iq.fu_full::IntAlu 361997 33.96% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 553138 51.89% 85.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 150897 14.16% 100.00% # attempts to use FU when none available
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iq.FU_type_0::No_OpClass 310952 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 795510781 96.66% 96.69% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iq.FU_type_0::MemRead 17835089 2.17% 98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9376864 1.14% 100.00% # Type of FU issued
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iq.FU_type_0::total 823033686 # Type of FU issued
system.cpu.iq.rate 1.836484 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1066032 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001295 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1905263509 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 851215281 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 818564848 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 272 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 823788636 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1638773 # Number of loads that had data forwarded from stores
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 3081166 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 22705 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11479 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1710957 # Number of stores squashed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1932446 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12217 # Number of times an access to memory failed due to the cache being blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iew.iewSquashCycles 3554121 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 26141117 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 2116575 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 829215106 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 320591 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 17055930 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10122177 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 718653 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1615740 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 10506 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11479 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 648838 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 592977 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1241815 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 821161230 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 17423630 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1872455 # Number of squashed instructions skipped in execute
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iew.exec_refs 26568531 # number of memory reference insts executed
system.cpu.iew.exec_branches 83193011 # Number of branches executed
system.cpu.iew.exec_stores 9144901 # Number of stores executed
system.cpu.iew.exec_rate 1.832306 # Inst execution rate
system.cpu.iew.wb_sent 820700229 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 818564922 # cumulative count of insts written-back
system.cpu.iew.wb_producers 639778882 # num instructions producing a value
system.cpu.iew.wb_consumers 1045529467 # num instructions consuming a value
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.iew.wb_rate 1.826513 # insts written-back per cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.commitSquashedInsts 22781132 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1052545 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1110334 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 254297399 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 3.170797 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.853937 # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.committed_per_cycle::0 82526547 32.45% 32.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11810769 4.64% 37.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3910269 1.54% 38.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74942576 29.47% 68.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2436425 0.96% 69.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1481605 0.58% 69.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 941054 0.37% 70.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 70918807 27.89% 97.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5329347 2.10% 100.00% # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.committed_per_cycle::total 254297399 # Number of insts commited each cycle
system.cpu.commit.committedInsts 407905700 # Number of instructions committed
system.cpu.commit.committedOps 806325509 # Number of ops (including micro ops) committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.refs 22385981 # Number of memory references committed
system.cpu.commit.loads 13974761 # Number of loads committed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.commit.membars 473457 # Number of memory barriers committed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.branches 82185695 # Number of branches committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.int_insts 735267209 # Number of committed integer instructions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.function_calls 0 # Number of function calls committed.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.commit.bw_lim_events 5329347 # number cycles where commit BW limit reached
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.rob.rob_reads 1077996488 # The number of ROB reads
system.cpu.rob.rob_writes 1661786087 # The number of ROB writes
system.cpu.timesIdled 1219722 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 190305661 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9817556036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 407905700 # Number of Instructions Simulated
system.cpu.committedOps 806325509 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 407905700 # Number of Instructions Simulated
system.cpu.cpi 1.098678 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.098678 # CPI: Total CPI of All Threads
system.cpu.ipc 0.910184 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.910184 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1506617542 # number of integer regfile reads
system.cpu.int_regfile_writes 976738350 # number of integer regfile writes
system.cpu.fp_regfile_reads 74 # number of floating regfile reads
system.cpu.misc_regfile_reads 264608213 # number of misc regfile reads
system.cpu.misc_regfile_writes 402112 # number of misc regfile writes
system.cpu.icache.replacements 1045620 # number of replacements
system.cpu.icache.tagsinuse 510.123573 # Cycle average of tags in use
system.cpu.icache.total_refs 7898000 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1046132 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.549716 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.icache.occ_blocks::cpu.inst 510.123573 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996335 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996335 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7898000 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7898000 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7898000 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7898000 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7898000 # number of overall hits
system.cpu.icache.overall_hits::total 7898000 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1108918 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1108918 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1108918 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1108918 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1108918 # number of overall misses
system.cpu.icache.overall_misses::total 1108918 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15254848492 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15254848492 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15254848492 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15254848492 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15254848492 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15254848492 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9006918 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9006918 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9006918 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9006918 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9006918 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9006918 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123118 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.123118 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.123118 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.123118 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.123118 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.123118 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13756.516255 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13756.516255 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13756.516255 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13756.516255 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 9824 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 33.189189 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60463 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 60463 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 60463 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 60463 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 60463 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 60463 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048455 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1048455 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1048455 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1048455 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1048455 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1048455 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12565081992 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12565081992 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12565081992 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12565081992 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12565081992 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12565081992 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116406 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.116406 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.116406 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11984.378912 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11984.378912 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.itb_walker_cache.replacements 9450 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.008249 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 25808 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 9463 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.727254 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5103990002500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008249 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375516 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.375516 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25828 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 25828 # number of ReadReq hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25830 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 25830 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25830 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 25830 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10341 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 10341 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10341 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 10341 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10341 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 10341 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 115658000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 115658000 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 115658000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 115658000 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 115658000 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 115658000 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36169 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 36169 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36171 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 36171 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36171 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 36171 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285908 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285908 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285892 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.285892 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285892 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.285892 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11184.411566 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11184.411566 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11184.411566 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11184.411566 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.itb_walker_cache.writebacks::writebacks 1982 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 1982 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10341 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10341 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10341 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 10341 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10341 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 10341 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94976000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94976000 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94976000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94976000 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94976000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94976000 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285908 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285908 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285892 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285892 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9184.411566 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dtb_walker_cache.replacements 109668 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 12.956689 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 133742 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 109682 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.219361 # Average number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.956689 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809793 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.809793 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133765 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 133765 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133765 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 133765 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133765 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 133765 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110693 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 110693 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110693 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 110693 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110693 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 110693 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1390562000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1390562000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1390562000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 1390562000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1390562000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 1390562000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244458 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 244458 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244458 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 244458 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244458 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 244458 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452810 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452810 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452810 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452810 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452810 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452810 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12562.330048 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12562.330048 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12562.330048 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12562.330048 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dtb_walker_cache.writebacks::writebacks 35480 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 35480 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110693 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110693 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110693 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 110693 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110693 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 110693 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1169176000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1169176000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1169176000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452810 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452810 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452810 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.330048 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dcache.replacements 1659150 # number of replacements
system.cpu.dcache.tagsinuse 511.992464 # Cycle average of tags in use
system.cpu.dcache.total_refs 19077771 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1659662 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.494974 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dcache.occ_blocks::cpu.data 511.992464 # Average occupied blocks per requestor
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dcache.ReadReq_hits::cpu.data 10988579 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10988579 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8084208 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8084208 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 19072787 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19072787 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19072787 # number of overall hits
system.cpu.dcache.overall_hits::total 19072787 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2233798 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2233798 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 317777 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 317777 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2551575 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2551575 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2551575 # number of overall misses
system.cpu.dcache.overall_misses::total 2551575 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32133763000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32133763000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9654013491 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9654013491 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 41787776491 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 41787776491 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 41787776491 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 41787776491 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13222377 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13222377 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8401985 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8401985 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21624362 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21624362 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21624362 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21624362 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168941 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.168941 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037822 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037822 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.117995 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.117995 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.117995 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.117995 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14385.259097 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14385.259097 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30379.837090 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30379.837090 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16377.247971 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16377.247971 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 403205 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.479816 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.dcache.writebacks::writebacks 1560680 # number of writebacks
system.cpu.dcache.writebacks::total 1560680 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862352 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 862352 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25015 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 25015 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 887367 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 887367 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 887367 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 887367 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371446 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1371446 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292762 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 292762 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1664208 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1664208 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1664208 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1664208 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17485386500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17485386500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8810445491 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8810445491 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26295831991 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26295831991 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26295831991 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26295831991 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296686000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296686000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470456500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470456500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767142500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767142500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103722 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103722 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034844 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.076960 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076960 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12749.598963 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12749.598963 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30094.224971 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30094.224971 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15800.808547 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15800.808547 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15800.808547 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15800.808547 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.replacements 113397 # number of replacements
system.cpu.l2cache.tagsinuse 64842.962658 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3927368 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 177482 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.128261 # Average number of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.occ_blocks::writebacks 50042.897281 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.875640 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.131992 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3274.977227 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 11514.080519 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.763594 # Average percentage of cache occupancy
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy
stats: Update the stats to reflect the 1GHz default system clock This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25 19:15:59 +02:00
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.occ_percent::cpu.inst 0.049972 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.175691 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.989425 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103288 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8019 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 1029235 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1333401 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2473943 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1598142 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1598142 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 335 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 335 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 156168 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 156168 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 103288 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 8019 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1029235 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1489569 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2630111 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 103288 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 8019 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1029235 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1489569 # number of overall hits
system.cpu.l2cache.overall_hits::total 2630111 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 50 # number of ReadReq misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 16847 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 36871 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 53774 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3714 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 3714 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 132646 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 132646 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 50 # number of demand (read+write) misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 16847 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 169517 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 186420 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 50 # number of overall misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 16847 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169517 # number of overall misses
system.cpu.l2cache.overall_misses::total 186420 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6252000 # number of ReadReq miss cycles
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1171120500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2550395499 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3728157499 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17029000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 17029000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6863407500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6863407500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6252000 # number of demand (read+write) miss cycles
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 1171120500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9413802999 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10591564999 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6252000 # number of overall miss cycles
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 1171120500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9413802999 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10591564999 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103338 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8025 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046082 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1370272 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2527717 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1598142 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1598142 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4049 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 4049 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 288814 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 288814 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103338 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 8025 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1046082 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1659086 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2816531 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103338 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 8025 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1046082 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1659086 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2816531 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000748 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016105 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021274 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.917264 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.917264 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459278 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.459278 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000748 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016105 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102175 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.066188 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000748 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016105 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102175 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.066188 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 125040 # average ReadReq miss latency
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69515.076868 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69170.771040 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69330.113047 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4585.083468 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4585.083468 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51742.287743 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51742.287743 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 125040 # average overall miss latency
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69515.076868 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55533.091071 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56815.604544 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 125040 # average overall miss latency
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69515.076868 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55533.091071 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56815.604544 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.writebacks::writebacks 102711 # number of writebacks
system.cpu.l2cache.writebacks::total 102711 # number of writebacks
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 50 # number of ReadReq MSHR misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16846 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36870 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 53772 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3714 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3714 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132646 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 132646 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 50 # number of demand (read+write) MSHR misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16846 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 169516 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 186418 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 50 # number of overall MSHR misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16846 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169516 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 186418 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5629796 # number of ReadReq MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 961575741 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2092180467 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3059700259 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 38132194 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 38132194 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5227507665 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5227507665 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5629796 # number of demand (read+write) MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 961575741 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7319688132 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8287207924 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5629796 # number of overall MSHR miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 961575741 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7319688132 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8287207924 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187404000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187404000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308295000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308295000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495699000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495699000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026907 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021273 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.917264 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.917264 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459278 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459278 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102174 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.066187 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000748 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016104 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102174 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.066187 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average ReadReq mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57080.359789 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56744.791619 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56901.366120 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10267.149704 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10267.149704 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39409.463271 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39409.463271 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
stats: update patches for branch predictor and fetch updates.
2013-03-05 05:33:47 +01:00
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink