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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

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X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
sim_seconds 5.136865 # Number of seconds simulated
sim_ticks 5136864535500 # Number of ticks simulated
final_tick 5136864535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
host_inst_rate 199949 # Simulator instruction rate (inst/s)
host_op_rate 395248 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2517891877 # Simulator tick rate (ticks/s)
host_mem_usage 755196 # Number of bytes of host memory used
host_seconds 2040.15 # Real time elapsed on the host
sim_insts 407925588 # Number of instructions simulated
sim_ops 806363480 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2498048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bytes_read::cpu.inst 1077760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10804608 # Number of bytes read from this memory
system.physmem.bytes_read::total 14383936 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1077760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1077760 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9566528 # Number of bytes written to this memory
system.physmem.bytes_written::total 9566528 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 39032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.num_reads::cpu.inst 16840 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168822 # Number of read requests responded to by this memory
system.physmem.num_reads::total 224749 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 149477 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149477 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 486298 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s)
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_read::cpu.inst 209809 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2103347 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2800139 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 209809 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 209809 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1862328 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1862328 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1862328 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 486298 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s)
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.bw_total::cpu.inst 209809 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2103347 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4662468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 224749 # Total number of read requests seen
system.physmem.writeReqs 149477 # Total number of write requests seen
system.physmem.cpureqs 378758 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 14383936 # Total number of bytes read from memory
system.physmem.bytesWritten 9566528 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 14383936 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 9566528 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 3970 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 14108 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 13038 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 13174 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 16315 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 13707 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 13158 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 13525 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 16255 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 13935 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 13285 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 13290 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 15648 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 13203 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 12660 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 13428 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 15923 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 9005 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 8432 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 8529 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 11625 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 8800 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 8560 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 8903 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 11692 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 9007 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 8684 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 8693 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 11170 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 8382 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 8108 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 8695 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 11192 # Track writes on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.numWrRetry 562 # Number of times wr buffer was full causing retry
system.physmem.totGap 5136864483000 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.readPktSize::6 224749 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 149477 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 173174 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 19685 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3521 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3015 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2402 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1894 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1830 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1773 # What read queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.rdQLenPdf::10 1145 # What read queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.rdQLenPdf::12 964 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 885 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 809 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 906 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 870 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 386 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 240 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::0 5359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 5713 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 6316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 6398 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 6438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 6479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 6486 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 6489 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 6490 # What write queue length does an incoming req see
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.wrQLenPdf::23 1140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 786 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
system.physmem.totQLat 4764271250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 9277483750 # Sum of mem lat for all requests
system.physmem.totBusLat 1123260000 # Total cycles spent in databus access
system.physmem.totBankLat 3389952500 # Total cycles spent in bank access
system.physmem.avgQLat 21207.34 # Average queueing delay per request
system.physmem.avgBankLat 15089.79 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgMemAccLat 41297.13 # Average memory access latency
system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
x86 regressions: updates due to new instructions and cpuid
2013-01-15 14:43:23 +01:00
system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgRdQLen 0.00 # Average read queue length over time
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.avgWrQLen 11.02 # Average write queue length over time
system.physmem.readRowHits 193727 # Number of row buffer hits during reads
system.physmem.writeRowHits 105780 # Number of row buffer hits during writes
system.physmem.readRowHitRate 86.23 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 70.77 # Row buffer hit rate for writes
system.physmem.avgGap 13726637.07 # Average gap between requests
system.iocache.replacements 47576 # number of replacements
system.iocache.tagsinuse 0.116322 # Cycle average of tags in use
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.total_refs 0 # Total number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.avg_refs 0 # Average number of references to valid blocks.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::pc.south_bridge.ide 0.116322 # Average occupied blocks per requestor
system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
system.iocache.overall_misses::total 47631 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 151593932 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 151593932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10023192160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10023192160 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 10174786092 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 10174786092 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 10174786092 # number of overall miss cycles
system.iocache.overall_miss_latency::total 10174786092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166403.877058 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 166403.877058 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214537.503425 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 214537.503425 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 213616.890093 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213616.890093 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 213616.890093 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 136470 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.blocked::no_mshrs 12410 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 10.996777 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104200712 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 104200712 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7592410619 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 7592410619 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 7696611331 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7696611331 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 7696611331 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114380.583974 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 114380.583974 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162508.788934 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 162508.788934 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161588.279293 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 161588.279293 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Regression: Update statistics for x86 long regression tests This patch updates reference statistics for the regression tests. This update was necessitated by a recent change in behavior of some instructions in the x86 architecture.
2011-11-18 05:53:56 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.branchPred.lookups 86198193 # Number of BP lookups
system.cpu.branchPred.condPredicted 86198193 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1106234 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 81290548 # Number of BTB lookups
system.cpu.branchPred.BTBHits 79213904 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.branchPred.BTBHitPct 97.445405 # BTB Hit Percentage
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.numCycles 448153841 # number of cpu cycles simulated
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.fetch.icacheStallCycles 27415171 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 425937394 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86198193 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 79213904 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 163576958 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4698498 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 117961 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 63103393 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 36350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 51299 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 9010068 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 483485 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 3126 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 257855511 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 3.261045 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.418033 # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.fetch.rateDist::0 94705411 36.73% 36.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1566235 0.61% 37.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 71918028 27.89% 65.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 935930 0.36% 65.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1598963 0.62% 66.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2419267 0.94% 67.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 1070398 0.42% 67.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 1376464 0.53% 68.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 82264815 31.90% 100.00% # Number of instructions fetched each cycle (Total)
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.fetch.rateDist::total 257855511 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.192341 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.950427 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31132857 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 60536501 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 159370274 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3261936 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3553943 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 837748670 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 951 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3553943 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 33869883 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 37385632 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 11021591 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 159568277 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 12456185 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 834115262 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 19668 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5867494 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 4754545 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 8312 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 995635482 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1810665967 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1810665163 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 804 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 964341342 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 31294133 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 459159 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 467055 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 28798095 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 17056943 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 10123506 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1248285 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 987203 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 827998215 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1251183 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 823066756 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 148002 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 21984557 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33441202 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 198541 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 257855511 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 3.191969 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 2.384014 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iq.issued_per_cycle::0 71390186 27.69% 27.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 15517919 6.02% 33.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 10294138 3.99% 37.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7464826 2.89% 40.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 75904474 29.44% 70.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 3838948 1.49% 71.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 72513480 28.12% 99.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 779753 0.30% 99.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 151787 0.06% 100.00% # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iq.issued_per_cycle::total 257855511 # Number of insts issued each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iq.fu_full::IntAlu 363612 34.06% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 553162 51.82% 85.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 150741 14.12% 100.00% # attempts to use FU when none available
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iq.FU_type_0::No_OpClass 311137 0.04% 0.04% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 795540449 96.66% 96.69% # Type of FU issued
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iq.FU_type_0::MemRead 17836742 2.17% 98.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 9378428 1.14% 100.00% # Type of FU issued
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iq.FU_type_0::total 823066756 # Type of FU issued
system.cpu.iq.rate 1.836572 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1067515 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1905334904 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 851243829 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 818598323 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 260 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 368 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 823823020 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 114 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1639481 # Number of loads that had data forwarded from stores
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 3079539 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 22701 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 11520 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1710580 # Number of stores squashed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 1932434 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 12204 # Number of times an access to memory failed due to the cache being blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iew.iewSquashCycles 3553943 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 26124965 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 2116869 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 829249398 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 321104 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 17056943 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 10123506 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 718931 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1615774 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 10404 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 11520 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 649169 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 592997 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1242166 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 821195112 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 17426068 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1871643 # Number of squashed instructions skipped in execute
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iew.exec_refs 26572625 # number of memory reference insts executed
system.cpu.iew.exec_branches 83197450 # Number of branches executed
system.cpu.iew.exec_stores 9146557 # Number of stores executed
system.cpu.iew.exec_rate 1.832396 # Inst execution rate
system.cpu.iew.wb_sent 820733466 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 818598386 # cumulative count of insts written-back
system.cpu.iew.wb_producers 639795417 # num instructions producing a value
system.cpu.iew.wb_consumers 1045555736 # num instructions consuming a value
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.iew.wb_rate 1.826601 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.commit.commitSquashedInsts 22777543 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1052640 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1110740 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 254301568 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 3.170895 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.853974 # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.commit.committed_per_cycle::0 82529406 32.45% 32.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 11802979 4.64% 37.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3912644 1.54% 38.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 74944166 29.47% 68.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 2437687 0.96% 69.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1481720 0.58% 69.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 940520 0.37% 70.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 70919321 27.89% 97.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 5333125 2.10% 100.00% # Number of insts commited each cycle
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.commit.committed_per_cycle::total 254301568 # Number of insts commited each cycle
system.cpu.commit.committedInsts 407925588 # Number of instructions committed
system.cpu.commit.committedOps 806363480 # Number of ops (including micro ops) committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.commit.refs 22390327 # Number of memory references committed
system.cpu.commit.loads 13977401 # Number of loads committed
system.cpu.commit.membars 473457 # Number of memory barriers committed
system.cpu.commit.branches 82191015 # Number of branches committed
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.commit.int_insts 735304742 # Number of committed integer instructions.
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.function_calls 0 # Number of function calls committed.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.commit.bw_lim_events 5333125 # number cycles where commit BW limit reached
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.rob.rob_reads 1078031216 # The number of ROB reads
system.cpu.rob.rob_writes 1661854677 # The number of ROB writes
system.cpu.timesIdled 1219790 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 190298330 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9825572650 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 407925588 # Number of Instructions Simulated
system.cpu.committedOps 806363480 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 407925588 # Number of Instructions Simulated
system.cpu.cpi 1.098617 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.098617 # CPI: Total CPI of All Threads
system.cpu.ipc 0.910236 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.910236 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1506687590 # number of integer regfile reads
system.cpu.int_regfile_writes 976781809 # number of integer regfile writes
system.cpu.fp_regfile_reads 63 # number of floating regfile reads
system.cpu.misc_regfile_reads 264621583 # number of misc regfile reads
system.cpu.misc_regfile_writes 402234 # number of misc regfile writes
system.cpu.icache.replacements 1045798 # number of replacements
system.cpu.icache.tagsinuse 510.125014 # Cycle average of tags in use
system.cpu.icache.total_refs 7900747 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1046310 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.551058 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.icache.occ_blocks::cpu.inst 510.125014 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 7900747 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 7900747 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 7900747 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 7900747 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 7900747 # number of overall hits
system.cpu.icache.overall_hits::total 7900747 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1109320 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1109320 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1109320 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1109320 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1109320 # number of overall misses
system.cpu.icache.overall_misses::total 1109320 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15268069493 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 15268069493 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 15268069493 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 15268069493 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 15268069493 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 15268069493 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9010067 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9010067 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9010067 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9010067 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9010067 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9010067 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123120 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.123120 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.123120 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.123120 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.123120 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.123120 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13763.449224 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13763.449224 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13763.449224 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13763.449224 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13763.449224 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 12508 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.icache.blocked::no_mshrs 293 # number of cycles access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 42.689420 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60685 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 60685 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 60685 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 60685 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 60685 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 60685 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048635 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1048635 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1048635 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1048635 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1048635 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1048635 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12573562493 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 12573562493 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12573562493 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 12573562493 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12573562493 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 12573562493 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116385 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.116385 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116385 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.116385 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11990.408954 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11990.408954 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11990.408954 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11990.408954 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.itb_walker_cache.replacements 9600 # number of replacements
system.cpu.itb_walker_cache.tagsinuse 6.016014 # Cycle average of tags in use
system.cpu.itb_walker_cache.total_refs 25681 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.sampled_refs 9614 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.avg_refs 2.671209 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.warmup_cycle 5103990045500 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.016014 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376001 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.occ_percent::total 0.376001 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25689 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 25689 # number of ReadReq hits
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25691 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 25691 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25691 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 25691 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10488 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 10488 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10488 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 10488 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10488 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 10488 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 116654500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 116654500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 116654500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 116654500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 116654500 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 116654500 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36177 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 36177 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36179 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 36179 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36179 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 36179 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.289908 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.289908 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.289892 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.289892 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.289892 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.289892 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11122.663997 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11122.663997 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11122.663997 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11122.663997 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11122.663997 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.itb_walker_cache.writebacks::writebacks 1936 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 1936 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10488 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10488 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10488 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 10488 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10488 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 10488 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 95678500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 95678500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 95678500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 95678500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 95678500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 95678500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.289908 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.289908 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.289892 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.289892 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.289892 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9122.663997 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9122.663997 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9122.663997 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dtb_walker_cache.replacements 108181 # number of replacements
system.cpu.dtb_walker_cache.tagsinuse 12.959012 # Cycle average of tags in use
system.cpu.dtb_walker_cache.total_refs 134869 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.sampled_refs 108196 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.246525 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959012 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809938 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.occ_percent::total 0.809938 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134886 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 134886 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134886 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 134886 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134886 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 134886 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109218 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 109218 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109218 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 109218 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109218 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 109218 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1375116000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1375116000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1375116000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 1375116000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1375116000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 1375116000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244104 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 244104 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244104 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 244104 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244104 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 244104 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447424 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447424 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447424 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447424 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447424 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447424 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12590.561995 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12590.561995 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12590.561995 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12590.561995 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12590.561995 # average overall miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dtb_walker_cache.writebacks::writebacks 35252 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 35252 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109218 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109218 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109218 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 109218 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109218 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 109218 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1156680000 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1156680000 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1156680000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1156680000 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447424 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447424 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447424 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447424 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10590.561995 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10590.561995 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10590.561995 # average overall mshr miss latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dcache.replacements 1660118 # number of replacements
system.cpu.dcache.tagsinuse 511.992206 # Cycle average of tags in use
system.cpu.dcache.total_refs 19078637 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1660630 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11.488795 # Average number of references to valid blocks.
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dcache.occ_blocks::cpu.data 511.992206 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 10987895 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 10987895 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8085738 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8085738 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 19073633 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 19073633 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 19073633 # number of overall hits
system.cpu.dcache.overall_hits::total 19073633 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2236252 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2236252 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 317957 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 317957 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2554209 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2554209 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2554209 # number of overall misses
system.cpu.dcache.overall_misses::total 2554209 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 32134007500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 32134007500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9664278994 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 9664278994 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 41798286494 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 41798286494 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 41798286494 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 41798286494 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13224147 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13224147 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8403695 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8403695 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21627842 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21627842 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21627842 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21627842 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169104 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.169104 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037835 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037835 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.118098 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.118098 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.118098 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.118098 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14369.582453 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14369.582453 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30394.924452 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30394.924452 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 16364.473892 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 16364.473892 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 16364.473892 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 400642 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dcache.blocked::no_mshrs 42486 # number of cycles access was blocked
X86 Regressions: Update stats due to introduction of TSO
2012-01-29 02:09:17 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.429977 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.dcache.writebacks::writebacks 1561388 # number of writebacks
system.cpu.dcache.writebacks::total 1561388 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864027 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 864027 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25006 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 25006 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 889033 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 889033 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 889033 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 889033 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1372225 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1372225 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292951 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 292951 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1665176 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1665176 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1665176 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1665176 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17481793000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17481793000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8820305494 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8820305494 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26302098494 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26302098494 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26302098494 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26302098494 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296698500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296698500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470686500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470686500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767385000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767385000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103767 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034860 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034860 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.076992 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076992 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076992 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12739.742389 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12739.742389 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30108.466925 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30108.466925 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15795.386490 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15795.386490 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.replacements 113561 # number of replacements
system.cpu.l2cache.tagsinuse 64842.483679 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3930962 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 177626 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 22.130555 # Average number of references to valid blocks.
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.occ_blocks::writebacks 50033.446344 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.888296 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133449 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 3280.677554 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 11517.338036 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.763450 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000166 # Average percentage of cache occupancy
stats: Update the stats to reflect the 1GHz default system clock This patch updates the stats to reflect the change in the default system clock from 1 THz to 1GHz. The changes are due to the DMA devices now injecting requests at a lower pace.
2012-10-25 19:15:59 +02:00
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.occ_percent::cpu.inst 0.050059 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.175741 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.989418 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102246 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8058 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 1029420 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1334149 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2473873 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1598576 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1598576 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 345 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 345 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 156103 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 156103 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 102246 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 8058 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1029420 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1490252 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2629976 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 102246 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 8058 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1029420 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1490252 # number of overall hits
system.cpu.l2cache.overall_hits::total 2629976 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 49 # number of ReadReq misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 16841 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 36881 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 53777 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 3693 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 3693 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 132888 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 132888 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 49 # number of demand (read+write) misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 16841 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 169769 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 186665 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 49 # number of overall misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 16841 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169769 # number of overall misses
system.cpu.l2cache.overall_misses::total 186665 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6312000 # number of ReadReq miss cycles
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177562500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2538376499 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3722640499 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16930000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 16930000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6874050999 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6874050999 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6312000 # number of demand (read+write) miss cycles
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_miss_latency::cpu.inst 1177562500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9412427498 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10596691498 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6312000 # number of overall miss cycles
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_miss_latency::cpu.inst 1177562500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9412427498 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10596691498 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 102295 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8064 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1046261 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1371030 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2527650 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1598576 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1598576 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4038 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 4038 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 288991 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 288991 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 102295 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 8064 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1046261 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1660021 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2816641 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 102295 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 8064 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1046261 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1660021 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2816641 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000479 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000744 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016096 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026900 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021275 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.914562 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.914562 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459834 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.459834 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000479 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000744 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016096 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102269 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.066272 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000479 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000744 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016096 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102269 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.066272 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 128816.326531 # average ReadReq miss latency
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69922.362093 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68826.129959 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69223.655076 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4584.348768 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4584.348768 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51728.154529 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51728.154529 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 56768.497029 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 128816.326531 # average overall miss latency
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69922.362093 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55442.557228 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56768.497029 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.writebacks::writebacks 102810 # number of writebacks
system.cpu.l2cache.writebacks::total 102810 # number of writebacks
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 49 # number of ReadReq MSHR misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16840 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36880 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 53775 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3693 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 3693 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132888 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 132888 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 49 # number of demand (read+write) MSHR misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 16840 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 169768 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 186663 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 49 # number of overall MSHR misses
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16840 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169768 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 186663 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5701045 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314255 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 968087231 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2080048452 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3054150983 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37901173 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37901173 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235111902 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235111902 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5701045 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314255 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 968087231 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7315160354 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8289262885 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5701045 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314255 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 968087231 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7315160354 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8289262885 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187415500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187415500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308505000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308505000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91495920500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91495920500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026899 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021275 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.914562 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.914562 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459834 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.066271 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000479 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000744 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016095 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102269 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.066271 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57487.365261 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56400.446095 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56794.997359 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10262.976713 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10262.976713 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39394.918292 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39394.918292 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116347.857143 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57487.365261 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43089.159052 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44407.637748 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add an X86_FS o3 regression.
2011-08-15 03:34:17 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink