sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt

798 lines
90 KiB
Plaintext
Raw Normal View History

Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
sim_seconds 0.000006 # Number of seconds simulated
sim_ticks 6408000 # Number of ticks simulated
final_tick 6408000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
host_inst_rate 494 # Simulator instruction rate (inst/s)
host_op_rate 494 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1327192 # Simulator tick rate (ticks/s)
host_mem_usage 215760 # Number of bytes of host memory used
host_seconds 4.83 # Real time elapsed on the host
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
sim_insts 2387 # Number of instructions simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
sim_ops 2387 # Number of ops (including micro ops) simulated
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 17472 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 273 # Number of read requests responded to by this memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bw_read::cpu.inst 1877652934 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 848938826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2726591760 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1877652934 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1877652934 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1877652934 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 848938826 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2726591760 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 273 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 17472 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 10 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 10 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 23 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 6357500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 273 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 137 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 90 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 1341773 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 7053773 # Sum of mem lat for all requests
system.physmem.totBusLat 1092000 # Total cycles spent in databus access
system.physmem.totBankLat 4620000 # Total cycles spent in bank access
system.physmem.avgQLat 4914.92 # Average queueing delay per request
system.physmem.avgBankLat 16923.08 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 25838.00 # Average memory access latency
system.physmem.avgRdBW 2726.59 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2726.59 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 17.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 1.10 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 229 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.88 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 23287.55 # Average gap between requests
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dtb.read_hits 718 # DTB read hits
system.cpu.dtb.read_misses 36 # DTB read misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.read_acv 1 # DTB read access violations
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dtb.read_accesses 754 # DTB read accesses
system.cpu.dtb.write_hits 382 # DTB write hits
system.cpu.dtb.write_misses 24 # DTB write misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dtb.write_accesses 406 # DTB write accesses
system.cpu.dtb.data_hits 1100 # DTB hits
system.cpu.dtb.data_misses 60 # DTB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dtb.data_acv 1 # DTB access violations
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dtb.data_accesses 1160 # DTB accesses
system.cpu.itb.fetch_hits 1042 # ITB hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.itb.fetch_misses 30 # ITB misses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.itb.fetch_accesses 1072 # ITB accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.numCycles 12817 # number of cpu cycles simulated
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.lookups 1162 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 576 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 259 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 820 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 228 # Number of BTB hits
tests: update tests because of changes in stat names and in the stats package
2009-03-07 23:30:55 +01:00
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.BPredUnit.usedRAS 224 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 4082 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 7077 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1162 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1223 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 261 # Number of cycles fetch has spent blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.PendingTrapStallCycles 857 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 1042 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 7043 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.004827 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.418564 # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::0 5820 82.64% 82.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 52 0.74% 83.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 133 1.89% 85.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 101 1.43% 86.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 157 2.23% 88.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 70 0.99% 89.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 69 0.98% 90.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 64 0.91% 91.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 577 8.19% 100.00% # Number of instructions fetched each cycle (Total)
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.fetch.rateDist::total 7043 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.090661 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.552157 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 5035 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 297 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 1173 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 15 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 523 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 176 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 84 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 6290 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 301 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 523 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 5140 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 24 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 214 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 1083 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 59 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 6004 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 4336 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 6797 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 6785 # Number of integer rename lookups
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rename.UndoneMaps 2568 # Number of HB maps that are undone due to squashing
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rename.skidInsts 172 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 984 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 506 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 5173 # Number of instructions added to the IQ (excludes non-spec)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.iqInstsIssued 4204 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 2615 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1486 # Number of squashed operands that are examined and possibly removed from graph
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::samples 7043 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.596905 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.307061 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::0 5344 75.88% 75.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 621 8.82% 84.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 394 5.59% 90.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 268 3.81% 94.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 205 2.91% 97.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 132 1.87% 98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 55 0.78% 99.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11 0.16% 99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.issued_per_cycle::total 7043 # Number of insts issued each cycle
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.fu_full::IntAlu 2 4.26% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.26% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 22 46.81% 51.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 23 48.94% 100.00% # attempts to use FU when none available
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::IntAlu 2977 70.81% 70.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 808 19.22% 90.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 418 9.94% 100.00% # Type of FU issued
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.FU_type_0::total 4204 # Type of FU issued
system.cpu.iq.rate 0.328002 # Inst issue rate
system.cpu.iq.fu_busy_cnt 47 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011180 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 15542 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 7792 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 3821 # Number of integer instruction queue wakeup accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iq.int_alu_accesses 4244 # Number of integer alu accesses
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 569 # Number of loads squashed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 212 # Number of stores squashed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.iewSquashCycles 523 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 12 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 5532 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 63 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 984 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 506 # Number of dispatched store instructions
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 160 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 221 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 4011 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 193 # Number of squashed instructions skipped in execute
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.exec_nop 353 # number of nop insts executed
system.cpu.iew.exec_refs 1161 # number of memory reference insts executed
system.cpu.iew.exec_branches 678 # Number of branches executed
system.cpu.iew.exec_stores 406 # Number of stores executed
system.cpu.iew.exec_rate 0.312944 # Inst execution rate
system.cpu.iew.wb_sent 3922 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 3827 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1795 # num instructions producing a value
system.cpu.iew.wb_consumers 2353 # num instructions consuming a value
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.iew.wb_rate 0.298588 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.762856 # average fanout of values written-back
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.commitSquashedInsts 2928 # The number of squashed insts skipped by commit
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 6520 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.395092 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.243251 # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::0 5631 86.37% 86.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 221 3.39% 89.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 313 4.80% 94.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 120 1.84% 96.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 64 0.98% 97.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 55 0.84% 98.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 34 0.52% 98.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 22 0.34% 99.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 60 0.92% 100.00% # Number of insts commited each cycle
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.committed_per_cycle::total 6520 # Number of insts commited each cycle
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 709 # Number of memory references committed
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.commit.loads 415 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.branches 396 # Number of branches committed
system.cpu.commit.fp_insts 6 # Number of committed floating point instructions.
system.cpu.commit.int_insts 2367 # Number of committed integer instructions.
system.cpu.commit.function_calls 71 # Number of function calls committed.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.rob.rob_reads 11717 # The number of ROB reads
system.cpu.rob.rob_writes 11541 # The number of ROB writes
system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 5774 # Total number of cycles that the CPU has spent unscheduled due to idling
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.committedInsts 2387 # Number of Instructions Simulated
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.cpi 5.369501 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.369501 # CPI: Total CPI of All Threads
system.cpu.ipc 0.186237 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.186237 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 4858 # number of integer regfile reads
system.cpu.int_regfile_writes 2964 # number of integer regfile writes
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 0 # number of replacements
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.tagsinuse 92.000483 # Cycle average of tags in use
system.cpu.icache.total_refs 799 # Total number of references to valid blocks.
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.avg_refs 4.250000 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.occ_blocks::cpu.inst 92.000483 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.044922 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.044922 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 799 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 799 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 799 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 799 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 799 # number of overall hits
system.cpu.icache.overall_hits::total 799 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 243 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 243 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 243 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 243 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 243 # number of overall misses
system.cpu.icache.overall_misses::total 243 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 7449000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 7449000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 7449000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 7449000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 7449000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 7449000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1042 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1042 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1042 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1042 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1042 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1042 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233205 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.233205 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.233205 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.233205 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.233205 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.233205 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30654.320988 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 30654.320988 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 30654.320988 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 30654.320988 # average overall miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 55 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 55 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 55 # number of overall MSHR hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5938000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 5938000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5938000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 5938000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5938000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 5938000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.180422 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.180422 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.180422 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31585.106383 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31585.106383 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.tagsinuse 44.834744 # Cycle average of tags in use
system.cpu.dcache.total_refs 777 # Total number of references to valid blocks.
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.avg_refs 9.141176 # Average number of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.occ_blocks::cpu.data 44.834744 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 564 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 564 # number of ReadReq hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_hits::cpu.data 777 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 777 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 777 # number of overall hits
system.cpu.dcache.overall_hits::total 777 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 120 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 120 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_misses::cpu.data 201 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 201 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 201 # number of overall misses
system.cpu.dcache.overall_misses::total 201 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3706500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 3706500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2874500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2874500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 6581000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 6581000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 6581000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 6581000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 684 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 684 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_accesses::cpu.data 978 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 978 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 978 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 978 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175439 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.175439 # miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.205521 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.205521 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.205521 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.205521 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30887.500000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 30887.500000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35487.654321 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35487.654321 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32741.293532 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32741.293532 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2417000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2417000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 953500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 953500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3370500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 3370500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3370500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 3370500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089181 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089181 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.086912 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.086912 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39622.950820 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39622.950820 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39729.166667 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39729.166667 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.tagsinuse 120.198004 # Cycle average of tags in use
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks.
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.occ_blocks::cpu.inst 92.103751 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 28.094254 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst 0.002811 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000857 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
system.cpu.l2cache.overall_misses::total 273 # number of overall misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5749500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2356000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 8105500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 928000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 928000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 5749500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 3284000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 9033500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 5749500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 3284000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 9033500 # number of overall miss cycles
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 30582.446809 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38622.950820 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 32552.208835 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38666.666667 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38666.666667 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 33089.743590 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 33089.743590 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5087760 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2153056 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7240816 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847024 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847024 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5087760 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3000080 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8087840 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5087760 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3000080 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8087840 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27062.553191 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35296 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29079.582329 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35292.666667 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35292.666667 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency
O3: Update stats for fetch and bp changes.
2011-07-10 19:56:09 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
Add o3-timing configuration for ALPHA_SE "Hello world" tests. build_opts/ALPHA_SE: Add O3CPU to default CPU model list. tests/SConscript: Add o3-timing configuration. --HG-- extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
2006-09-01 23:59:36 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink