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gem5/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt

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config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_seconds 1.286250 # Number of seconds simulated
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
sim_ticks 1286249817500 # Number of ticks simulated
final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
host_inst_rate 1412500 # Simulator instruction rate (inst/s)
host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1956550284 # Simulator tick rate (ticks/s)
host_mem_usage 303116 # Number of bytes of host memory used
host_seconds 657.41 # Real time elapsed on the host
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory
system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory
system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
tests: update tests for TLB unification
2009-04-09 07:21:30 +02:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.read_hits 237510597 # DTB read hits
system.cpu.dtb.read_misses 194650 # DTB read misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.read_acv 0 # DTB read access violations
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
system.cpu.dtb.write_hits 98301200 # DTB write hits
system.cpu.dtb.write_misses 6871 # DTB write misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.write_acv 0 # DTB write access violations
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
system.cpu.dtb.data_hits 335811797 # DTB hits
system.cpu.dtb.data_misses 201521 # DTB misses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.dtb.data_acv 0 # DTB access violations
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.dtb.data_accesses 336013318 # DTB accesses
system.cpu.itb.fetch_hits 928789151 # ITB hits
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.fetch_misses 105 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.itb.fetch_accesses 928789256 # ITB accesses
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.workload.num_syscalls 37 # Number of system calls
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.numCycles 2572499635 # number of cpu cycles simulated
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedInsts 928587629 # Number of instructions committed
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
system.cpu.num_int_insts 822136244 # number of integer instructions
system.cpu.num_fp_insts 33439365 # number of float instructions
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
system.cpu.num_mem_refs 336013318 # number of memory refs
system.cpu.num_load_insts 237705247 # Number of load instructions
system.cpu.num_store_insts 98308071 # Number of store instructions
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.num_idle_cycles 0 # Number of idle cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.num_busy_cycles 2572499635 # Number of busy cycles
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.Branches 123111018 # Number of branches fetched
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.op_class::total 928789150 # Class of executed instruction
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.replacements 776432 # number of replacements
system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks
system.cpu.dcache.writebacks::total 91660 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.replacements 4618 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits
system.cpu.icache.overall_hits::total 928782983 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
system.cpu.icache.overall_misses::total 6168 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.replacements 257900 # number of replacements
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996640 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 7386496 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 7386496 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 4015 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 489636 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 493651 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 91660 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 91660 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 4015 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 492002 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 496017 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 4015 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 492002 # number of overall hits
system.cpu.l2cache.overall_hits::total 496017 # number of overall hits
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 2153 # number of ReadReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.data 221878 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 224031 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_misses::cpu.data 288526 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 290679 # number of demand (read+write) misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses
system.cpu.l2cache.overall_misses::total 290679 # number of overall misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113033000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11648595000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 11761628000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499020000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3499020000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 113033000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 15147615000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 15260648000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 113033000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 91660 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 91660 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311839 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.312159 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.369655 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.369493 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221878 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 224031 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.data 288526 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 290679 # number of demand (read+write) MSHR misses
stats: Update stats for unified cache configuration This patch updates the stats to reflect the changes in the L2 MSHRs, as the latter are now uniform across the regressions.
2012-10-30 14:35:32 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
alpha:o3:simple: update simout/err files A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
2011-06-21 00:57:14 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 878356 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 878356 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 878356 # Request fanout histogram
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::ReadReq 224031 # Transaction distribution
system.membus.trans_dist::ReadResp 224031 # Transaction distribution
system.membus.trans_dist::Writeback 66683 # Transaction distribution
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 357362 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 357362 # Request fanout histogram
system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
config file updates --HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12 21:04:14 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink