2010-07-27 07:03:44 +02:00
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[root]
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type=Root
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children=system
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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2012-02-12 23:07:43 +01:00
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|
full_system=false
|
2014-01-24 22:29:33 +01:00
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|
sim_quantum=0
|
2011-02-08 04:23:13 +01:00
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|
time_sync_enable=false
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|
time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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2010-07-27 07:03:44 +02:00
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[system]
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|
type=System
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2013-09-28 21:25:17 +02:00
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children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
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2012-02-12 23:07:43 +01:00
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boot_osflags=a
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2013-09-28 21:25:17 +02:00
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cache_line_size=64
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clk_domain=system.clk_domain
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2014-01-24 22:29:33 +01:00
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|
eventq_index=0
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2012-02-12 23:07:43 +01:00
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|
init_param=0
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|
kernel=
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|
load_addr_mask=1099511627775
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2014-01-24 22:29:34 +01:00
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load_offset=0
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2010-07-27 07:03:44 +02:00
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|
mem_mode=atomic
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2013-01-24 19:29:00 +01:00
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mem_ranges=
|
2012-01-25 18:19:50 +01:00
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memories=system.physmem
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num_work_ids=16
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2012-02-12 23:07:43 +01:00
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readfile=
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symbolfile=
|
2011-02-08 04:23:13 +01:00
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|
work_begin_ckpt_count=0
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|
work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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|
work_end_ckpt_count=0
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|
work_end_exit_count=0
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work_item_id=-1
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2012-03-09 21:33:07 +01:00
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system_port=system.membus.slave[0]
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2010-07-27 07:03:44 +02:00
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2013-09-28 21:25:17 +02:00
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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2013-09-28 21:25:17 +02:00
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voltage_domain=system.voltage_domain
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2010-07-27 07:03:44 +02:00
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[system.cpu]
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type=AtomicSimpleCPU
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2014-01-24 22:29:34 +01:00
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children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload
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2010-07-27 07:03:44 +02:00
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checker=Null
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2013-09-28 21:25:17 +02:00
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clk_domain=system.cpu_clk_domain
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2010-07-27 07:03:44 +02:00
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cpu_id=0
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do_checkpoint_insts=true
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2012-02-12 23:07:43 +01:00
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do_quiesce=true
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2010-07-27 07:03:44 +02:00
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do_statistics_insts=true
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2014-01-24 22:29:34 +01:00
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dstage2_mmu=system.cpu.dstage2_mmu
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2010-07-27 07:03:44 +02:00
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dtb=system.cpu.dtb
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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2012-05-09 20:52:14 +02:00
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fastmem=false
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2010-07-27 07:03:44 +02:00
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function_trace=false
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function_trace_start=0
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2012-02-12 23:07:43 +01:00
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interrupts=system.cpu.interrupts
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2013-01-24 19:29:00 +01:00
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isa=system.cpu.isa
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2014-01-24 22:29:34 +01:00
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istage2_mmu=system.cpu.istage2_mmu
|
2010-07-27 07:03:44 +02:00
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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2012-02-12 23:07:43 +01:00
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profile=0
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2010-07-27 07:03:44 +02:00
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progress_interval=0
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2013-09-28 21:25:17 +02:00
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simpoint_interval=100000000
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simpoint_profile=false
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simpoint_profile_file=simpoint.bb.gz
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simpoint_start_insts=
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2010-07-27 07:03:44 +02:00
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simulate_data_stalls=false
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simulate_inst_stalls=false
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2013-01-24 19:29:00 +01:00
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switched_out=false
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2010-07-27 07:03:44 +02:00
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system=system
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tracer=system.cpu.tracer
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width=1
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workload=system.cpu.workload
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2012-03-09 21:33:07 +01:00
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dcache_port=system.membus.slave[2]
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icache_port=system.membus.slave[1]
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2010-07-27 07:03:44 +02:00
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|
2014-01-24 22:29:34 +01:00
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[system.cpu.dstage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
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tlb=system.cpu.dtb
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[system.cpu.dstage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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walker=system.cpu.dstage2_mmu.stage2_tlb.walker
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[system.cpu.dstage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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sys=system
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port=system.membus.slave[6]
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2010-07-27 07:03:44 +02:00
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[system.cpu.dtb]
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type=ArmTLB
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2012-02-12 23:07:43 +01:00
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children=walker
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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2014-01-24 22:29:34 +01:00
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is_stage2=false
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2010-07-27 07:03:44 +02:00
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size=64
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2012-02-12 23:07:43 +01:00
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walker=system.cpu.dtb.walker
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[system.cpu.dtb.walker]
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type=ArmTableWalker
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2013-09-28 21:25:17 +02:00
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clk_domain=system.cpu_clk_domain
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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2014-01-24 22:29:34 +01:00
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|
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is_stage2=false
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2012-09-25 18:49:41 +02:00
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num_squash_per_cycle=2
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2012-02-12 23:07:43 +01:00
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sys=system
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2012-03-09 21:33:07 +01:00
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port=system.membus.slave[4]
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2012-02-12 23:07:43 +01:00
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[system.cpu.interrupts]
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type=ArmInterrupts
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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2010-07-27 07:03:44 +02:00
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|
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|
2013-01-24 19:29:00 +01:00
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[system.cpu.isa]
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type=ArmISA
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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2013-01-24 19:29:00 +01:00
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|
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fpsid=1090793632
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2014-01-24 22:29:34 +01:00
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id_aa64afr0_el1=0
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id_aa64afr1_el1=0
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id_aa64dfr0_el1=1052678
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id_aa64dfr1_el1=0
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id_aa64isar0_el1=0
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id_aa64isar1_el1=0
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id_aa64mmfr0_el1=15728642
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id_aa64mmfr1_el1=0
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id_aa64pfr0_el1=17
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id_aa64pfr1_el1=0
|
2013-01-24 19:29:00 +01:00
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id_isar0=34607377
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id_isar1=34677009
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id_isar2=555950401
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id_isar3=17899825
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id_isar4=268501314
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id_isar5=0
|
2014-01-24 22:29:34 +01:00
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id_mmfr0=270536963
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2013-01-24 19:29:00 +01:00
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id_mmfr1=0
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id_mmfr2=19070976
|
2014-01-24 22:29:34 +01:00
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id_mmfr3=34611729
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2013-01-24 19:29:00 +01:00
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id_pfr0=49
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2014-01-24 22:29:34 +01:00
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id_pfr1=4113
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midr=1091551472
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system=system
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[system.cpu.istage2_mmu]
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type=ArmStage2MMU
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children=stage2_tlb
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eventq_index=0
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stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
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tlb=system.cpu.itb
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[system.cpu.istage2_mmu.stage2_tlb]
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type=ArmTLB
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children=walker
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eventq_index=0
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is_stage2=true
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size=32
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walker=system.cpu.istage2_mmu.stage2_tlb.walker
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[system.cpu.istage2_mmu.stage2_tlb.walker]
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type=ArmTableWalker
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clk_domain=system.cpu_clk_domain
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eventq_index=0
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is_stage2=true
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num_squash_per_cycle=2
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sys=system
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port=system.membus.slave[5]
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2013-01-24 19:29:00 +01:00
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|
2010-07-27 07:03:44 +02:00
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[system.cpu.itb]
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type=ArmTLB
|
2012-02-12 23:07:43 +01:00
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children=walker
|
2014-01-24 22:29:33 +01:00
|
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eventq_index=0
|
2014-01-24 22:29:34 +01:00
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is_stage2=false
|
2010-07-27 07:03:44 +02:00
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size=64
|
2012-02-12 23:07:43 +01:00
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walker=system.cpu.itb.walker
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[system.cpu.itb.walker]
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type=ArmTableWalker
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2013-09-28 21:25:17 +02:00
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clk_domain=system.cpu_clk_domain
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2014-01-24 22:29:33 +01:00
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eventq_index=0
|
2014-01-24 22:29:34 +01:00
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is_stage2=false
|
2012-09-25 18:49:41 +02:00
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num_squash_per_cycle=2
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2012-02-12 23:07:43 +01:00
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sys=system
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2012-03-09 21:33:07 +01:00
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port=system.membus.slave[3]
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2010-07-27 07:03:44 +02:00
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[system.cpu.tracer]
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type=ExeTracer
|
2014-01-24 22:29:33 +01:00
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eventq_index=0
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2010-07-27 07:03:44 +02:00
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[system.cpu.workload]
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type=LiveProcess
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cmd=parser 2.1.dict -batch
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2012-09-25 18:49:41 +02:00
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cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
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2010-07-27 07:03:44 +02:00
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egid=100
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env=
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errout=cerr
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euid=100
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2014-01-24 22:29:33 +01:00
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eventq_index=0
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executable=/dist/cpu2000/binaries/arm/linux/parser
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2010-07-27 07:03:44 +02:00
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gid=100
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2014-01-24 22:29:33 +01:00
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input=/dist/cpu2000/data/parser/mdred/input/parser.in
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2010-07-27 07:03:44 +02:00
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=114600000000
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system=system
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uid=100
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2013-09-28 21:25:17 +02:00
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[system.cpu_clk_domain]
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type=SrcClockDomain
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clock=500
|
2014-01-24 22:29:33 +01:00
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eventq_index=0
|
2013-09-28 21:25:17 +02:00
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voltage_domain=system.voltage_domain
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|
2010-07-27 07:03:44 +02:00
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[system.membus]
|
2012-06-05 07:23:16 +02:00
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type=CoherentBus
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2013-09-28 21:25:17 +02:00
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clk_domain=system.clk_domain
|
2014-01-24 22:29:33 +01:00
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eventq_index=0
|
2010-07-27 07:03:44 +02:00
|
|
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header_cycles=1
|
2013-09-28 21:25:17 +02:00
|
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system=system
|
2010-08-17 14:06:22 +02:00
|
|
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use_default_range=false
|
2012-09-25 18:49:41 +02:00
|
|
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width=8
|
|
|
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master=system.physmem.port
|
2014-01-24 22:29:34 +01:00
|
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|
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
|
2010-07-27 07:03:44 +02:00
|
|
|
|
|
|
|
[system.physmem]
|
2012-05-09 20:52:14 +02:00
|
|
|
type=SimpleMemory
|
2012-09-25 18:49:41 +02:00
|
|
|
bandwidth=73.000000
|
2013-09-28 21:25:17 +02:00
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2010-07-27 07:03:44 +02:00
|
|
|
latency=30000
|
|
|
|
latency_var=0
|
|
|
|
null=false
|
|
|
|
range=0:134217727
|
2012-03-09 21:33:07 +01:00
|
|
|
port=system.membus.master[0]
|
2010-07-27 07:03:44 +02:00
|
|
|
|
2013-09-28 21:25:17 +02:00
|
|
|
[system.voltage_domain]
|
|
|
|
type=VoltageDomain
|
2014-01-24 22:29:33 +01:00
|
|
|
eventq_index=0
|
2013-09-28 21:25:17 +02:00
|
|
|
voltage=1.000000
|
|
|
|
|