2007-02-01 00:47:23 +01:00
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---------- Begin Simulation Statistics ----------
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2011-09-13 18:58:09 +02:00
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sim_seconds 0.089480 # Number of seconds simulated
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sim_ticks 89480174500 # Number of ticks simulated
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2012-01-25 18:19:50 +01:00
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final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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2007-02-01 00:47:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2012-01-25 18:19:50 +01:00
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host_inst_rate 190161 # Simulator instruction rate (inst/s)
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host_tick_rate 45305657 # Simulator tick rate (ticks/s)
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host_mem_usage 214676 # Number of bytes of host memory used
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host_seconds 1975.03 # Real time elapsed on the host
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2011-07-10 19:56:09 +02:00
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sim_insts 375574794 # Number of instructions simulated
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2012-01-25 18:19:50 +01:00
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system.physmem.bytes_read 475840 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 7435 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 5317826 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 2458288 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 5317826 # Total bandwidth to/from this memory (bytes/s)
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2011-07-10 19:56:09 +02:00
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.read_hits 105444914 # DTB read hits
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system.cpu.dtb.read_misses 94699 # DTB read misses
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2011-08-19 22:08:08 +02:00
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system.cpu.dtb.read_acv 48617 # DTB read access violations
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.read_accesses 105539613 # DTB read accesses
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system.cpu.dtb.write_hits 79763652 # DTB write hits
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system.cpu.dtb.write_misses 1536 # DTB write misses
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2011-08-19 22:08:08 +02:00
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system.cpu.dtb.write_acv 1 # DTB write access violations
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.write_accesses 79765188 # DTB write accesses
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system.cpu.dtb.data_hits 185208566 # DTB hits
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system.cpu.dtb.data_misses 96235 # DTB misses
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2011-08-19 22:08:08 +02:00
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system.cpu.dtb.data_acv 48618 # DTB access violations
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2011-09-13 18:58:09 +02:00
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system.cpu.dtb.data_accesses 185304801 # DTB accesses
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system.cpu.itb.fetch_hits 57904086 # ITB hits
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system.cpu.itb.fetch_misses 346 # ITB misses
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2011-07-10 19:56:09 +02:00
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system.cpu.itb.fetch_acv 0 # ITB acv
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2011-09-13 18:58:09 +02:00
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system.cpu.itb.fetch_accesses 57904432 # ITB accesses
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2011-07-10 19:56:09 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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2011-09-13 18:58:09 +02:00
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system.cpu.numCycles 178960351 # number of cpu cycles simulated
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2011-07-10 19:56:09 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.lookups 56765606 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 33143039 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3552012 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 40427205 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 32022628 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-09-13 18:58:09 +02:00
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system.cpu.BPredUnit.usedRAS 10686505 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 1330 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 59866357 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 502938652 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 56765606 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 42709133 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 93526616 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 12701088 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 16326839 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 7643 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 57904086 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1110763 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 178838548 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.812250 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.245901 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::0 85311932 47.70% 47.70% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 8035871 4.49% 52.20% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 9868460 5.52% 57.71% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 6372149 3.56% 61.28% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 13508487 7.55% 68.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 9517347 5.32% 74.15% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 5905302 3.30% 77.46% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3555081 1.99% 79.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 36763919 20.56% 100.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-09-13 18:58:09 +02:00
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system.cpu.fetch.rateDist::total 178838548 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.317197 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.810336 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 65738845 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 12641259 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 87702735 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3649079 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 9106630 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 10252982 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 4580 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 491283130 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 12139 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 9106630 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 70077435 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 4396073 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 392991 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 87026850 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 7838569 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 478183111 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 34338 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 6474620 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 310467420 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 626927534 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 331115388 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 295812146 # Number of floating rename lookups
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
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2011-09-13 18:58:09 +02:00
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system.cpu.rename.UndoneMaps 50935101 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 38371 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 296 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 21811876 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 110641644 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 85552281 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 8662202 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 5906832 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 433013718 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 258 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 418626838 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 2003473 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 56038444 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 32198216 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 178838548 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.340809 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 2.008173 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::0 44336411 24.79% 24.79% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 29007268 16.22% 41.01% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 27775406 15.53% 56.54% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 26238037 14.67% 71.21% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 22251353 12.44% 83.66% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 15664112 8.76% 92.41% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 8263195 4.62% 97.03% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3972623 2.22% 99.26% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1330143 0.74% 100.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.issued_per_cycle::total 178838548 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-09-13 18:58:09 +02:00
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system.cpu.iq.fu_full::IntAlu 135690 1.14% 1.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 41926 0.35% 1.49% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 2442 0.02% 1.51% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 8992 0.08% 1.59% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 1877041 15.76% 17.34% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 1762283 14.79% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.14% # attempts to use FU when none available
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|
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system.cpu.iq.fu_full::SimdMult 0 0.00% 32.14% # attempts to use FU when none available
|
|
|
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 32.14% # attempts to use FU when none available
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|
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.14% # attempts to use FU when none available
|
|
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.14% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 5120089 42.98% 75.12% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 2964035 24.88% 100.00% # attempts to use FU when none available
|
2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
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system.cpu.iq.FU_type_0::IntAlu 164031789 39.18% 39.19% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::IntMult 2126165 0.51% 39.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatAdd 33716465 8.05% 47.75% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCmp 7893369 1.89% 49.64% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatCvt 2899949 0.69% 50.33% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatMult 16711518 3.99% 54.32% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatDiv 1573138 0.38% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.70% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 108174365 25.84% 80.54% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 81466499 19.46% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 418626838 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.339216 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 11912498 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.028456 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 681277012 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 289109429 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 241633599 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 348731183 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 199993522 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 164553982 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 252486483 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 178019272 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 13980098 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 15887158 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 143607 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 50570 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 12031553 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 233419 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 9106630 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2382208 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 372749 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 458676643 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2278358 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 110641644 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 85552281 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 258 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 129 # Number of times the IQ has become full, causing a stall
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 50570 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 3441219 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 544657 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3985876 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 409944817 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 105588265 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 8682021 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.exec_nop 25662667 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 185353481 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 48120403 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 79765216 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.290702 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 407421919 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 406187581 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 197894075 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 277422150 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.iew.wb_rate 2.269707 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 169731918 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.348790 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.858024 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 70140218 41.32% 41.32% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 25651558 15.11% 56.44% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 14667534 8.64% 65.08% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 12267165 7.23% 72.31% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 9098146 5.36% 77.67% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 6161287 3.63% 81.30% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 5543706 3.27% 84.56% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 3203239 1.89% 86.45% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 22999065 13.55% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.count 398664569 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 168275214 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 94754486 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 44587530 # Number of branches committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.int_insts 316365825 # Number of committed integer instructions.
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.commit.bw_lim_events 22999065 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.rob.rob_reads 605411260 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 926487800 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.committedInsts 375574794 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 2.098648 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 2.098648 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 409675274 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 175727060 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 159328411 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 105866122 # number of floating regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.replacements 2110 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1834.326922 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 57898804 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 57898804 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 5282 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1245 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1245 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1245 # number of overall MSHR hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 4037 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 4037 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 4037 # number of overall MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 123459000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 123459000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 123459000 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.replacements 793 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3296.196945 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 164730953 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 4193 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 39287.134033 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 3296.196945 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.804736 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 91229707 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 73501239 # number of WriteReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_hits 164730946 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 164730946 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1678 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 19489 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 21167 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 21167 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 55919500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 568883000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 624802500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 624802500 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 91231385 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.demand_accesses 164752113 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 164752113 # number of overall (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses
|
2011-08-19 22:08:08 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 29517.763500 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 29517.763500 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2600 # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.writebacks 671 # number of writebacks
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 680 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 16294 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 16974 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 16974 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 998 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_misses 4193 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 4193 # number of overall MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 31703500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 113133500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 144837000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 144837000 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.replacements 10 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 4007.455925 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 810 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.167114 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 3629.785283 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 377.670641 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.110772 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.occ_percent::1 0.011526 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.l2cache.ReadReq_hits 730 # number of ReadReq hits
|
|
|
|
|
system.cpu.l2cache.Writeback_hits 671 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 65 # number of ReadExReq hits
|
|
|
|
|
system.cpu.l2cache.demand_hits 795 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 795 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_misses 3130 # number of ReadExReq misses
|
|
|
|
|
system.cpu.l2cache.demand_misses 7435 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7435 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 148163500 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 108392000 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 256555500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 256555500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 5035 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.Writeback_accesses 671 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.demand_accesses 8230 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8230 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.855015 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.979656 # miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.903402 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.903402 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34506.455952 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34506.455952 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-09-13 18:58:09 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-02-01 00:47:23 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
