2007-02-01 00:47:23 +01:00
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---------- Begin Simulation Statistics ----------
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2011-08-19 22:08:06 +02:00
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sim_seconds 0.090508 # Number of seconds simulated
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sim_ticks 90508462500 # Number of ticks simulated
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2007-02-01 00:47:23 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-08-19 22:08:06 +02:00
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host_inst_rate 100669 # Simulator instruction rate (inst/s)
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host_tick_rate 24259753 # Simulator tick rate (ticks/s)
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host_mem_usage 252880 # Number of bytes of host memory used
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host_seconds 3730.81 # Real time elapsed on the host
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2011-07-10 19:56:09 +02:00
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sim_insts 375574794 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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2011-08-19 22:08:06 +02:00
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system.cpu.dtb.read_hits 105325909 # DTB read hits
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system.cpu.dtb.read_misses 93344 # DTB read misses
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system.cpu.dtb.read_acv 48634 # DTB read access violations
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system.cpu.dtb.read_accesses 105419253 # DTB read accesses
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system.cpu.dtb.write_hits 79718162 # DTB write hits
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system.cpu.dtb.write_misses 1558 # DTB write misses
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2011-07-10 19:56:09 +02:00
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system.cpu.dtb.write_acv 0 # DTB write access violations
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2011-08-19 22:08:06 +02:00
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system.cpu.dtb.write_accesses 79719720 # DTB write accesses
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system.cpu.dtb.data_hits 185044071 # DTB hits
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system.cpu.dtb.data_misses 94902 # DTB misses
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system.cpu.dtb.data_acv 48634 # DTB access violations
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system.cpu.dtb.data_accesses 185138973 # DTB accesses
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system.cpu.itb.fetch_hits 58032693 # ITB hits
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system.cpu.itb.fetch_misses 351 # ITB misses
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2011-07-10 19:56:09 +02:00
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system.cpu.itb.fetch_acv 0 # ITB acv
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2011-08-19 22:08:06 +02:00
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system.cpu.itb.fetch_accesses 58033044 # ITB accesses
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2011-07-10 19:56:09 +02:00
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 215 # Number of system calls
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2011-08-19 22:08:06 +02:00
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system.cpu.numCycles 181016927 # number of cpu cycles simulated
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2011-07-10 19:56:09 +02:00
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.lookups 56908652 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 33128839 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 3549307 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 40569971 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 32137344 # Number of BTB hits
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2009-03-07 23:30:55 +01:00
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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2011-08-19 22:08:06 +02:00
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system.cpu.BPredUnit.usedRAS 10736279 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 1343 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 59988242 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 503999677 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 56908652 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 42873623 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 93805949 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 12846494 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 17811682 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 7687 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 58032693 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1098562 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 180895317 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.786140 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.241759 # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::0 87089368 48.14% 48.14% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 8126413 4.49% 52.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 9953250 5.50% 58.14% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 6311167 3.49% 61.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 13618559 7.53% 69.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 9505792 5.25% 74.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 5896466 3.26% 77.67% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 3503145 1.94% 79.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 36891157 20.39% 100.00% # Number of instructions fetched each cycle (Total)
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2011-07-10 19:56:09 +02:00
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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2011-08-19 22:08:06 +02:00
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system.cpu.fetch.rateDist::total 180895317 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.314383 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.784268 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 66262768 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 13721794 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 87804231 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 3829220 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 9277304 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 10346731 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 4343 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 492360513 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 11994 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 9277304 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 70771279 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 4688791 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 402464 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 87101855 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 8653624 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 479416177 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 6 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 50185 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 7149377 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 311562327 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 628686073 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 332583088 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 296102985 # Number of floating rename lookups
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2011-07-10 19:56:09 +02:00
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system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed
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2011-08-19 22:08:06 +02:00
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system.cpu.rename.UndoneMaps 52030008 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 38365 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 280 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 23740235 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 110658167 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 85526614 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 15465988 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 10430696 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 434355597 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 252 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 419519707 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 1756806 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 57360180 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 32293778 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 180895317 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.319130 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.993104 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::0 44820498 24.78% 24.78% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 29979430 16.57% 41.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 28846817 15.95% 57.30% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 25627519 14.17% 71.46% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 22480714 12.43% 83.89% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 15907163 8.79% 92.68% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 8306052 4.59% 97.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 3747889 2.07% 99.35% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 1179235 0.65% 100.00% # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.issued_per_cycle::total 180895317 # Number of insts issued each cycle
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.fu_full::IntAlu 69354 0.60% 0.60% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 0.60% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 38404 0.33% 0.93% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 5709 0.05% 0.98% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 19332 0.17% 1.15% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 2037444 17.66% 18.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 875919 7.59% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.40% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 5719458 49.56% 75.96% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 2774394 24.04% 100.00% # attempts to use FU when none available
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2011-07-10 19:56:09 +02:00
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
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2011-08-19 22:08:06 +02:00
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system.cpu.iq.FU_type_0::IntAlu 164900286 39.31% 39.31% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 2243051 0.53% 39.85% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.85% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 33844550 8.07% 47.92% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 7897710 1.88% 49.80% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 2993735 0.71% 50.51% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 16825521 4.01% 54.52% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 1580906 0.38% 54.90% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.90% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.90% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.90% # Type of FU issued
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|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.90% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemRead 107841565 25.71% 80.61% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::MemWrite 81358802 19.39% 100.00% # Type of FU issued
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iq.FU_type_0::total 419519707 # Type of FU issued
|
|
|
|
|
system.cpu.iq.rate 2.317572 # Inst issue rate
|
|
|
|
|
system.cpu.iq.fu_busy_cnt 11540014 # FU busy when requested
|
|
|
|
|
system.cpu.iq.fu_busy_rate 0.027508 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.int_inst_queue_reads 685462958 # Number of integer instruction queue reads
|
|
|
|
|
system.cpu.iq.int_inst_queue_writes 291219348 # Number of integer instruction queue writes
|
|
|
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 242560611 # Number of integer instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.fp_inst_queue_reads 347768593 # Number of floating instruction queue reads
|
|
|
|
|
system.cpu.iq.fp_inst_queue_writes 200512633 # Number of floating instruction queue writes
|
|
|
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 164917620 # Number of floating instruction queue wakeup accesses
|
|
|
|
|
system.cpu.iq.int_alu_accesses 253759021 # Number of integer alu accesses
|
|
|
|
|
system.cpu.iq.fp_alu_accesses 177267119 # Number of floating point alu accesses
|
|
|
|
|
system.cpu.iew.lsq.thread0.forwLoads 14283738 # Number of loads that had data forwarded from stores
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.squashedLoads 15903681 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 169313 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 15968 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread0.squashedStores 12005886 # Number of stores squashed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 213972 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.iewSquashCycles 9277304 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewBlockCycles 2317535 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 350843 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 460018539 # Number of instructions dispatched to IQ
|
|
|
|
|
system.cpu.iew.iewDispSquashedInsts 2425230 # Number of squashed instructions skipped by dispatch
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 110658167 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispStoreInsts 85526614 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 252 # Number of dispatched non-speculative instructions
|
|
|
|
|
system.cpu.iew.iewIQFullEvents 132 # Number of times the IQ has become full, causing a stall
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.memOrderViolationEvents 15968 # Number of memory order violations
|
|
|
|
|
system.cpu.iew.predictedTakenIncorrect 3438704 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 545017 # Number of branches that were predicted not taken incorrectly
|
|
|
|
|
system.cpu.iew.branchMispredicts 3983721 # Number of branch mispredicts detected at execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 411016170 # Number of executed instructions
|
|
|
|
|
system.cpu.iew.iewExecLoadInsts 105467950 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 8503537 # Number of squashed instructions skipped in execute
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.exec_nop 25662690 # number of nop insts executed
|
|
|
|
|
system.cpu.iew.exec_refs 185187689 # number of memory reference insts executed
|
|
|
|
|
system.cpu.iew.exec_branches 48286737 # Number of branches executed
|
|
|
|
|
system.cpu.iew.exec_stores 79719739 # Number of stores executed
|
|
|
|
|
system.cpu.iew.exec_rate 2.270595 # Inst execution rate
|
|
|
|
|
system.cpu.iew.wb_sent 408658291 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.wb_count 407478231 # cumulative count of insts written-back
|
|
|
|
|
system.cpu.iew.wb_producers 198809248 # num instructions producing a value
|
|
|
|
|
system.cpu.iew.wb_consumers 280006771 # num instructions consuming a value
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.iew.wb_rate 2.251050 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.wb_fanout 0.710016 # average fanout of values written-back
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.commitSquashedInsts 61360500 # The number of squashed insts skipped by commit
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.branchMispredicts 3545034 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.committed_per_cycle::samples 171618013 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::mean 2.322976 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::stdev 2.832511 # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::0 70646303 41.16% 41.16% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::1 26006834 15.15% 56.32% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::2 15503557 9.03% 65.35% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::3 13282401 7.74% 73.09% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::4 8794833 5.12% 78.22% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::5 6427011 3.74% 81.96% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::6 5152706 3.00% 84.96% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::7 2862149 1.67% 86.63% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::8 22942219 13.37% 100.00% # Number of insts commited each cycle
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
|
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.committed_per_cycle::total 171618013 # Number of insts commited each cycle
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.count 398664569 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.refs 168275214 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.loads 94754486 # Number of loads committed
|
|
|
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.branches 44587530 # Number of branches committed
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.int_insts 316365825 # Number of committed integer instructions.
|
2011-04-20 03:45:23 +02:00
|
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.commit.bw_lim_events 22942219 # number cycles where commit BW limit reached
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.rob.rob_reads 608697886 # The number of ROB reads
|
|
|
|
|
system.cpu.rob.rob_writes 929339596 # The number of ROB writes
|
|
|
|
|
system.cpu.timesIdled 2701 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.idleCycles 121610 # Total number of cycles that the CPU has spent unscheduled due to idling
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.committedInsts 375574794 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.cpi 0.481973 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 0.481973 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.ipc 2.074805 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 2.074805 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.int_regfile_reads 410790761 # number of integer regfile reads
|
|
|
|
|
system.cpu.int_regfile_writes 176550359 # number of integer regfile writes
|
|
|
|
|
system.cpu.fp_regfile_reads 159677516 # number of floating regfile reads
|
|
|
|
|
system.cpu.fp_regfile_writes 106247961 # number of floating regfile writes
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
|
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.replacements 2105 # number of replacements
|
|
|
|
|
system.cpu.icache.tagsinuse 1832.667923 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 58027410 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.sampled_refs 4031 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.avg_refs 14395.289010 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.occ_blocks::0 1832.667923 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.occ_percent::0 0.894857 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.ReadReq_hits 58027410 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.demand_hits 58027410 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.overall_hits 58027410 # number of overall hits
|
|
|
|
|
system.cpu.icache.ReadReq_misses 5283 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.demand_misses 5283 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.overall_misses 5283 # number of overall misses
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 167989000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_latency 167989000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_latency 167989000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 58032693 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.icache.demand_accesses 58032693 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_accesses 58032693 # number of overall (read+write) accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 31798.031422 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency 31798.031422 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency 31798.031422 # average overall miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_hits 1252 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 1252 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 1252 # number of overall MSHR hits
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 4031 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 4031 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 4031 # number of overall MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 123392000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_latency 123392000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_latency 123392000 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30610.766559 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 30610.766559 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 30610.766559 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.replacements 787 # number of replacements
|
|
|
|
|
system.cpu.dcache.tagsinuse 3295.378268 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 164327794 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.sampled_refs 4186 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.avg_refs 39256.520306 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.occ_blocks::0 3295.378268 # Average occupied blocks per context
|
|
|
|
|
system.cpu.dcache.occ_percent::0 0.804536 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 90826520 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_hits 73501267 # number of WriteReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_hits 164327787 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.overall_hits 164327787 # number of overall hits
|
|
|
|
|
system.cpu.dcache.ReadReq_misses 1669 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 19461 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.demand_misses 21130 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.overall_misses 21130 # number of overall misses
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 56052000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_miss_latency 568707000 # number of WriteReq miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 624759000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 624759000 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 90828189 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_accesses 164348917 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_accesses 164348917 # number of overall (read+write) accesses
|
2011-04-04 18:42:25 +02:00
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_miss_rate 0.000129 # miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.000129 # miss rate for overall accesses
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 33584.182145 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 29222.907353 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 29567.392333 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 29567.392333 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.writebacks 662 # number of writebacks
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 676 # number of ReadReq MSHR hits
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 16268 # number of WriteReq MSHR hits
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 16944 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 16944 # number of overall MSHR hits
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 993 # number of ReadReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 4186 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_misses 4186 # number of overall MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 31737500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 113123500 # number of WriteReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 144861000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 144861000 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
|
2008-02-26 08:20:40 +01:00
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31961.228600 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35428.593799 # average WriteReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 34606.067845 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 34606.067845 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.replacements 11 # number of replacements
|
|
|
|
|
system.cpu.l2cache.tagsinuse 4003.203107 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 792 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.sampled_refs 4846 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.avg_refs 0.163434 # Average number of references to valid blocks.
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.occ_blocks::0 3625.567893 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_blocks::1 377.635214 # Average occupied blocks per context
|
|
|
|
|
system.cpu.l2cache.occ_percent::0 0.110644 # Average percentage of cache occupancy
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.occ_percent::1 0.011525 # Average percentage of cache occupancy
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_hits 719 # number of ReadReq hits
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits
|
|
|
|
|
system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.demand_hits 781 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.overall_hits 781 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 4305 # number of ReadReq misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.demand_misses 7436 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.overall_misses 7436 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 148172000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_miss_latency 108394500 # number of ReadExReq miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 256566500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 256566500 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 5024 # number of ReadReq accesses(hits+misses)
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.cpu.l2cache.ReadExReq_accesses 3193 # number of ReadExReq accesses(hits+misses)
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.demand_accesses 8217 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_accesses 8217 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.856887 # miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_miss_rate 0.980583 # miss rate for ReadExReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 0.904953 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.904953 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34418.583043 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34619.770042 # average ReadExReq miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 34503.294782 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 34503.294782 # average overall miss latency
|
2010-09-09 20:40:19 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
2009-04-22 19:25:17 +02:00
|
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_misses 7436 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 7436 # number of overall MSHR misses
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 134317500 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 98537000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 232854500 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 232854500 # number of overall MSHR miss cycles
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.856887 # mshr miss rate for ReadReq accesses
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980583 # mshr miss rate for ReadExReq accesses
|
2011-08-19 22:08:06 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.904953 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.904953 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.348432 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31471.414883 # average ReadExReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31314.483593 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31314.483593 # average overall mshr miss latency
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
2007-02-01 00:47:23 +01:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-07-10 19:56:09 +02:00
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-02-01 00:47:23 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
